From: Andrew Stubbs <ams@codesourcery.com>
Date: Tue, 19 Jul 2022 10:14:28 +0000 (+0100)
Subject: amdgcn: 64-bit vector shifts
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e798cf3ce905a082f1b6b32015f30cea7d5f53a6;p=thirdparty%2Fgcc.git

amdgcn: 64-bit vector shifts

Enable 64-bit vector-vector and vector-scalar shifts.

gcc/ChangeLog:

	* config/gcn/gcn-valu.md (V_INT_noHI): New iterator.
	(<expander><mode>3<exec>): Use V_INT_noHI.
	(v<expander><mode>3<exec>): Likewise.

(cherry picked from commit 6e0ca3fe88d8f98ba6b4009c9483e87afbcf4ee8)
---

diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp
index c1de5d4f4ac5..a8ba3b5e78b4 100644
--- a/gcc/ChangeLog.omp
+++ b/gcc/ChangeLog.omp
@@ -1,3 +1,10 @@
+2022-08-02  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+	* config/gcn/gcn-valu.md (V_INT_noHI): New iterator.
+	(<expander><mode>3<exec>): Use V_INT_noHI.
+	(v<expander><mode>3<exec>): Likewise.
+
 2022-08-02  Andrew Stubbs  <ams@codesourcery.com>
 
 	Backport from mainline:
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index ec114db9dd1f..a3099f7db178 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -60,6 +60,8 @@
 
 (define_mode_iterator V_INT_noQI
 		      [V64HI V64SI V64DI])
+(define_mode_iterator V_INT_noHI
+		      [V64SI V64DI])
 
 ; All of above
 (define_mode_iterator V_ALL
@@ -2089,10 +2091,10 @@
   })
 
 (define_insn "<expander><mode>3<exec>"
-  [(set (match_operand:V_SI 0 "register_operand"  "= v")
-	(shiftop:V_SI
-	  (match_operand:V_SI 1 "gcn_alu_operand" "  v")
-	  (vec_duplicate:V_SI
+  [(set (match_operand:V_INT_noHI 0 "register_operand"  "= v")
+	(shiftop:V_INT_noHI
+	  (match_operand:V_INT_noHI 1 "gcn_alu_operand" "  v")
+	  (vec_duplicate:<VnSI>
 	    (match_operand:SI 2 "gcn_alu_operand"  "SvB"))))]
   ""
   "v_<revmnemonic>0\t%0, %2, %1"
@@ -2120,10 +2122,10 @@
   })
 
 (define_insn "v<expander><mode>3<exec>"
-  [(set (match_operand:V_SI 0 "register_operand"  "=v")
-	(shiftop:V_SI
-	  (match_operand:V_SI 1 "gcn_alu_operand" " v")
-	  (match_operand:V_SI 2 "gcn_alu_operand" "vB")))]
+  [(set (match_operand:V_INT_noHI 0 "register_operand"  "=v")
+	(shiftop:V_INT_noHI
+	  (match_operand:V_INT_noHI 1 "gcn_alu_operand" " v")
+	  (match_operand:<VnSI> 2 "gcn_alu_operand"	"vB")))]
   ""
   "v_<revmnemonic>0\t%0, %2, %1"
   [(set_attr "type" "vop2")