From: Richard Henderson Date: Fri, 24 Oct 2025 08:53:02 +0000 (+0200) Subject: Merge tag 'pull-riscv-to-apply-20251024' of https://github.com/alistair23/qemu into... X-Git-Tag: v10.2.0-rc1~45 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e8779f3d1509cd07620c6166a9a280376e01ff2f;p=thirdparty%2Fqemu.git Merge tag 'pull-riscv-to-apply-20251024' of https://github.com/alistair23/qemu into staging Second RISC-V PR for 10.2 * Correct mmu-type property of sifive_u harts in device tree * Centralize MO_TE uses in a pair of helpers * Fix Ethernet interface support for microchip-icicle-kit * Fix mask for smsiaddrcfgh * Fix env->priv setting in reset_regs_csr() * Coverity-related fixes * Fix riscv_cpu_sirq_pending() mask * Fix a uninitialized variable warning * Make PMP granularity configurable # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmj6vn4ACgkQr3yVEwxT # gBORBg/9HMcPIWY4TweyZXcVkcB/4LY3XboBCcumTUO3dEkiVMYc5TDauO++YiyJ # YPRzFSAgwNxoF2ndtNLSc6OCu6LPRzWpt9a/MavTzfNLOQZ5vUbYCd3g24uR4Plz # AOt7Jn9l8+95MxGeTq5NfDdOnyC+mF4EiIjhplbZz7UcMpouKRysAibSjuyXlYGD # DutmQ/bctyDsASNFIl3xwT4po1M4EgMX4nL01ZbfYw2sTjPH2Vj53E0eQ9iZCsP6 # l8L8PEz4Jiad2rapJdm2OS6mirMd3PZbYWqvRga/NQiTs4jGYSxiIhlpqR3Ez2id # UBGjLKcbsgvyaX1ILq3n6nfftjrXpSEnCMh86/H3xZ8dhA8eBMrGTJvYXAX33ao5 # d3ClcT+E7FTduc+hWl/B/l3eb6fOcEIQ172slBiPEfJJqwJgkXgOfftlxRJQ3iGs # FbpCL0zEeB1/0SUvgI8Wv5652GiaAljWhhIM7FhWpohc2DxV2iUXuxhhXgHkztwL # EIddIo9FLQqY7wxlQhvQKRT0hCm/9mtokq6jiQUTuVMn7gf4fWdvDSozRvX1b0DB # CiJcPnKgM/M4UQHci8rboADWPSJ8oOSdz5dheQfXVNJczFnDqzMMVFbkFicXidJU # aT+1sPuuSYE6hquR1p4yvxeyyfIQCdffzRBr3WZ2iq7GQ+I4/64= # =P0/u # -----END PGP SIGNATURE----- # gpg: Signature made Fri 24 Oct 2025 01:47:10 AM CEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis " [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20251024' of https://github.com/alistair23/qemu: (25 commits) target/riscv: Make PMP CSRs conform to WARL constraints target/riscv: Make PMP granularity configurable target/riscv: Fix a uninitialized variable warning target/riscv: fix riscv_cpu_sirq_pending() mask target/riscv/riscv-qmp-cmds.c: coverity-related fixes target/riscv/kvm: fix env->priv setting in reset_regs_csr() hw/intc: Allow gaps in hartids for aclint and aplic aplic: fix mask for smsiaddrcfgh microchip icicle: Enable PCS on Cadence Ethernet hw/net/cadence_gem: Add pcs-enabled property hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus target/riscv: Introduce mo_endian_env() helper target/riscv: Introduce mo_endian() helper target/riscv: Factor MemOp variable out when MO_TE is set target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc() target/riscv: Conceal MO_TE within gen_cmpxchg*() target/riscv: Conceal MO_TE within gen_storepair_tl() target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx() target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx() ... Signed-off-by: Richard Henderson --- e8779f3d1509cd07620c6166a9a280376e01ff2f