From: H.J. Lu <hjl.tools@gmail.com>
Date: Mon, 21 Mar 2022 18:45:59 +0000 (-0700)
Subject: x86: Disable SSE in ISA2 for -mgeneral-regs-only
X-Git-Tag: basepoints/gcc-13~568
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e8b6afa98f0a390c955a089a3d61fdd24f4e1d3a;p=thirdparty%2Fgcc.git

x86: Disable SSE in ISA2 for -mgeneral-regs-only

Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET
in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and
AVX512 ISAs.

gcc/

	PR target/105000
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace
	OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET.

gcc/testsuite/

	PR target/105000
	* gcc.target/i386/pr105000-1.c: New test.
	* gcc.target/i386/pr105000-2.c: Likewise.
	* gcc.target/i386/pr105000-3.c: Likewise.
	* gcc.target/i386/pr105000-4.c: Likewise.
---

diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 449df6351c96..07fdd045f303 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -321,7 +321,7 @@ along with GCC; see the file COPYING3.  If not see
    | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
    | OPTION_MASK_ISA2_AVX512FP16_UNSET)
 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
-  (OPTION_MASK_ISA2_AVX512F_UNSET)
+  OPTION_MASK_ISA2_SSE_UNSET
 #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
diff --git a/gcc/testsuite/gcc.target/i386/pr105000-1.c b/gcc/testsuite/gcc.target/i386/pr105000-1.c
new file mode 100644
index 000000000000..020e2adca83b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105000-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mshstk -mavxvnni" } */
+
+#include <x86gprintrin.h>
+
+__attribute__((target("no-mmx,no-sse")))
+int
+foo ()
+{
+  return _get_ssp ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr105000-2.c b/gcc/testsuite/gcc.target/i386/pr105000-2.c
new file mode 100644
index 000000000000..a113fd1dfa22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105000-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mshstk -mkl" } */
+
+#include <x86gprintrin.h>
+
+__attribute__((target("no-mmx,no-sse")))
+int
+foo ()
+{
+  return _get_ssp ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr105000-3.c b/gcc/testsuite/gcc.target/i386/pr105000-3.c
new file mode 100644
index 000000000000..7e82925270cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105000-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mshstk -mwidekl" } */
+
+#include <x86gprintrin.h>
+
+__attribute__((target("no-mmx,no-sse")))
+int
+foo ()
+{
+  return _get_ssp ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr105000-4.c b/gcc/testsuite/gcc.target/i386/pr105000-4.c
new file mode 100644
index 000000000000..195eabe85a23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105000-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mshstk -mavx512fp16" } */
+
+#include <x86gprintrin.h>
+
+__attribute__((target("no-mmx,no-sse")))
+int
+foo ()
+{
+  return _get_ssp ();
+}