From: Paul Kocialkowski Date: Fri, 4 Jul 2025 15:40:08 +0000 (+0200) Subject: clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ea879ce83d360aa13acd54cf6af913885b69ed44;p=thirdparty%2Flinux.git clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll It appears (based on experimentation) that both the de and tcon clocks need to have the same parent for the two units to work together. Assign them both to the video pll by manually clearing the parent selection bits (effectively setting index 0) and marking the clocks with the CLK_SET_RATE_NO_REPARENT flag, which ensures that they will never use a different parent. The video pll is also a possible parent for the camera subsystem, but it can use the dedicated isp pll if needed so there should be no negative side-effect due to this change. Note that ccu_mux_helper_set_parent cannot be used at this stage as it requires the clock driver to be initialized and this configuration is best done before the clock driver is available to consumers. Signed-off-by: Paul Kocialkowski Link: https://patch.msgid.link/20250704154008.3463257-2-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai --- diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 7744fc632ea6d..0c01aca4e19bf 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -347,11 +347,13 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", static const char * const de_parents[] = { "pll-video", "pll-periph0" }; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, - 0x104, 0, 4, 24, 3, BIT(31), 0); + 0x104, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_NO_REPARENT); static const char * const tcon_parents[] = { "pll-video" }; static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, - 0x118, 0, 4, 24, 3, BIT(31), 0); + 0x118, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_NO_REPARENT); static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(31), 0); @@ -753,6 +755,21 @@ static int sun8i_v3s_ccu_probe(struct platform_device *pdev) val &= ~GENMASK(19, 16); writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG); + /* + * Assign the DE and TCON clock to the video PLL. Both clocks need to + * have the same parent for the units to work together. + */ + + val = readl(reg + de_clk.common.reg); + val &= ~GENMASK(de_clk.mux.shift + de_clk.mux.width - 1, + de_clk.mux.shift); + writel(val, reg + de_clk.common.reg); + + val = readl(reg + tcon_clk.common.reg); + val &= ~GENMASK(tcon_clk.mux.shift + tcon_clk.mux.width - 1, + tcon_clk.mux.shift); + writel(val, reg + tcon_clk.common.reg); + return devm_sunxi_ccu_probe(&pdev->dev, reg, desc); }