From: Mark Wielaard <mark@klomp.org>
Date: Tue, 23 Feb 2021 15:19:26 +0000 (+0100)
Subject: Filter out unsupported instructions from HWCAP2 on powerpc.
X-Git-Tag: VALGRIND_3_17_0~45
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ea98cccb4d50a8740708507c4c72cfb1e6c88e38;p=thirdparty%2Fvalgrind.git

Filter out unsupported instructions from HWCAP2 on powerpc.

Valgrind currently doesn't support the DARN random number instruction
and the SCV syscall instruction. Filter them out of HWCAP2 so glibc
and applications don't try to use them when running under valgrind.

Also suppress printing a log message for scv instructions in the
instruction stream.

Reported by: Florian Weimer <fweimer@redhat.com>

DARN bug: https://bugs.kde.org/show_bug.cgi?id=411189
SCV bug: https://bugs.kde.org/show_bug.cgi?id=431157
---

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 880a47ebb2..308c2fe762 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -10878,8 +10878,9 @@ static Bool dis_syslink ( UInt prefix, UInt theInstr,
    /* There is no prefixed version of these instructions.  */
    PREFIX_CHECK
 
-   if (theInstr != 0x44000002) {
-      vex_printf("dis_syslink(ppc)(theInstr)\n");
+   if (theInstr != 0x44000002) { // sc
+      if (theInstr != 0x44000001) // scv
+         vex_printf("dis_syslink(ppc)(theInstr)\n");
       return False;
    }
 
diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index ba84fa6e9d..cb7902446a 100644
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -750,6 +750,14 @@ Addr setup_client_stack( void*  init_sp,
                 PPC_FEATURE2_HAS_ISEL         0x08000000
                 PPC_FEATURE2_HAS_TAR          0x04000000
                 PPC_FEATURE2_HAS_VCRYPTO      0x02000000
+                PPC_FEATURE2_HTM_NOSC         0x01000000
+                PPC_FEATURE2_ARCH_3_00        0x00800000
+                PPC_FEATURE2_HAS_IEEE128      0x00400000
+                PPC_FEATURE2_DARN             0x00200000
+                PPC_FEATURE2_SCV              0x00100000
+                PPC_FEATURE2_HTM_NO_SUSPEND   0x00080000
+                PPC_FEATURE2_ARCH_3_1         0x00040000
+                PPC_FEATURE2_MMA              0x00020000
             */
             auxv_2_07 = (auxv->u.a_val & 0x80000000ULL) == 0x80000000ULL;
             hw_caps_2_07 = (vex_archinfo->hwcaps & VEX_HWCAPS_PPC64_ISA2_07)
@@ -797,6 +805,23 @@ Addr setup_client_stack( void*  init_sp,
              * matches the setting in VEX HWCAPS.
              */
             vg_assert(auxv_3_1 == hw_caps_3_1);
+
+            /* Mask unrecognized HWCAP bits.  Only keep the bits that have
+             * explicit support in VEX. Filter out HTM bits since the
+             * transaction begin instruction (tbegin) is always failed in
+             * Valgrind causing the code to execute the failure path.
+             * Also filter out the DARN random number (bug #411189).
+             * And the SCV syscall (bug #431157).
+             */
+            auxv->u.a_val &= (0x80000000ULL     /* ARCH_2_07 */
+                              | 0x20000000ULL   /* DSCR */
+                              | 0x10000000ULL   /* EBB */
+                              | 0x08000000ULL   /* ISEL */
+                              | 0x04000000ULL   /* TAR */
+                              | 0x04000000ULL   /* VEC_CRYPTO */
+                              | 0x00800000ULL   /* ARCH_3_00 */
+                              | 0x00400000ULL   /* HAS_IEEE128 */
+                              | 0x00040000ULL); /* ARCH_3_1 */
          }
 
             break;