From: Sandra Loosemore <sloosemore@baylibre.com>
Date: Thu, 6 Nov 2025 00:26:04 +0000 (+0000)
Subject: arc: Fix positive form of -mno-brcc and -mno-dpfp-lrsr options [PR122243]
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=eb03ea05f3445736ccf69e0fe42c54a72fb1a576;p=thirdparty%2Fgcc.git

arc: Fix positive form of -mno-brcc and -mno-dpfp-lrsr options [PR122243]

These two options are defined in the negative form and don't have the
RejectNegative property so they end up having positive forms beginning
with "-mno-no-", which is confusing.  I've inverted the sense of the
option instead (so that the positive forms are -mbrcc and
-mdpfp-lrsr).

I'm not set up to build or test gcc for ARC but this is a straightforward
change similar to fixes I've made for other target-inspecific options.
Either this fix or adding RejectNegative would break any makefiles
that use the (undocumented) -mno-no forms, though.

gcc/ChangeLog
	PR other/122243
	* config/arc/arc.opt (-mno-brcc, -mno-dpfp-lrsr): Redefine in
	the positive sense.
---

diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 9bd04f15737..6da08383b76 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -181,9 +181,9 @@ mlong-calls
 Target Mask(LONG_CALLS_SET)
 Generate call insns as register indirect calls.
 
-mno-brcc
-Target Mask(NO_BRCC_SET)
-Do no generate BRcc instructions in arc_reorg.
+mbrcc
+Target InverseMask(NO_BRCC_SET)
+Generate BRcc instructions in arc_reorg.
 
 msdata
 Target InverseMask(NO_SDATA_SET)
@@ -221,9 +221,9 @@ mdpfp-fast
 Target Mask(DPFP_FAST_SET)
 FPX: Generate Double Precision FPX (fast) instructions.
 
-mno-dpfp-lrsr
-Target Mask(DPFP_DISABLE_LRSR)
-Disable LR and SR instructions from using FPX extension aux registers.
+mdpfp-lrsr
+Target InverseMask(DPFP_DISABLE_LRSR)
+Enable LR and SR instructions to use FPX extension aux registers.
 
 msimd
 Target Mask(SIMD_SET)