From: Ivo Raisr Date: Mon, 8 May 2017 17:21:36 +0000 (+0000) Subject: Remove TileGX/Linux port. X-Git-Tag: svn/VALGRIND_3_13_0^2~22 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=eb8f51783b243b79dd5346fc540784383c258cd2;p=thirdparty%2Fvalgrind.git Remove TileGX/Linux port. Fixes BZ#379504. git-svn-id: svn://svn.valgrind.org/vex/trunk@3363 --- diff --git a/VEX/auxprogs/genoffsets.c b/VEX/auxprogs/genoffsets.c index 71dc4a24ac..1f680e4f6c 100644 --- a/VEX/auxprogs/genoffsets.c +++ b/VEX/auxprogs/genoffsets.c @@ -55,7 +55,6 @@ #include "../pub/libvex_guest_s390x.h" #include "../pub/libvex_guest_mips32.h" #include "../pub/libvex_guest_mips64.h" -#include "../pub/libvex_guest_tilegx.h" #define VG_STRINGIFZ(__str) #__str #define VG_STRINGIFY(__str) VG_STRINGIFZ(__str) @@ -264,68 +263,6 @@ void foo ( void ) GENOFFSET(MIPS64,mips64,PC); GENOFFSET(MIPS64,mips64,HI); GENOFFSET(MIPS64,mips64,LO); - - // Tilegx - GENOFFSET(TILEGX,tilegx,r0); - GENOFFSET(TILEGX,tilegx,r1); - GENOFFSET(TILEGX,tilegx,r2); - GENOFFSET(TILEGX,tilegx,r3); - GENOFFSET(TILEGX,tilegx,r4); - GENOFFSET(TILEGX,tilegx,r5); - GENOFFSET(TILEGX,tilegx,r6); - GENOFFSET(TILEGX,tilegx,r7); - GENOFFSET(TILEGX,tilegx,r8); - GENOFFSET(TILEGX,tilegx,r9); - GENOFFSET(TILEGX,tilegx,r10); - GENOFFSET(TILEGX,tilegx,r11); - GENOFFSET(TILEGX,tilegx,r12); - GENOFFSET(TILEGX,tilegx,r13); - GENOFFSET(TILEGX,tilegx,r14); - GENOFFSET(TILEGX,tilegx,r15); - GENOFFSET(TILEGX,tilegx,r16); - GENOFFSET(TILEGX,tilegx,r17); - GENOFFSET(TILEGX,tilegx,r18); - GENOFFSET(TILEGX,tilegx,r19); - GENOFFSET(TILEGX,tilegx,r20); - GENOFFSET(TILEGX,tilegx,r21); - GENOFFSET(TILEGX,tilegx,r22); - GENOFFSET(TILEGX,tilegx,r23); - GENOFFSET(TILEGX,tilegx,r24); - GENOFFSET(TILEGX,tilegx,r25); - GENOFFSET(TILEGX,tilegx,r26); - GENOFFSET(TILEGX,tilegx,r27); - GENOFFSET(TILEGX,tilegx,r28); - GENOFFSET(TILEGX,tilegx,r29); - GENOFFSET(TILEGX,tilegx,r30); - GENOFFSET(TILEGX,tilegx,r31); - GENOFFSET(TILEGX,tilegx,r32); - GENOFFSET(TILEGX,tilegx,r33); - GENOFFSET(TILEGX,tilegx,r34); - GENOFFSET(TILEGX,tilegx,r35); - GENOFFSET(TILEGX,tilegx,r36); - GENOFFSET(TILEGX,tilegx,r37); - GENOFFSET(TILEGX,tilegx,r38); - GENOFFSET(TILEGX,tilegx,r39); - GENOFFSET(TILEGX,tilegx,r40); - GENOFFSET(TILEGX,tilegx,r41); - GENOFFSET(TILEGX,tilegx,r42); - GENOFFSET(TILEGX,tilegx,r43); - GENOFFSET(TILEGX,tilegx,r44); - GENOFFSET(TILEGX,tilegx,r45); - GENOFFSET(TILEGX,tilegx,r46); - GENOFFSET(TILEGX,tilegx,r47); - GENOFFSET(TILEGX,tilegx,r48); - GENOFFSET(TILEGX,tilegx,r49); - GENOFFSET(TILEGX,tilegx,r50); - GENOFFSET(TILEGX,tilegx,r51); - GENOFFSET(TILEGX,tilegx,r52); - GENOFFSET(TILEGX,tilegx,r53); - GENOFFSET(TILEGX,tilegx,r54); - GENOFFSET(TILEGX,tilegx,r55); - GENOFFSET(TILEGX,tilegx,pc); - GENOFFSET(TILEGX,tilegx,EMNOTE); - GENOFFSET(TILEGX,tilegx,CMSTART); - GENOFFSET(TILEGX,tilegx,NRADDR); } /*--------------------------------------------------------------------*/ diff --git a/VEX/priv/guest_tilegx_defs.h b/VEX/priv/guest_tilegx_defs.h deleted file mode 100644 index 5cdb621d3c..0000000000 --- a/VEX/priv/guest_tilegx_defs.h +++ /dev/null @@ -1,110 +0,0 @@ -/*---------------------------------------------------------------*/ -/*--- begin guest_tilegx_defs.h ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2010-2017 Tilera Corp. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - - /* Contributed by Zhi-Gang Liu */ - -#ifndef __VEX_GUEST_TILEGX_DEFS_H -#define __VEX_GUEST_TILEGX_DEFS_H - -#ifdef __tilegx__ -#include "tilegx_disasm.h" -#endif - -/*---------------------------------------------------------*/ -/*--- tilegx to IR conversion ---*/ -/*---------------------------------------------------------*/ - -/* Convert one TILEGX insn to IR. See the type DisOneInstrFn in - guest_generic_bb_to_IR.h. */ -extern DisResult disInstr_TILEGX ( IRSB* irbb, - Bool (*resteerOkFn) ( void *, Addr ), - Bool resteerCisOk, - void* callback_opaque, - const UChar* guest_code, - Long delta, - Addr guest_IP, - VexArch guest_arch, - const VexArchInfo* archinfo, - const VexAbiInfo* abiinfo, - VexEndness host_endness_IN, - Bool sigill_diag_IN ); - -/* Used by the optimiser to specialise calls to helpers. */ -extern IRExpr *guest_tilegx_spechelper ( const HChar * function_name, - IRExpr ** args, - IRStmt ** precedingStmts, - Int n_precedingStmts ); - -/* Describes to the optimser which part of the guest state require - precise memory exceptions. This is logically part of the guest - state description. */ -extern Bool guest_tilegx_state_requires_precise_mem_exns ( - Int, Int, VexRegisterUpdates ); - -extern VexGuestLayout tilegxGuest_layout; - -/*---------------------------------------------------------*/ -/*--- tilegx guest helpers ---*/ -/*---------------------------------------------------------*/ - -extern ULong tilegx_dirtyhelper_gen ( ULong opc, - ULong rd0, - ULong rd1, - ULong rd2, - ULong rd3 ); - -/*---------------------------------------------------------*/ -/*--- Condition code stuff ---*/ -/*---------------------------------------------------------*/ - -/* Defines conditions which we can ask for TILEGX */ - -typedef enum { - TILEGXCondEQ = 0, /* equal : Z=1 */ - TILEGXCondNE = 1, /* not equal : Z=0 */ - TILEGXCondHS = 2, /* >=u (higher or same) : C=1 */ - TILEGXCondLO = 3, /* u (higher) : C=1 && Z=0 */ - TILEGXCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ - TILEGXCondGE = 10, /* >=s (signed greater or equal) : N=V */ - TILEGXCondLT = 11, /* s (signed greater) : Z=0 && N=V */ - TILEGXCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ - TILEGXCondAL = 14, /* always (unconditional) : 1 */ - TILEGXCondNV = 15 /* never (unconditional): : 0 */ -} TILEGXCondcode; - -#endif /* __VEX_GUEST_TILEGX_DEFS_H */ - -/*---------------------------------------------------------------*/ -/*--- end guest_tilegx_defs.h ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/priv/guest_tilegx_helpers.c b/VEX/priv/guest_tilegx_helpers.c deleted file mode 100644 index c774be2121..0000000000 --- a/VEX/priv/guest_tilegx_helpers.c +++ /dev/null @@ -1,1103 +0,0 @@ -/*---------------------------------------------------------------*/ -/*--- begin guest_tilegx_helpers.c ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2010-2017 Tilera Corp. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - -/* Contributed by Zhi-Gang Liu */ - -#include "libvex_basictypes.h" -#include "libvex_emnote.h" -#include "libvex_guest_tilegx.h" -#include "libvex_ir.h" -#include "libvex.h" - -#include "main_util.h" -#include "guest_generic_bb_to_IR.h" -#include "guest_tilegx_defs.h" - -/* This file contains helper functions for tilegx guest code. Calls to - these functions are generated by the back end. -*/ - -#define ALWAYSDEFD(field) \ - { offsetof(VexGuestTILEGXState, field), \ - (sizeof ((VexGuestTILEGXState*)0)->field) } - -IRExpr *guest_tilegx_spechelper ( const HChar * function_name, IRExpr ** args, - IRStmt ** precedingStmts, Int n_precedingStmts) -{ - return NULL; -} - -/* VISIBLE TO LIBVEX CLIENT */ -void LibVEX_GuestTILEGX_initialise ( VexGuestTILEGXState * vex_state ) -{ - vex_state->guest_r0 = 0; - vex_state->guest_r1 = 0; - vex_state->guest_r2 = 0; - vex_state->guest_r3 = 0; - vex_state->guest_r4 = 0; - vex_state->guest_r5 = 0; - vex_state->guest_r6 = 0; - vex_state->guest_r7 = 0; - vex_state->guest_r8 = 0; - vex_state->guest_r9 = 0; - vex_state->guest_r10 = 0; - vex_state->guest_r11 = 0; - vex_state->guest_r12 = 0; - vex_state->guest_r13 = 0; - vex_state->guest_r14 = 0; - vex_state->guest_r15 = 0; - vex_state->guest_r16 = 0; - vex_state->guest_r17 = 0; - vex_state->guest_r18 = 0; - vex_state->guest_r19 = 0; - vex_state->guest_r20 = 0; - vex_state->guest_r21 = 0; - vex_state->guest_r22 = 0; - vex_state->guest_r23 = 0; - vex_state->guest_r24 = 0; - vex_state->guest_r25 = 0; - vex_state->guest_r26 = 0; - vex_state->guest_r27 = 0; - vex_state->guest_r28 = 0; - vex_state->guest_r29 = 0; - vex_state->guest_r30 = 0; - vex_state->guest_r31 = 0; - vex_state->guest_r32 = 0; - vex_state->guest_r33 = 0; - vex_state->guest_r34 = 0; - vex_state->guest_r35 = 0; - vex_state->guest_r36 = 0; - vex_state->guest_r37 = 0; - vex_state->guest_r38 = 0; - vex_state->guest_r39 = 0; - vex_state->guest_r40 = 0; - vex_state->guest_r41 = 0; - vex_state->guest_r42 = 0; - vex_state->guest_r43 = 0; - vex_state->guest_r44 = 0; - vex_state->guest_r45 = 0; - vex_state->guest_r46 = 0; - vex_state->guest_r47 = 0; - vex_state->guest_r48 = 0; - vex_state->guest_r49 = 0; - vex_state->guest_r50 = 0; - vex_state->guest_r51 = 0; - vex_state->guest_r52 = 0; - vex_state->guest_r53 = 0; - vex_state->guest_r54 = 0; - vex_state->guest_r55 = 0; - - vex_state->guest_pc = 0; /* Program counter */ - - vex_state->guest_EMNOTE = 0; - vex_state->guest_CMSTART = 0; - - /* For clflush: record start and length of area to invalidate */ - vex_state->guest_CMSTART = 0; - vex_state->guest_CMLEN = 0; - - /* Used to record the unredirected guest address at the start of - a translation whose start has been redirected. By reading - this pseudo-register shortly afterwards, the translation can - find out what the corresponding no-redirection address was. - Note, this is only set for wrap-style redirects, not for - replace-style ones. */ - vex_state->guest_NRADDR = 0; -} - -/*-----------------------------------------------------------*/ -/*--- Describing the tilegx guest state, for the benefit ---*/ -/*--- of iropt and instrumenters. ---*/ -/*-----------------------------------------------------------*/ - -/* Figure out if any part of the guest state contained in minoff - .. maxoff requires precise memory exceptions. If in doubt return - True (but this is generates significantly slower code). - - We enforce precise exns for guest SP, PC. -*/ -Bool guest_tilegx_state_requires_precise_mem_exns ( - Int minoff, Int maxoff, - VexRegisterUpdates pxControl) -{ - Int sp_min = offsetof(VexGuestTILEGXState, guest_r54); - Int sp_max = sp_min + 8 - 1; - Int pc_min = offsetof(VexGuestTILEGXState, guest_pc); - Int pc_max = pc_min + 8 - 1; - - if (maxoff < sp_min || minoff > sp_max) { - /* no overlap with sp */ - if (pxControl == VexRegUpdSpAtMemAccess) - return False; /* We only need to check stack pointer. */ - } else { - return True; - } - - if (maxoff < pc_min || minoff > pc_max) { - /* no overlap with pc */ - } else { - return True; - } - - /* We appear to need precise updates of R52 in order to get proper - stacktraces from non-optimised code. */ - Int fp_min = offsetof(VexGuestTILEGXState, guest_r52); - Int fp_max = fp_min + 8 - 1; - - if (maxoff < fp_min || minoff > fp_max) { - /* no overlap with fp */ - } else { - return True; - } - - return False; -} - -VexGuestLayout tilegxGuest_layout = { - /* Total size of the guest state, in bytes. */ - .total_sizeB = sizeof(VexGuestTILEGXState), - /* Describe the stack pointer. */ - .offset_SP = offsetof(VexGuestTILEGXState, guest_r54), - .sizeof_SP = 8, - /* Describe the frame pointer. */ - .offset_FP = offsetof(VexGuestTILEGXState, guest_r52), - .sizeof_FP = 8, - /* Describe the instruction pointer. */ - .offset_IP = offsetof(VexGuestTILEGXState, guest_pc), - .sizeof_IP = 8, - /* Describe any sections to be regarded by Memcheck as - 'always-defined'. */ - .n_alwaysDefd = 8, - /* ? :( */ - .alwaysDefd = { - /* 0 */ ALWAYSDEFD(guest_r0), - /* 1 */ ALWAYSDEFD(guest_r1), - /* 2 */ ALWAYSDEFD(guest_EMNOTE), - /* 3 */ ALWAYSDEFD(guest_CMSTART), - /* 4 */ ALWAYSDEFD(guest_CMLEN), - /* 5 */ ALWAYSDEFD(guest_r52), - /* 6 */ ALWAYSDEFD(guest_r55), - /* 7 */ ALWAYSDEFD(guest_pc), - } -}; - -#ifdef __tilegx__ -ULong tilegx_dirtyhelper_gen ( ULong opc, - ULong rd0, ULong rd1, - ULong rd2, ULong rd3) -{ - switch (opc) - { - case 0: - { - /* break point */ - switch (rd0) { - case 0x286a44ae90048fffULL: - asm (" bpt "); - break; - default: - vex_printf("unhandled \"bpt\": cins=%016llx\n", rd0); - - vassert(0); - return 0; - } - } - break; - case 28: - { - return __insn_addxsc(rd1, rd2); - } - break; - - case 150: - { - __insn_mf(); - return 0; - } - break; - - case 152: /* mm rd, ra, imm0, imm1 */ - { - ULong mask; - - if( rd2 <= rd3) - mask = (-1ULL << rd2) ^ ((-1ULL << rd3) << 1); - else - mask = (-1ULL << rd2) | (-1ULL >> (63 - rd3)); - - return (rd0 & mask) | (rd1 & (-1ULL ^ mask)); - } - break; - case 154: /* mtspr imm, ra */ - { - switch(rd0) - { - case 0x2785: - __insn_mtspr(0x2785, rd1); - break; - case 0x2780: - __insn_mtspr(0x2780, rd1); - break; - case 0x2708: - __insn_mtspr(0x2708, rd1); - break; - case 0x2580: - __insn_mtspr(0x2580, rd1); - break; - case 0x2581: - __insn_mtspr(0x2581, rd1); - break; - case 0x2709: // PASS - __insn_mtspr(0x2709, rd1); - break; - case 0x2707: // FAIL - __insn_mtspr(0x2707, rd1); - break; - case 0x2705: // DONE - __insn_mtspr(0x2705, rd1); - break; - - case 0x2870: // - - default: - vex_printf("opc=%d rd0=%llx rd1=%llx\n", - (int)opc, rd0, rd1); - vassert(0); - } - } - break; - - case 151: /* mfspr rd, imm */ - { - switch(rd1) - { - case 0x2785: // SIM_CTRL - return __insn_mfspr(0x2785); - break; - - case 0x2708: // ICS - return __insn_mfspr(0x2708); - break; - - case 0x2780: // CMPEXCH_VALUE - return __insn_mfspr(0x2780); - break; - - case 0x2781: // CYCLE - return __insn_mfspr(0x2781); - break; - - case 0x2709: // PASS - return __insn_mfspr(0x2709); - break; - - case 0x2707: // FAIL - return __insn_mfspr(0x2707); - break; - - case 0x2705: // DONE - return __insn_mfspr(0x2705); - break; - - case 0x2580: // EX_CONTEXT_0 - return __insn_mfspr(0x2580); - break; - - case 0x2581: // EX_CONTEXT_1 - return __insn_mfspr(0x2581); - break; - - default: - vex_printf("opc=%d rd0=%llx rd1=%llx\n", - (int)opc, rd0, rd1); - vassert(0); - } - } - break; - case 183: - { - return __insn_pcnt(rd1); - } - break; - case 184: - { - return __insn_revbits(rd1); - } - break; - case 185: /* revbytes rd, ra */ - { - return __insn_revbytes(rd1); - } - break; - - case 102: - return __insn_fsingle_add1(rd1, rd2); - break; - - case 103: - return __insn_fsingle_addsub2(rd0, rd1, rd2); - break; - - case 104: - return __insn_fsingle_mul1(rd1, rd2); - break; - - case 105: - return __insn_fsingle_mul2(rd1, rd2); - break; - - case 106: - return __insn_fsingle_pack1(rd1); - break; - - case 107: - return __insn_fsingle_pack2(rd1, rd2); - break; - - case 108: - return __insn_fsingle_sub1(rd1, rd2); - break; - - case 21: - switch (rd0) { - case 0x286a44ae90048fffULL: - asm ("{ moveli zero, 72 ; raise }"); - break; - default: - vex_printf("unhandled \"raise\": cins=%016llx\n", rd0); - __insn_ill(); - return 0; - } - break; - - case 64: - { - return __insn_cmul(rd1, rd2); - } - break; - case 65: - { - return __insn_cmula(rd0, rd1, rd2); - } - break; - case 66: - { - return __insn_cmulaf(rd0, rd1, rd2); - } - break; - case 67: - { - return __insn_cmulf(rd1, rd2); - } - break; - case 68: - { - return __insn_cmulfr(rd1, rd2); - } - break; - case 69: - { - return __insn_cmulh(rd1, rd2); - } - break; - case 70: - { - return __insn_cmulhr(rd1, rd2); - } - break; - case 71: - { - return __insn_crc32_32(rd1, rd2); - } - break; - case 72: - { - return __insn_crc32_8(rd1, rd2); - } - break; - case 75: - { - return __insn_dblalign2(rd1, rd2); - } - break; - case 76: - { - return __insn_dblalign4(rd1, rd2); - } - break; - case 77: - { - return __insn_dblalign6(rd1, rd2); - } - break; - case 78: - { - __insn_drain(); - return 0; - } - break; - case 79: - { - __insn_dtlbpr(rd0); - return 0; - } - break; - case 82: - { - return __insn_fdouble_add_flags(rd1, rd2); - } - break; - case 83: - { - return __insn_fdouble_addsub(rd0, rd1, rd2); - } - break; - case 84: - { - return __insn_fdouble_mul_flags(rd1, rd2); - } - break; - case 85: - { - return __insn_fdouble_pack1(rd1, rd2); - } - break; - case 86: - { - return __insn_fdouble_pack2(rd0, rd1, rd2); - } - break; - case 87: - { - return __insn_fdouble_sub_flags(rd1, rd2); - } - break; - case 88: - { - return __insn_fdouble_unpack_max(rd1, rd2); - } - break; - case 89: - { - return __insn_fdouble_unpack_min(rd1, rd2); - } - break; - - case 98: - { - __insn_finv(rd0); - return 0; - } - break; - case 99: - { - __insn_flush(rd0); - return 0; - } - break; - case 100: - { - __insn_flushwb(); - return 0; - } - break; - - case 109: - { - __insn_icoh((ULong *)rd0); - return 0; - } - break; - case 110: - { - __insn_ill(); - } - break; - case 111: - { - __insn_inv((ULong *)rd0); - return 0; - } - break; - - case 169: - { - return __insn_mula_hu_hu(rd0, rd1, rd2); - } - break; - case 170: - { - return __insn_mula_hu_ls(rd0, rd1, rd2); - } - break; - case 205: - { - return __insn_shufflebytes(rd0, rd1, rd2); - } - break; - case 224: - { - return __insn_subxsc(rd1, rd2); - } - break; - case 229: - { - return __insn_tblidxb0(rd0, rd1); - } - break; - case 230: - { - return __insn_tblidxb1(rd0, rd1); - } - break; - case 231: - { - return __insn_tblidxb2(rd0, rd1); - } - break; - case 232: - { - return __insn_tblidxb3(rd0, rd1); - } - break; - case 233: - { - return __insn_v1add(rd1, rd2); - } - break; - case 234: - { - return __insn_v1add(rd1, rd2); - } - break; - case 235: - { - return __insn_v1adduc(rd1, rd2); - } - break; - case 236: - { - return __insn_v1adiffu(rd1, rd2); - } - break; - case 237: - { - return __insn_v1avgu(rd1, rd2); - } - break; - - case 238: - { - return __insn_v1cmpeq(rd1, rd2); - } - break; - case 239: - { - return __insn_v1cmpeq(rd1, rd2); - } - break; - case 240: - { - return __insn_v1cmples(rd1, rd2); - } - break; - case 241: - { - return __insn_v1cmpleu(rd1, rd2); - } - break; - case 242: - { - return __insn_v1cmplts(rd1, rd2); - } - break; - case 243: - { - return __insn_v1cmplts(rd1, rd2); - } - break; - case 244: - { - return __insn_v1cmpltu(rd1, rd2); - } - break; - case 245: - { - return __insn_v1cmpltu(rd1, rd2); - } - break; - case 246: - { - return __insn_v1cmpne(rd1, rd2); - } - break; - case 247: - { - return __insn_v1ddotpu(rd1, rd2); - } - break; - case 248: - { - return __insn_v1ddotpua(rd0, rd1, rd2); - } - break; - case 249: - { - return __insn_v1ddotpus(rd1, rd2); - } - break; - case 250: - { - return __insn_v1ddotpusa(rd0, rd1, rd2); - } - break; - case 251: - { - return __insn_v1dotp(rd1, rd2); - } - break; - case 252: - { - return __insn_v1dotpa(rd0, rd1, rd2); - } - break; - case 253: - { - return __insn_v1dotpu(rd1, rd2); - } - break; - case 254: - { - return __insn_v1dotpua(rd0, rd1, rd2); - } - break; - case 255: - { - return __insn_v1dotpus(rd1, rd2); - } - break; - case 256: - { - return __insn_v1dotpusa(rd0, rd1, rd2); - } - break; - case 257: - { - return __insn_v1int_h(rd1, rd2); - } - break; - case 258: - { - return __insn_v1int_l(rd1, rd2); - } - break; - case 259: - { - return __insn_v1maxu(rd1, rd2); - } - break; - case 260: - { - return __insn_v1maxu(rd1, rd2); - } - break; - case 261: - { - return __insn_v1minu(rd1, rd2); - } - break; - case 262: - { - return __insn_v1minu(rd1, rd2); - } - break; - case 263: - { - return __insn_v1mnz(rd1, rd2); - } - break; - case 264: - { - return __insn_v1multu(rd1, rd2); - } - break; - case 265: - { - return __insn_v1mulu(rd1, rd2); - } - break; - case 266: - { - return __insn_v1mulus(rd1, rd2); - } - break; - case 267: - { - return __insn_v1mz(rd1, rd2); - } - break; - case 268: - { - return __insn_v1sadau(rd0, rd1, rd2); - } - break; - case 269: - { - return __insn_v1sadu(rd1, rd2); - } - break; - case 270: - { - return __insn_v1shl(rd1, rd2); - } - break; - case 271: - { - return __insn_v1shl(rd1, rd2); - } - break; - case 272: - { - return __insn_v1shrs(rd1, rd2); - } - break; - case 273: - { - return __insn_v1shrs(rd1, rd2); - } - break; - case 274: - { - return __insn_v1shru(rd1, rd2); - } - break; - case 275: - { - return __insn_v1shrui(rd1, rd2); - } - break; - case 276: - { - return __insn_v1sub(rd1, rd2); - } - break; - case 277: - { - return __insn_v1subuc(rd1, rd2); - } - break; - case 278: - { - return __insn_v2add(rd1, rd2); - } - break; - case 279: - { - return __insn_v2add(rd1, rd2); - } - break; - case 280: - { - return __insn_v2addsc(rd1, rd2); - } - break; - case 281: - { - return __insn_v2adiffs(rd1, rd2); - } - break; - case 282: - { - return __insn_v2avgs(rd1, rd2); - } - break; - case 283: - { - return __insn_v2cmpeq(rd1, rd2); - } - break; - case 284: - { - return __insn_v2cmpeq(rd1, rd2); - } - break; - case 285: - { - return __insn_v2cmples(rd1, rd2); - } - break; - case 286: - { - return __insn_v2cmpleu(rd1, rd2); - } - break; - case 287: - { - return __insn_v2cmplts(rd1, rd2); - } - break; - case 288: - { - return __insn_v2cmplts(rd1, rd2); - } - break; - case 289: - { - return __insn_v2cmpltu(rd1, rd2); - } - break; - case 290: - { - return __insn_v2cmpltu(rd1, rd2); - } - break; - case 291: - { - return __insn_v2cmpne(rd1, rd2); - } - break; - case 292: - { - return __insn_v2dotp(rd1, rd2); - } - break; - case 293: - { - return __insn_v2dotpa(rd0, rd1, rd2); - } - break; - case 294: - { - return __insn_v2int_h(rd1, rd2); - } - break; - case 295: - { - return __insn_v2int_l(rd1, rd2); - } - break; - case 296: - { - return __insn_v2maxs(rd1, rd2); - } - break; - case 297: - { - return __insn_v2maxs(rd1, rd2); - } - break; - case 298: - { - return __insn_v2mins(rd1, rd2); - } - break; - case 299: - { - return __insn_v2mins(rd1, rd2); - } - break; - case 300: - { - return __insn_v2mnz(rd1, rd2); - } - break; - case 301: - { - return __insn_v2mulfsc(rd1, rd2); - } - break; - case 302: - { - return __insn_v2muls(rd1, rd2); - } - break; - case 303: - { - return __insn_v2mults(rd1, rd2); - } - break; - case 304: - { - return __insn_v2mz(rd1, rd2); - } - break; - case 305: - { - return __insn_v2packh(rd1, rd2); - } - break; - case 306: - { - return __insn_v2packl(rd1, rd2); - } - break; - case 307: - { - return __insn_v2packuc(rd1, rd2); - } - break; - case 308: - { - return __insn_v2sadas(rd0, rd1, rd2); - } - break; - case 309: - { - return __insn_v2sadau(rd0, rd1, rd2); - } - break; - case 310: - { - return __insn_v2sads(rd1, rd2); - } - break; - case 311: - { - return __insn_v2sadu(rd1, rd2); - } - break; - case 312: - { - return __insn_v2shl(rd1, rd2); - } - break; - case 313: - { - return __insn_v2shl(rd1, rd2); - } - break; - case 314: - { - return __insn_v2shlsc(rd1, rd2); - } - break; - case 315: - { - return __insn_v2shrs(rd1, rd2); - } - break; - case 316: - { - return __insn_v2shrs(rd1, rd2); - } - break; - case 317: - { - return __insn_v2shru(rd1, rd2); - } - break; - case 318: - { - return __insn_v2shru(rd1, rd2); - } - break; - case 319: - { - return __insn_v2sub(rd1, rd2); - } - break; - case 320: - { - return __insn_v2subsc(rd1, rd2); - } - break; - case 321: - { - return __insn_v4add(rd1, rd2); - } - break; - case 322: - { - return __insn_v4addsc(rd1, rd2); - } - break; - case 323: - { - return __insn_v4int_h(rd1, rd2); - } - break; - case 324: - { - return __insn_v4int_l(rd1, rd2); - } - break; - case 325: - { - return __insn_v4packsc(rd1, rd2); - } - break; - case 326: - { - return __insn_v4shl(rd1, rd2); - } - break; - case 327: - { - return __insn_v4shlsc(rd1, rd2); - } - break; - case 328: - { - return __insn_v4shrs(rd1, rd2); - } - break; - case 329: - { - return __insn_v4shru(rd1, rd2); - } - break; - case 330: - { - return __insn_v4sub(rd1, rd2); - } - break; - case 331: - { - return __insn_v4subsc(rd1, rd2); - } - break; - - default: - vex_printf("opc=%d rd0=%llx rd1=%llx\n", - (int)opc, rd0, rd1); - vassert(0); - } -} -#else -ULong tilegx_dirtyhelper_gen ( ULong opc, - ULong rd0, ULong rd1, - ULong rd2, ULong rd3 ) -{ - vex_printf("NOT a TILEGX platform"); - return 0; -} -#endif /* __tilegx__ */ - -/*---------------------------------------------------------------*/ -/*--- end guest_tilegx_helpers.c ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/priv/guest_tilegx_toIR.c b/VEX/priv/guest_tilegx_toIR.c deleted file mode 100644 index 46e64442ce..0000000000 --- a/VEX/priv/guest_tilegx_toIR.c +++ /dev/null @@ -1,2578 +0,0 @@ - -/*--------------------------------------------------------------------*/ -/*--- begin guest_tilegx_toIR.c ---*/ -/*--------------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2010-2017 Tilera Corp. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - -/* Contributed by Zhi-Gang Liu */ - -/* Translates TILEGX code to IR. */ - -#include "libvex_basictypes.h" -#include "libvex_ir.h" -#include "libvex.h" -#include "libvex_guest_tilegx.h" - -#include "main_util.h" -#include "main_globals.h" -#include "guest_generic_bb_to_IR.h" -#include "guest_tilegx_defs.h" -#include "tilegx_disasm.h" - -/*------------------------------------------------------------*/ -/*--- Globals ---*/ -/*------------------------------------------------------------*/ - -/* These are set at the start of the translation of a instruction, so - that we don't have to pass them around endlessly. CONST means does - not change during translation of the instruction. -*/ - -/* CONST: is the host bigendian? This has to do with float vs double - register accesses on VFP, but it's complex and not properly thought - out. */ -static VexEndness host_endness; - -/* Pointer to the guest code area. */ -static UChar *guest_code; - -/* The guest address corresponding to guest_code[0]. */ -static Addr64 guest_PC_bbstart; - -/* CONST: The guest address for the instruction currently being - translated. */ -static Addr64 guest_PC_curr_instr; - -/* MOD: The IRSB* into which we're generating code. */ -static IRSB *irsb; - -/*------------------------------------------------------------*/ -/*--- Debugging output ---*/ -/*------------------------------------------------------------*/ - -#define DIP(format, args...) \ - if (vex_traceflags & VEX_TRACE_FE) \ - vex_printf(format, ## args) - -/*------------------------------------------------------------*/ -/*--- Helper bits and pieces for deconstructing the ---*/ -/*--- tilegx insn stream. ---*/ -/*------------------------------------------------------------*/ - -static Int integerGuestRegOffset ( UInt iregNo ) -{ - return 8 * (iregNo); -} - -/*------------------------------------------------------------*/ -/*--- Field helpers ---*/ -/*------------------------------------------------------------*/ - -/*------------------------------------------------------------*/ -/*--- Helper bits and pieces for creating IR fragments. ---*/ -/*------------------------------------------------------------*/ - -static IRExpr *mkU8 ( UInt i ) -{ - return IRExpr_Const(IRConst_U8((UChar) i)); -} - -/* Create an expression node for a 32-bit integer constant */ -static IRExpr *mkU32 ( UInt i ) -{ - return IRExpr_Const(IRConst_U32(i)); -} - -/* Create an expression node for a 64-bit integer constant */ -static IRExpr *mkU64 ( ULong i ) -{ - return IRExpr_Const(IRConst_U64(i)); -} - -static IRExpr *mkexpr ( IRTemp tmp ) -{ - return IRExpr_RdTmp(tmp); -} - -static IRExpr *unop ( IROp op, IRExpr * a ) -{ - return IRExpr_Unop(op, a); -} - -static IRExpr *binop ( IROp op, IRExpr * a1, IRExpr * a2 ) -{ - return IRExpr_Binop(op, a1, a2); -} - -static IRExpr *load ( IRType ty, IRExpr * addr ) -{ - IRExpr *load1 = NULL; - - load1 = IRExpr_Load(Iend_LE, ty, addr); - return load1; -} - -/* Add a statement to the list held by "irsb". */ -static void stmt ( IRStmt * st ) -{ - addStmtToIRSB(irsb, st); -} - -#define OFFB_PC offsetof(VexGuestTILEGXState, guest_pc) - -static void putPC ( IRExpr * e ) -{ - stmt(IRStmt_Put(OFFB_PC, e)); -} - -static void assign ( IRTemp dst, IRExpr * e ) -{ - stmt(IRStmt_WrTmp(dst, e)); -} - -static void store ( IRExpr * addr, IRExpr * data ) -{ - stmt(IRStmt_Store(Iend_LE, addr, data)); -} - -/* Generate a new temporary of the given type. */ -static IRTemp newTemp ( IRType ty ) -{ - vassert(isPlausibleIRType(ty)); - return newIRTemp(irsb->tyenv, ty); -} - -static ULong extend_s_16to64 ( UInt x ) -{ - return (ULong) ((((Long) x) << 48) >> 48); -} - -static ULong extend_s_8to64 ( UInt x ) -{ - return (ULong) ((((Long) x) << 56) >> 56); -} - -static IRExpr *getIReg ( UInt iregNo ) -{ - IRType ty = Ity_I64; - if(!(iregNo < 56 || iregNo == 63 || - (iregNo >= 70 && iregNo <= 73))) { - vex_printf("iregNo=%u\n", iregNo); - vassert(0); - } - return IRExpr_Get(integerGuestRegOffset(iregNo), ty); -} - -static void putIReg ( UInt archreg, IRExpr * e ) -{ - IRType ty = Ity_I64; - if(!(archreg < 56 || archreg == 63 || archreg == 70 || - archreg == 72 || archreg == 73)) { - vex_printf("archreg=%u\n", archreg); - vassert(0); - } - vassert(typeOfIRExpr(irsb->tyenv, e) == ty); - if (archreg != 63) - stmt(IRStmt_Put(integerGuestRegOffset(archreg), e)); -} - -/* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some - of these combinations make sense. */ -static IRExpr *narrowTo ( IRType dst_ty, IRExpr * e ) -{ - IRType src_ty = typeOfIRExpr(irsb->tyenv, e); - if (src_ty == dst_ty) - return e; - if (src_ty == Ity_I32 && dst_ty == Ity_I16) - return unop(Iop_32to16, e); - if (src_ty == Ity_I32 && dst_ty == Ity_I8) - return unop(Iop_32to8, e); - - if (src_ty == Ity_I64 && dst_ty == Ity_I8) { - return unop(Iop_64to8, e); - } - if (src_ty == Ity_I64 && dst_ty == Ity_I16) { - return unop(Iop_64to16, e); - } - if (src_ty == Ity_I64 && dst_ty == Ity_I32) { - return unop(Iop_64to32, e); - } - - if (vex_traceflags & VEX_TRACE_FE) { - vex_printf("\nsrc, dst tys are: "); - ppIRType(src_ty); - vex_printf(", "); - ppIRType(dst_ty); - vex_printf("\n"); - } - vpanic("narrowTo(tilegx)"); - return e; -} - -#define signExtend(_e, _n) \ - ((_n == 32) ? \ - unop(Iop_32Sto64, _e) : \ - ((_n == 16) ? \ - unop(Iop_16Sto64, _e) : \ - (binop(Iop_Sar64, binop(Iop_Shl64, _e, mkU8(63 - (_n))), mkU8(63 - (_n)))))) - -static IRStmt* dis_branch ( IRExpr* guard, ULong imm ) -{ - IRTemp t0; - - t0 = newTemp(Ity_I1); - assign(t0, guard); - return IRStmt_Exit(mkexpr(t0), Ijk_Boring, - IRConst_U64(imm), OFFB_PC); -} - -#define MARK_REG_WB(_rd, _td) \ - do { \ - vassert(rd_wb_index < 6); \ - rd_wb_temp[rd_wb_index] = _td; \ - rd_wb_reg[rd_wb_index] = _rd; \ - rd_wb_index++; \ - } while(0) - - -/* Expand/repeat byte _X 8 times to a 64-bit value */ -#define V1EXP(_X) \ - ({ \ - _X = ((((UChar)(_X)) << 8) | ((UChar)(_X))); \ - _X = (((_X) << 16) | (_X)); \ - (((_X) << 32) | (_X)); \ - }) - -/* Expand/repeat byte _X 4 times to a 64-bit value */ -#define V2EXP(_X) \ - ({ \ - _X = ((((UChar)(_X)) << 16) | ((UChar)(_X))); \ - (((_X) << 32) | (_X)); \ - }) - -/*------------------------------------------------------------*/ -/*--- Disassemble a single instruction ---*/ -/*------------------------------------------------------------*/ - -/* Disassemble a single instruction bundle into IR. The bundle is - located in host memory at guest_instr, and has guest IP of - guest_PC_curr_instr, which will have been set before the call - here. */ -static DisResult disInstr_TILEGX_WRK ( Bool(*resteerOkFn) (void *, Addr), - Bool resteerCisOk, - void *callback_opaque, - Long delta64, - const VexArchInfo * archinfo, - const VexAbiInfo * abiinfo, - Bool sigill_diag ) -{ - struct tilegx_decoded_instruction - decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]; - ULong cins, opcode = -1, rd, ra, rb, imm = 0; - ULong opd[4]; - ULong opd_src_map, opd_dst_map, opd_imm_map; - Int use_dirty_helper; - IRTemp t0, t1, t2, t3, t4; - IRTemp tb[4]; - IRTemp rd_wb_temp[6]; - ULong rd_wb_reg[6]; - /* Tilegx is a VLIW processor, we have to commit register write after read.*/ - Int rd_wb_index; - Int n = 0, nr_insn; - DisResult dres; - - /* The running delta */ - Long delta = delta64; - - /* Holds pc at the start of the insn, so that we can print - consistent error messages for unimplemented insns. */ - //Long delta_start = delta; - - UChar *code = (UChar *) (guest_code + delta); - - IRStmt *bstmt = NULL; /* Branch statement. */ - IRExpr *next = NULL; /* Next bundle expr. */ - ULong jumpkind = Ijk_Boring; - ULong steering_pc; - - /* Set result defaults. */ - dres.whatNext = Dis_Continue; - dres.len = 0; - dres.continueAt = 0; - dres.jk_StopHere = Ijk_INVALID; - dres.hint = Dis_HintNone; - - /* Verify the code addr is 8-byte aligned. */ - vassert((((Addr)code) & 7) == 0); - - /* Get the instruction bundle. */ - cins = *((ULong *)(Addr) code); - - /* "Special" instructions. */ - /* Spot the 16-byte preamble: ****tilegx**** - 0:02b3c7ff91234fff { moveli zero, 4660 ; moveli zero, 22136 } - 8:0091a7ff95678fff { moveli zero, 22136 ; moveli zero, 4660 } - */ -#define CL_W0 0x02b3c7ff91234fffULL -#define CL_W1 0x0091a7ff95678fffULL - - if (*((ULong*)(Addr)(code)) == CL_W0 && - *((ULong*)(Addr)(code + 8)) == CL_W1) { - /* Got a "Special" instruction preamble. Which one is it? */ - if (*((ULong*)(Addr)(code + 16)) == - 0x283a69a6d1483000ULL /* or r13, r13, r13 */ ) { - /* r0 = client_request ( r12 ) */ - DIP("r0 = client_request ( r12 )\n"); - - putPC(mkU64(guest_PC_curr_instr + 24)); - - dres.jk_StopHere = Ijk_ClientReq; - dres.whatNext = Dis_StopHere; - dres.len = 24; - goto decode_success; - - } else if (*((ULong*)(Addr)(code + 16)) == - 0x283a71c751483000ULL /* or r14, r14, r14 */ ) { - /* r11 = guest_NRADDR */ - DIP("r11 = guest_NRADDR\n"); - dres.len = 24; - putIReg(11, IRExpr_Get(offsetof(VexGuestTILEGXState, guest_NRADDR), - Ity_I64)); - putPC(mkU64(guest_PC_curr_instr + 8)); - goto decode_success; - - } else if (*((ULong*)(Addr)(code + 16)) == - 0x283a79e7d1483000ULL /* or r15, r15, r15 */ ) { - /* branch-and-link-to-noredir r12 */ - DIP("branch-and-link-to-noredir r12\n"); - dres.len = 24; - putIReg(55, mkU64(guest_PC_curr_instr + 24)); - - putPC(getIReg(12)); - - dres.jk_StopHere = Ijk_NoRedir; - dres.whatNext = Dis_StopHere; - goto decode_success; - - } else if (*((ULong*)(Addr)(code + 16)) == - 0x283a5965d1483000ULL /* or r11, r11, r11 */ ) { - /* vex-inject-ir */ - DIP("vex-inject-ir\n"); - dres.len = 24; - - vex_inject_ir(irsb, Iend_LE); - - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_CMSTART), - mkU64(guest_PC_curr_instr))); - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_CMLEN), - mkU64(24))); - - /* 2 + 1 = 3 bundles. 24 bytes. */ - putPC(mkU64(guest_PC_curr_instr + 24)); - - dres.jk_StopHere = Ijk_InvalICache; - dres.whatNext = Dis_StopHere; - goto decode_success; - } - - /* We don't expect this. */ - vex_printf("%s: unexpect special bundles at %lx\n", - __func__, (Addr)guest_PC_curr_instr); - delta += 16; - goto decode_failure; - /*NOTREACHED*/ - } - - /* To decode the given instruction bundle. */ - nr_insn = parse_insn_tilegx((tilegx_bundle_bits)cins, - (ULong)(Addr)code, - decoded); - - if (vex_traceflags & VEX_TRACE_FE) - decode_and_display(&cins, 1, (ULong)(Addr)code); - - /* Init. rb_wb_index */ - rd_wb_index = 0; - - steering_pc = -1ULL; - - for (n = 0; n < nr_insn; n++) { - opcode = decoded[n].opcode->mnemonic; - Int opi; - - rd = ra = rb = -1; - opd[0] = opd[1] = opd[2] = opd[3] = -1; - opd_dst_map = 0; - opd_src_map = 0; - opd_imm_map = 0; - - for (opi = 0; opi < decoded[n].opcode->num_operands; opi++) { - const struct tilegx_operand *op = decoded[n].operands[opi]; - opd[opi] = decoded[n].operand_values[opi]; - - /* Set the operands. rd, ra, rb and imm. */ - if (opi < 3) { - if (op->is_dest_reg) { - if (rd == -1) - rd = decoded[n].operand_values[opi]; - else if (ra == -1) - ra = decoded[n].operand_values[opi]; - } else if (op->is_src_reg) { - if (ra == -1) { - ra = decoded[n].operand_values[opi]; - } else if(rb == -1) { - rb = decoded[n].operand_values[opi]; - } else { - vassert(0); - } - } else { - imm = decoded[n].operand_values[opi]; - } - } - - /* Build bit maps of used dest, source registers - and immediate. */ - if (op->is_dest_reg) { - opd_dst_map |= 1ULL << opi; - if(op->is_src_reg) - opd_src_map |= 1ULL << opi; - } else if(op->is_src_reg) { - opd_src_map |= 1ULL << opi; - } else { - opd_imm_map |= 1ULL << opi; - } - } - - use_dirty_helper = 0; - - switch (opcode) { - case 0: /* "bpt" */ /* "raise" */ - /* "bpt" pseudo instruction is an illegal instruction */ - opd_imm_map |= (1 << 0); - opd[0] = cins; - use_dirty_helper = 1; - break; - case 1: /* "info" */ /* Ignore this instruction. */ - break; - case 2: /* "infol" */ /* Ignore this instruction. */ - break; - case 3: /* "ld4s_tls" */ /* Ignore this instruction. */ - break; - case 4: /* "ld_tls" */ /* Ignore this instruction. */ - break; - case 5: /* "move" */ - t2 = newTemp(Ity_I64); - assign(t2, getIReg(ra)); - MARK_REG_WB(rd, t2); - break; - case 6: /* "movei" */ - t2 = newTemp(Ity_I64); - assign(t2, mkU64(extend_s_8to64(imm))); - MARK_REG_WB(rd, t2); - break; - case 7: /* "moveli" */ - t2 = newTemp(Ity_I64); - assign(t2, mkU64(extend_s_16to64(imm))); - MARK_REG_WB(rd, t2); - break; - case 8: /* "prefetch" */ /* Ignore. */ - break; - case 9: /* "prefetch_add_l1" */ /* Ignore. */ - break; - case 10: /* "prefetch_add_l1_fault" */ /* Ignore. */ - break; - case 11: /* "prefetch_add_l2" */ /* Ignore. */ - break; - case 12: /* "prefetch_add_l2_fault" */ /* Ignore. */ - break; - case 13: /* "prefetch_add_l3" */ /* Ignore. */ - break; - case 14: /* "prefetch_add_l3_fault" */ /* Ignore. */ - break; - case 15: /* "prefetch_l1" */ /* Ignore. */ - break; - case 16: /* "prefetch_l1_fault" */ /* Ignore. */ - break; - case 17: /* "prefetch_l2" */ /* Ignore. */ - break; - case 18: /* "prefetch_l2_fault" */ /* Ignore. */ - break; - case 19: /* "prefetch_l3" */ /* Ignore. */ - break; - case 20: /* "prefetch_l3_fault" */ /* Ignore. */ - break; - case 21: /* "raise" */ - /* "raise" pseudo instruction is an illegal instruction plusing - a "moveli zero, ", so we need save whole bundle in the - opd[0], which will be used in the dirty helper. */ - opd_imm_map |= (1 << 0); - opd[0] = cins; - use_dirty_helper = 1; - break; - case 22: /* "add" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, getIReg(ra), getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 23: /* "addi" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, getIReg(ra), - mkU64(extend_s_8to64(imm)))); - MARK_REG_WB(rd, t2); - break; - case 24: /* "addli" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, getIReg(ra), - mkU64(extend_s_16to64(imm)))); - MARK_REG_WB(rd, t2); - break; - case 25: /* "addx" */ - t2 = newTemp(Ity_I64); - assign(t2, signExtend(binop(Iop_Add32, - narrowTo(Ity_I32, getIReg(ra)), - narrowTo(Ity_I32, getIReg(rb))), - 32)); - MARK_REG_WB(rd, t2); - break; - case 26: /* "addxi" */ - t2 = newTemp(Ity_I64); - assign(t2, signExtend(binop(Iop_Add32, - narrowTo(Ity_I32, getIReg(ra)), - mkU32(imm)), 32)); - MARK_REG_WB(rd, t2); - break; - case 27: /* "addxli" */ - t2 = newTemp(Ity_I64); - assign(t2, signExtend(binop(Iop_Add32, - narrowTo(Ity_I32, getIReg(ra)), - mkU32(imm)), 32)); - - MARK_REG_WB(rd, t2); - break; - case 28: /* "addxsc" */ - use_dirty_helper = 1; - break; - case 29: /* "and" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_And64, getIReg(ra), getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 30: /* "andi" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_And64, getIReg(ra), - mkU64(extend_s_8to64(imm)))); - MARK_REG_WB(rd, t2); - break; - case 31: /* "beqz" */ - /* Fall-through */ - case 32: - /* "beqzt" */ - bstmt = dis_branch(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)), - imm); - break; - case 33: /* "bfexts" */ - { - ULong imm0 = decoded[n].operand_values[3]; - ULong mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1)); - t0 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t0, binop(Iop_Xor64, - binop(Iop_Sub64, - binop(Iop_And64, - binop(Iop_Shr64, - getIReg(ra), - mkU8(imm0)), - mkU64(1)), - mkU64(1)), - mkU64(-1ULL))); - assign(t2, - binop(Iop_Or64, - binop(Iop_And64, - binop(Iop_Or64, - binop(Iop_Shr64, - getIReg(ra), - mkU8(imm)), - binop(Iop_Shl64, - getIReg(ra), - mkU8(64 - imm))), - mkU64(mask)), - binop(Iop_And64, - mkexpr(t0), - mkU64(~mask)))); - - MARK_REG_WB(rd, t2); - } - break; - case 34: /* "bfextu" */ - { - ULong imm0 = decoded[n].operand_values[3]; - ULong mask = 0; - t2 = newTemp(Ity_I64); - mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1)); - - assign(t2, - binop(Iop_And64, - binop(Iop_Or64, - binop(Iop_Shr64, - getIReg(ra), - mkU8(imm)), - binop(Iop_Shl64, - getIReg(ra), - mkU8(64 - imm))), - mkU64(mask))); - MARK_REG_WB(rd, t2); - } - break; - case 35: /* "bfins" */ - { - ULong mask; - ULong imm0 = decoded[n].operand_values[3]; - t0 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - if (imm <= imm0) - { - mask = ((-1ULL << imm) ^ ((-1ULL << imm0) << 1)); - } - else - { - mask = ((-1ULL << imm) | (-1ULL >> (63 - imm0))); - } - - assign(t0, binop(Iop_Or64, - binop(Iop_Shl64, - getIReg(ra), - mkU8(imm)), - binop(Iop_Shr64, - getIReg(ra), - mkU8(64 - imm)))); - - assign(t2, binop(Iop_Or64, - binop(Iop_And64, - mkexpr(t0), - mkU64(mask)), - binop(Iop_And64, - getIReg(rd), - mkU64(~mask)))); - - MARK_REG_WB(rd, t2); - } - break; - case 36: /* "bgez" */ - /* Fall-through */ - case 37: /* "bgezt" */ - bstmt = dis_branch(binop(Iop_CmpEQ64, - binop(Iop_And64, - getIReg(ra), - mkU64(0x8000000000000000ULL)), - mkU64(0x0)), - imm); - break; - case 38: /* "bgtz" */ - /* Fall-through */ - case 39: - /* "bgtzt" */ - bstmt = dis_branch(unop(Iop_Not1, - binop(Iop_CmpLE64S, - getIReg(ra), - mkU64(0))), - imm); - break; - case 40: /* "blbc" */ - /* Fall-through */ - case 41: /* "blbct" */ - bstmt = dis_branch(unop(Iop_64to1, - unop(Iop_Not64, getIReg(ra))), - imm); - - break; - case 42: /* "blbs" */ - /* Fall-through */ - case 43: - /* "blbst" */ - bstmt = dis_branch(unop(Iop_64to1, - getIReg(ra)), - imm); - break; - case 44: /* "blez" */ - bstmt = dis_branch(binop(Iop_CmpLE64S, getIReg(ra), - mkU64(0)), - imm); - break; - case 45: /* "blezt" */ - bstmt = dis_branch(binop(Iop_CmpLE64S, getIReg(ra), - mkU64(0)), - imm); - break; - case 46: /* "bltz" */ - bstmt = dis_branch(binop(Iop_CmpLT64S, getIReg(ra), - mkU64(0)), - imm); - break; - case 47: /* "bltzt" */ - bstmt = dis_branch(binop(Iop_CmpLT64S, getIReg(ra), - mkU64(0)), - imm); - break; - case 48: /* "bnez" */ - /* Fall-through */ - case 49: - /* "bnezt" */ - bstmt = dis_branch(binop(Iop_CmpNE64, getIReg(ra), - mkU64(0)), - imm); - break; - case 50: /* "clz" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_Clz64, getIReg(ra))); - - MARK_REG_WB(rd, t2); - break; - case 51: /* "cmoveqz rd, ra, rb" */ - t2 = newTemp(Ity_I64); - assign(t2, IRExpr_ITE(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)), - getIReg(rb), getIReg(rd))); - MARK_REG_WB(rd, t2); - break; - case 52: /* "cmovnez" */ - t2 = newTemp(Ity_I64); - assign(t2, IRExpr_ITE(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)), - getIReg(rd), getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 53: /* "cmpeq" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, binop(Iop_CmpEQ64, - getIReg(ra), getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - - case 54: /* "cmpeqi" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, binop(Iop_CmpEQ64, - getIReg(ra), - mkU64(extend_s_8to64(imm))))); - MARK_REG_WB(rd, t2); - break; - case 55: /* "cmpexch" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - - assign(t1, getIReg(rb)); - stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t2, Iend_LE, - getIReg(ra), - NULL, binop(Iop_Add64, - getIReg(70), - getIReg(71)), - NULL, mkexpr(t1)))); - MARK_REG_WB(rd, t2); - break; - case 56: /* "cmpexch4" */ - t1 = newTemp(Ity_I32); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I32); - - assign(t1, narrowTo(Ity_I32, getIReg(rb))); - stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t3, Iend_LE, - getIReg(ra), - NULL, - narrowTo(Ity_I32, binop(Iop_Add64, - getIReg(70), - getIReg(71))), - NULL, - mkexpr(t1)))); - assign(t2, unop(Iop_32Uto64, mkexpr(t3))); - MARK_REG_WB(rd, t2); - break; - case 57: /* "cmples" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpLE64S, getIReg(ra), getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 58: /* "cmpleu" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpLE64U, getIReg(ra), getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 59: /* "cmplts" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpLT64S, getIReg(ra), getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 60: /* "cmpltsi" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpLT64S, - getIReg(ra), - mkU64(extend_s_8to64(imm))))); - MARK_REG_WB(rd, t2); - break; - case 61: - - /* "cmpltu" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpLT64U, getIReg(ra), getIReg(rb)))); - MARK_REG_WB(rd, t2); - - - break; - case 62: /* "cmpltui" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpLT64U, - getIReg(ra), - mkU64(imm)))); - MARK_REG_WB(rd, t2); - - - break; - case 63: /* "cmpne" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_1Uto64, - binop(Iop_CmpNE64, getIReg(ra), getIReg(rb)))); - MARK_REG_WB(rd, t2); - - - break; - case 64: - /* Fall-through */ - case 65: - /* Fall-through */ - case 66: - /* Fall-through */ - case 67: - /* Fall-through */ - case 68: - /* Fall-through */ - case 69: - /* Fall-through */ - case 70: - /* Fall-through */ - case 71: - /* Fall-through */ - case 72: - use_dirty_helper = 1; - break; - case 73: /* "ctz" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_Ctz64, getIReg(ra))); - - MARK_REG_WB(rd, t2); - - - break; - case 74: /* "dblalign" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - - /* t0 is the bit shift amount */ - assign(t0, binop(Iop_Shl64, - binop(Iop_And64, - getIReg(rb), - mkU64(7)), - mkU8(3))); - assign(t1, binop(Iop_Sub64, - mkU64(64), - mkexpr(t0))); - - assign(t2, binop(Iop_Or64, - binop(Iop_Shl64, - getIReg(ra), - unop(Iop_64to8, mkexpr(t1))), - binop(Iop_Shr64, - getIReg(rd), - unop(Iop_64to8, mkexpr(t0))))); - - MARK_REG_WB(rd, t2); - break; - case 75: - /* Fall-through */ - case 76: - /* Fall-through */ - case 77: - /* Fall-through */ - case 78: - /* Fall-through */ - case 79: - use_dirty_helper = 1; - break; - case 80: /* "exch" */ - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t2, - Iend_LE, - getIReg(ra), - NULL, - mkU64(0x0), - NULL, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 81: /* "exch4 rd, ra, rb" */ - t0 = newTemp(Ity_I32); - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t0, - Iend_LE, - getIReg(ra), - NULL, - mkU32(0x0), - NULL, - narrowTo(Ity_I32, - getIReg(rb))))); - assign(t2, unop(Iop_32Sto64, mkexpr(t0))); - MARK_REG_WB(rd, t2); - break; - case 82: - /* Fall-through */ - case 83: - /* Fall-through */ - case 84: - /* Fall-through */ - case 85: - /* Fall-through */ - case 86: - /* Fall-through */ - case 87: - /* Fall-through */ - case 88: - /* Fall-through */ - case 89: - use_dirty_helper = 1; - break; - case 90: /* "fetchadd" */ - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t2, - Iend_LE, - getIReg(ra), - NULL, - // fetchadd=3 - mkU64(0x3), - NULL, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 91: /* "fetchadd4" */ - t0 = newTemp(Ity_I32); - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t0, - Iend_LE, - getIReg(ra), - NULL, - // fetchadd=3 - mkU32(0x3), - NULL, - narrowTo(Ity_I32, - getIReg(rb))))); - assign(t2, unop(Iop_32Sto64, mkexpr(t0))); - MARK_REG_WB(rd, t2); - - break; - case 92: /* "fetchaddgez" */ - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t2, - Iend_LE, - getIReg(ra), - NULL, - // fetchaddgez=5 - mkU64(0x5), - NULL, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 93: /* "fetchaddgez4" */ - t0 = newTemp(Ity_I32); - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t0, - Iend_LE, - getIReg(ra), - NULL, - // fetchaddgez=5 - mkU32(0x5), - NULL, - narrowTo(Ity_I32, - getIReg(rb))))); - assign(t2, unop(Iop_32Sto64, mkexpr(t0))); - MARK_REG_WB(rd, t2); - break; - case 94: /* "fetchand\n") */ - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t2, - Iend_LE, - getIReg(ra), - NULL, - mkU64(0x2), - NULL, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 95: - /* mkIRCAS. - 0: xch### 1: cmpexch###, - 2: fetchand## 3: fetchadd## - 4: fetchor## 5: fetchaddgez - */ - /* "fetchand4" */ - t0 = newTemp(Ity_I32); - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t0, - Iend_LE, - getIReg(ra), - NULL, - mkU32(0x2), - NULL, - narrowTo(Ity_I32, - getIReg(rb))))); - assign(t2, unop(Iop_32Sto64, mkexpr(t0))); - MARK_REG_WB(rd, t2); - break; - case 96: /* "fetchor" */ - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t2, - Iend_LE, - getIReg(ra), - NULL, - mkU64(0x4), - NULL, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 97: /* "fetchor4" */ - t0 = newTemp(Ity_I32); - t2 = newTemp(Ity_I64); - stmt( IRStmt_CAS( - mkIRCAS(IRTemp_INVALID, - t0, - Iend_LE, - getIReg(ra), - NULL, - mkU32(0x4), - NULL, - narrowTo(Ity_I32, - getIReg(rb))))); - assign(t2, unop(Iop_32Sto64, mkexpr(t0))); - MARK_REG_WB(rd, t2); - break; - case 98: - /* Fall-through */ - case 99: - /* Fall-through */ - case 100: - use_dirty_helper = 1; - break; - case 101: /* "fnop" Ignore */ - break; - case 102: - /* Fall-through */ - case 103: - /* Fall-through */ - case 104: - /* Fall-through */ - case 105: - /* Fall-through */ - case 106: - /* Fall-through */ - case 107: - /* Fall-through */ - case 108: - use_dirty_helper = 1; - break; - case 109: - /* Fall-through */ - case 110: - /* Fall-through */ - case 111: - use_dirty_helper = 1; - break; - case 112: /* "iret" */ - next = mkU64(guest_PC_curr_instr + 8); - jumpkind = Ijk_Ret; - break; - case 113: /* "j" */ - next = mkU64(imm); - /* set steering address. */ - steering_pc = imm; - jumpkind = Ijk_Boring; - break; - case 114: - t2 = newTemp(Ity_I64); - assign(t2, mkU64(guest_PC_curr_instr + 8)); - /* set steering address. */ - steering_pc = imm; - next = mkU64(imm); - jumpkind = Ijk_Call; - MARK_REG_WB(55, t2); - break; - case 115: /* "jalr" */ - /* Fall-through */ - case 116: /* "jalrp" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, getIReg(ra)); - assign(t2, mkU64(guest_PC_curr_instr + 8)); - next = mkexpr(t1); - jumpkind = Ijk_Call; - MARK_REG_WB(55, t2); - break; - case 117: /* "jr" */ - /* Fall-through */ - case 118: /* "jrp" */ - next = getIReg(ra); - jumpkind = Ijk_Boring; - break; - case 119: /* "ld" */ - t2 = newTemp(Ity_I64); - assign(t2, load(Ity_I64, (getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 120: /* "ld1s" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_8Sto64, - load(Ity_I8, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - break; - case 121: /* "ld1s_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_8Sto64, - load(Ity_I8, (getIReg(ra))))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 122: /* "ld1u" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_8Uto64, - load(Ity_I8, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - - break; - case 123: /* "ld1u_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_8Uto64, - load(Ity_I8, (getIReg(ra))))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 124: /* "ld2s" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_16Sto64, - load(Ity_I16, getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 125: /* "ld2s_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_16Sto64, - load(Ity_I16, getIReg(ra)))); - MARK_REG_WB(rd, t2); - MARK_REG_WB(ra, t1); - break; - case 126: /* "ld2u" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_16Uto64, - load(Ity_I16, getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 127: /* "ld2u_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_16Uto64, - load(Ity_I16, getIReg(ra)))); - MARK_REG_WB(rd, t2); - MARK_REG_WB(ra, t1); - break; - case 128: /* "ld4s" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - load(Ity_I32, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - break; - case 129: /* "ld4s_add" */ - t2 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_32Sto64, - load(Ity_I32, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - MARK_REG_WB(ra, t1); - break; - case 130: /* "ld4u" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Uto64, - load(Ity_I32, getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 131: /* "ld4u_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_32Uto64, - load(Ity_I32, getIReg(ra)))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 132: /* "ld_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, load(Ity_I64, getIReg(ra))); - assign(t2, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(ra, t2); - MARK_REG_WB(rd, t1); - break; - case 133: /* "ldna" */ - t2 = newTemp(Ity_I64); - assign(t2, load(Ity_I64, - binop(Iop_And64, - getIReg(ra), - unop(Iop_Not64, - mkU64(7))))); - MARK_REG_WB(rd, t2); - break; - case 134: /* "ldna_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, load(Ity_I64, - binop(Iop_And64, - getIReg(ra), - unop(Iop_Not64, - mkU64(7))))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 135: /* "ldnt" */ - /* Valgrind IR has no Non-Temp load. Use normal load. */ - t2 = newTemp(Ity_I64); - assign(t2, load(Ity_I64, (getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 136: /* "ldnt1s" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_8Sto64, - load(Ity_I8, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - break; - case 137: /* "ldnt1s_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_8Sto64, - load(Ity_I8, (getIReg(ra))))); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 138: /* "ldnt1u" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_8Uto64, - load(Ity_I8, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - break; - case 139: /* "ldnt1u_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - assign(t2, unop(Iop_8Uto64, - load(Ity_I8, (getIReg(ra))))); - - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 140: /* "ldnt2s" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_16Sto64, - load(Ity_I16, getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 141: /* "ldnt2s_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_16Sto64, - load(Ity_I16, getIReg(ra)))); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 142: /* "ldnt2u" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_16Uto64, - load(Ity_I16, getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 143: /* "ldnt2u_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_16Uto64, - load(Ity_I16, getIReg(ra)))); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(ra, t1); - MARK_REG_WB(rd, t2); - break; - case 144: /* "ldnt4s" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - load(Ity_I32, (getIReg(ra))))); - MARK_REG_WB(rd, t2); - break; - case 145: /* "ldnt4s_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - load(Ity_I32, (getIReg(ra))))); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(rd, t2); - MARK_REG_WB(ra, t1); - break; - case 146: /* "ldnt4u" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Uto64, - load(Ity_I32, getIReg(ra)))); - MARK_REG_WB(rd, t2); - break; - case 147: /* "ldnt4u_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Uto64, - load(Ity_I32, getIReg(ra)))); - assign(t1, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(rd, t2); - MARK_REG_WB(ra, t1); - break; - case 148: /* "ldnt_add" */ - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t1, load(Ity_I64, getIReg(ra))); - assign(t2, binop(Iop_Add64, getIReg(ra), mkU64(imm))); - MARK_REG_WB(rd, t1); - MARK_REG_WB(ra, t2); - break; - case 149: /* "lnk" */ - t2 = newTemp(Ity_I64); - assign(t2, mkU64(guest_PC_curr_instr + 8)); - MARK_REG_WB(rd, t2); - break; - case 150: /* "mf" */ - use_dirty_helper = 1; - break; - case 151: /* "mfspr" */ - t2 = newTemp(Ity_I64); - if (imm == 0x2780) { // Get Cmpexch value - assign(t2, getIReg(70)); - MARK_REG_WB(rd, t2); - } else if (imm == 0x2580) { // Get EX_CONTEXT_0_0 - assign(t2, getIReg(576 / 8)); - MARK_REG_WB(rd, t2); - } else if (imm == 0x2581) { // Get EX_CONTEXT_0_1 - assign(t2, getIReg(584 / 8)); - MARK_REG_WB(rd, t2); - } else - use_dirty_helper = 1; - break; - case 152: /* "mm" */ - use_dirty_helper = 1; - break; - case 153: /* "mnz" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_And64, - unop(Iop_1Sto64, binop(Iop_CmpNE64, - getIReg(ra), - mkU64(0))), - getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 154: /* "mtspr imm, ra" */ - if (imm == 0x2780) // Set Cmpexch value - putIReg(70, getIReg(ra)); - else if (imm == 0x2580) // set EX_CONTEXT_0_0 - putIReg(576/8, getIReg(ra)); - else if (imm == 0x2581) // set EX_CONTEXT_0_1 - putIReg(584/8, getIReg(ra)); - else - use_dirty_helper = 1; - break; - case 155: /* "mul_hs_hs" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullS32, - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(ra), - mkU8(32))), - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(rb), - mkU8(32))))); - MARK_REG_WB(rd, t2); - break; - case 156: /* "mul_hs_hu" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Shr64, getIReg(ra), mkU8(32))))); - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32))))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32))))); - assign(t2, binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32)))); - MARK_REG_WB(rd, t2); - break; - case 157: /* "mul_hs_ls" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullS32, - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(ra), - mkU8(32))), - unop(Iop_64to32, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 158: /* "mul_hs_lu" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Shr64, getIReg(ra), mkU8(32))))); - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, getIReg(rb)))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, getIReg(rb)))); - assign(t2, binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32)))); - MARK_REG_WB(rd, t2); - break; - case 159: /* "mul_hu_hu" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullU32, - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(ra), - mkU8(32))), - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(rb), - mkU8(32))))); - MARK_REG_WB(rd, t2); - break; - case 160: /* "mul_hu_ls" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, - getIReg(ra)))); - - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32))))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, binop(Iop_Shr64, getIReg(rb), mkU8(32))))); - assign(t2, binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32)))); - MARK_REG_WB(rd, t2); - break; - case 161: /* "mul_hu_lu" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullU32, - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(ra), - mkU8(32))), - unop(Iop_64to32, - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 162: /* "mul_ls_ls" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullS32, - unop(Iop_64to32, getIReg(ra)), - unop(Iop_64to32, getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 163: /* "mul_ls_lu" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, getIReg(ra)))); - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, getIReg(rb)))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, getIReg(rb)))); - assign(t2, binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32)))); - MARK_REG_WB(rd, t2); - break; - case 164: /* "mul_lu_lu" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullU32, - unop(Iop_64to32, getIReg(ra)), - unop(Iop_64to32, getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 165: /* "mula_hs_hs" */ - t0 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - - assign(t0, binop(Iop_MullS32, - unop(Iop_64to32, binop(Iop_Shr64, - getIReg(ra), mkU8(32))), - unop(Iop_64to32, binop(Iop_Shr64, - getIReg(rb), mkU8(32))))); - assign(t2, binop(Iop_Add64, getIReg(rd), mkexpr(t0))); - MARK_REG_WB(rd, t2); - break; - case 166: /* "mula_hs_hu" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - t4 = newTemp(Ity_I64); - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Shr64, getIReg(ra), mkU8(32))))); - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, binop(Iop_Shr64, - getIReg(rb), mkU8(32))))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, binop(Iop_Shr64, - getIReg(rb), mkU8(32))))); - assign(t2, binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32)))); - assign(t4, binop(Iop_Add64, getIReg(rd), mkexpr(t2))); - MARK_REG_WB(rd, t4); - break; - case 167: /* "mula_hs_ls" */ - t2 = newTemp(Ity_I64); - t4 = newTemp(Ity_I64); - assign(t2, binop(Iop_MullS32, - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(ra), - mkU8(32))), - unop(Iop_64to32, - getIReg(rb)))); - assign(t4, binop(Iop_Add64, getIReg(rd), mkexpr(t2))); - MARK_REG_WB(rd, t4); - break; - case 168: /* "mula_hs_lu" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - t4 = newTemp(Ity_I64); - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Shr64, getIReg(ra), mkU8(32))))); - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, getIReg(rb)))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, getIReg(rb)))); - assign(t2, binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32)))); - assign(t4, binop(Iop_Add64, getIReg(rd), mkexpr(t2))); - MARK_REG_WB(rd, t4); - break; - case 169: /* "mula_hu_hu" */ - use_dirty_helper = 1; - break; - case 170: /* "mula_hu_ls" */ - use_dirty_helper = 1; - break; - case 171: /* "mula_hu_lu" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, - binop(Iop_MullU32, - unop(Iop_64to32, - binop(Iop_Shr64, - getIReg(ra), - mkU8(32))), - unop(Iop_64to32, - getIReg(rb))), - getIReg(rd))); - MARK_REG_WB(rd, t2); - break; - case 172: /* "mula_ls_ls" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, - getIReg(rd), - binop(Iop_MullS32, - unop(Iop_64to32, getIReg(ra)), - unop(Iop_64to32, getIReg(rb))))); - MARK_REG_WB(rd, t2); - break; - case 173: /* "mula_ls_lu" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - - assign(t0, unop(Iop_32Sto64, - unop(Iop_64to32, getIReg(ra)))); - assign(t1, binop(Iop_MullU32, - unop(Iop_64to32, mkexpr(t0)), - unop(Iop_64to32, getIReg(rb)))); - assign(t3, binop(Iop_MullU32, - unop(Iop_64to32, binop(Iop_Shr64, - mkexpr(t0), - mkU8(32))), - unop(Iop_64to32, getIReg(rb)))); - assign(t2, binop(Iop_Add64, - getIReg(rd), - binop(Iop_Add64, - mkexpr(t1), - binop(Iop_Shl64, - mkexpr(t3), - mkU8(32))))); - MARK_REG_WB(rd, t2); - break; - case 174: /* "mula_lu_lu" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, - binop(Iop_MullU32, - unop(Iop_64to32, - getIReg(ra)), - unop(Iop_64to32, - getIReg(rb))), - getIReg(rd))); - MARK_REG_WB(rd, t2); - break; - case 175: /* "mulax" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Add64, - getIReg(rd), - binop(Iop_MullU32, - narrowTo(Ity_I32, getIReg(ra)), - narrowTo(Ity_I32, getIReg(rb))))))); - MARK_REG_WB(rd, t2); - break; - case 176: /* "mulx" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_MullU32, - narrowTo(Ity_I32, getIReg(ra)), - narrowTo(Ity_I32, getIReg(rb)))))); - MARK_REG_WB(rd, t2); - break; - case 177: /* "mz" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_And64, - unop(Iop_1Sto64, binop(Iop_CmpEQ64, - getIReg(ra), - mkU64(0))), - getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 178: /* "nap" */ - break; - case 179: /* "nop" */ - break; - case 180: /* "nor" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_Not64, - binop(Iop_Or64, - getIReg(ra), - getIReg(rb)))); - MARK_REG_WB(rd, t2); - break; - case 181: /* "or" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Or64, - getIReg(ra), - getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 182: /* "ori" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Or64, - getIReg(ra), - mkU64(imm))); - MARK_REG_WB(rd, t2); - break; - case 183: - /* Fall-through */ - case 184: - /* Fall-through */ - case 185: - use_dirty_helper = 1; - break; - case 186: /* "rotl" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t0, binop(Iop_Shl64, - getIReg(ra), - unop(Iop_64to8, getIReg(rb)))); - assign(t1, binop(Iop_Shr64, - getIReg(ra), - unop(Iop_64to8, binop(Iop_Sub64, - mkU64(0), - getIReg(rb))))); - assign(t2, binop(Iop_Or64, mkexpr(t0), mkexpr(t1))); - MARK_REG_WB(rd, t2); - break; - case 187: /* "rotli" */ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I64); - assign(t0, binop(Iop_Shl64, - getIReg(ra), - mkU8(imm))); - assign(t1, binop(Iop_Shr64, - getIReg(ra), - mkU8(0 - imm))); - assign(t2, binop(Iop_Or64, mkexpr(t0), mkexpr(t1))); - MARK_REG_WB(rd, t2); - break; - case 188: /* "shl" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Shl64, - getIReg(ra), - unop(Iop_64to8, getIReg(rb)))); - MARK_REG_WB(rd, t2); - - break; - case 189: /* "shl16insli" */ - t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_I64); - assign(t3, binop(Iop_Shl64, getIReg(ra), mkU8(16))); - imm &= 0xFFFFULL; - if (imm & 0x8000) - { - t4 = newTemp(Ity_I64); - assign(t4, mkU64(imm)); - assign(t2, binop(Iop_Add64, mkexpr(t3), mkexpr(t4))); - } - else - { - assign(t2, binop(Iop_Add64, mkexpr(t3), mkU64(imm))); - } - MARK_REG_WB(rd, t2); - - break; - case 190: /* "shl1add" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, - binop(Iop_Shl64, - getIReg(ra), mkU8(1)), - getIReg(rb))); - - MARK_REG_WB(rd, t2); - break; - case 191: /* "shl1addx" */ - t2 = newTemp(Ity_I64); - assign(t2, - unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Add64, - binop(Iop_Shl64, - getIReg(ra), mkU8(1)), - getIReg(rb))))); - MARK_REG_WB(rd, t2); - break; - case 192: /* "shl2add" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, - binop(Iop_Shl64, - getIReg(ra), mkU8(2)), - getIReg(rb))); - - MARK_REG_WB(rd, t2); - - break; - case 193: /* "shl2addx" */ - t2 = newTemp(Ity_I64); - assign(t2, - unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Add64, - binop(Iop_Shl64, - getIReg(ra), mkU8(2)), - getIReg(rb))))); - MARK_REG_WB(rd, t2); - - break; - case 194: /* "shl3add" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Add64, - binop(Iop_Shl64, - getIReg(ra), mkU8(3)), - getIReg(rb))); - - MARK_REG_WB(rd, t2); - break; - case 195: /* "shl3addx" */ - t2 = newTemp(Ity_I64); - assign(t2, - unop(Iop_32Sto64, - unop(Iop_64to32, - binop(Iop_Add64, - binop(Iop_Shl64, - getIReg(ra), mkU8(3)), - getIReg(rb))))); - MARK_REG_WB(rd, t2); - break; - case 196: /* "shli" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Shl64, getIReg(ra), - mkU8(imm))); - MARK_REG_WB(rd, t2); - break; - case 197: /* "shlx" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - binop(Iop_Shl32, - narrowTo(Ity_I32, getIReg(ra)), - narrowTo(Ity_I8, getIReg(rb))))); - MARK_REG_WB(rd, t2); - break; - case 198: /* "shlxi" */ - t2 = newTemp(Ity_I64); - assign(t2, signExtend(binop(Iop_Shl32, - narrowTo(Ity_I32, getIReg(ra)), - mkU8(imm)), - 32)); - MARK_REG_WB(rd, t2); - break; - case 199: /* "shrs" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Sar64, getIReg(ra), - narrowTo(Ity_I8, getIReg(rb)))); - - MARK_REG_WB(rd, t2); - break; - case 200: /* "shrsi" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Sar64, getIReg(ra), - mkU8(imm))); - - MARK_REG_WB(rd, t2); - break; - case 201: /* "shru" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Shr64, - getIReg(ra), - narrowTo(Ity_I8, (getIReg(rb))))); - - MARK_REG_WB(rd, t2); - break; - case 202: /* "shrui" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Shr64, getIReg(ra), mkU8(imm))); - - MARK_REG_WB(rd, t2); - break; - case 203: /* "shrux" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - (binop(Iop_Shr32, - narrowTo(Ity_I32, getIReg(ra)), - narrowTo(Ity_I8, getIReg(rb)))))); - MARK_REG_WB(rd, t2); - break; - case 204: /* "shruxi" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - (binop(Iop_Shr32, - narrowTo(Ity_I32, getIReg(ra)), - mkU8(imm))))); - MARK_REG_WB(rd, t2); - break; - case 205: /* "shufflebytes" */ - use_dirty_helper = 1; - break; - case 206: /* "st" */ - store(getIReg(ra), getIReg(rb)); - break; - case 207: /* "st1" */ - store(getIReg(ra), narrowTo(Ity_I8, getIReg(rb))); - break; - case 208: /* "st1_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), narrowTo(Ity_I8, getIReg(opd[1]))); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 209: /* "st2" */ - store(getIReg(ra), narrowTo(Ity_I16, getIReg(rb))); - break; - case 210: /* "st2_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), narrowTo(Ity_I16, getIReg(opd[1]))); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 211: /* "st4" */ - store(getIReg(ra), narrowTo(Ity_I32, getIReg(rb))); - break; - case 212: /* "st4_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), narrowTo(Ity_I32, getIReg(opd[1]))); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 213: /* "st_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), getIReg(opd[1])); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 214: /* "stnt" */ - store(getIReg(ra), getIReg(rb)); - break; - case 215: /* "stnt1" */ - store(getIReg(ra), narrowTo(Ity_I8, getIReg(rb))); - break; - case 216: /* "stnt1_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), narrowTo(Ity_I8, getIReg(opd[1]))); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 217: /* "stnt2" */ - store(getIReg(ra), narrowTo(Ity_I16, getIReg(rb))); - break; - case 218: /* "stnt2_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), narrowTo(Ity_I16, getIReg(opd[1]))); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 219: /* "stnt4" */ - store(getIReg(ra), narrowTo(Ity_I32, getIReg(rb))); - break; - case 220: /* "stnt4_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), narrowTo(Ity_I32, getIReg(opd[1]))); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 221: /* "stnt_add" */ - t2 = newTemp(Ity_I64); - store(getIReg(opd[0]), getIReg(opd[1])); - assign(t2, binop(Iop_Add64, getIReg(opd[0]), mkU64(opd[2]))); - MARK_REG_WB(opd[0], t2); - break; - case 222: /* "sub" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Sub64, getIReg(ra), - getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 223: /* "subx" */ - t2 = newTemp(Ity_I64); - assign(t2, unop(Iop_32Sto64, - binop(Iop_Sub32, - narrowTo(Ity_I32, getIReg(ra)), - narrowTo(Ity_I32, getIReg(rb))))); - MARK_REG_WB(rd, t2); - break; - case 224: /* "subxsc" */ - use_dirty_helper = 1; - break; - case 225: /* "swint0" */ - vex_printf( "\n *** swint0 ***\n"); - vassert(0); - break; - case 226: /* "swint1" */ - next = mkU64(guest_PC_curr_instr + 8); - jumpkind = Ijk_Sys_syscall; - break; - case 227: /* "swint2" */ - vex_printf( "\n *** swint2 ***\n"); - vassert(0); - break; - case 228: /* "swint3" */ - vex_printf( "\n *** swint3 ***\n"); - vassert(0); - break; - case 229: - /* Fall-through */ - case 230: - /* Fall-through */ - case 231: - /* Fall-through */ - case 232: - /* Fall-through */ - case 233: - use_dirty_helper = 1; - break; - case 234: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - case 235: - /* Fall-through */ - case 236: - /* Fall-through */ - case 237: - use_dirty_helper = 1; - break; - case 238: /* "v1cmpeq" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_CmpEQ8x8, getIReg(ra), - getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 239: /* "v1cmpeqi" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_CmpEQ8x8, getIReg(ra), - mkU64(imm))); - - MARK_REG_WB(rd, t2); - break; - case 240: - /* Fall-through */ - case 241: - /* Fall-through */ - case 242: - use_dirty_helper = 1; - break; - case 243: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - /* Fall-through */ - case 244: - use_dirty_helper = 1; - break; - case 245: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - case 246: /* "v1cmpne" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_CmpEQ8x8, - binop(Iop_CmpEQ8x8, getIReg(ra), - getIReg(rb)), - getIReg(63))); - MARK_REG_WB(rd, t2); - break; - case 247: - /* Fall-through */ - case 248: - /* Fall-through */ - case 249: - /* Fall-through */ - case 250: - /* Fall-through */ - case 251: - /* Fall-through */ - case 252: - /* Fall-through */ - case 253: - /* Fall-through */ - case 254: - /* Fall-through */ - case 255: - /* Fall-through */ - case 256: - /* Fall-through */ - case 257: - /* Fall-through */ - case 258: - /* Fall-through */ - case 259: - use_dirty_helper = 1; - break; - case 260: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - case 261: - use_dirty_helper = 1; - break; - case 262: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - case 263: - /* Fall-through */ - case 264: - /* Fall-through */ - case 265: - /* Fall-through */ - case 266: - /* Fall-through */ - case 267: - /* Fall-through */ - case 268: - /* Fall-through */ - case 269: - /* Fall-through */ - case 270: - use_dirty_helper = 1; - break; - case 271: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - case 272: - use_dirty_helper = 1; - break; - case 273: - opd[3] = V1EXP(opd[3]); - use_dirty_helper = 1; - break; - case 274: - use_dirty_helper = 1; - break; - case 275: /* "v1shrui" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Shr8x8, - getIReg(ra), - mkU64(imm))); - MARK_REG_WB(rd, t2); - break; - case 276: - /* Fall-through */ - case 277: - /* Fall-through */ - case 278: - use_dirty_helper = 1; - break; - case 279: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 280: - /* Fall-through */ - case 281: - /* Fall-through */ - case 282: - /* Fall-through */ - case 283: - use_dirty_helper = 1; - break; - case 284: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 285: - /* Fall-through */ - case 286: - /* Fall-through */ - case 287: - use_dirty_helper = 1; - break; - case 288: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 289: - use_dirty_helper = 1; - break; - case 290: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 291: - /* Fall-through */ - case 292: - /* Fall-through */ - case 293: - /* Fall-through */ - case 294: - /* Fall-through */ - case 295: - /* Fall-through */ - case 296: - use_dirty_helper = 1; - break; - case 297: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 298: - use_dirty_helper = 1; - break; - case 299: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 300: - /* Fall-through */ - case 301: - /* Fall-through */ - case 302: - /* Fall-through */ - case 303: - /* Fall-through */ - case 304: - /* Fall-through */ - case 305: - /* Fall-through */ - case 306: - /* Fall-through */ - case 307: - /* Fall-through */ - case 308: - /* Fall-through */ - case 309: - /* Fall-through */ - case 310: - /* Fall-through */ - case 311: - /* Fall-through */ - case 312: - use_dirty_helper = 1; - break; - case 313: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 314: - /* Fall-through */ - case 315: - use_dirty_helper = 1; - break; - case 316: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 317: - use_dirty_helper = 1; - break; - case 318: - opd[3] = V2EXP(opd[3]); - use_dirty_helper = 1; - break; - case 319: - /* Fall-through */ - case 320: - /* Fall-through */ - case 321: - /* Fall-through */ - case 322: - /* Fall-through */ - case 323: - use_dirty_helper = 1; - break; - case 324: /* "v4int_l" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Or64, - binop(Iop_Shl64, - getIReg(ra), - mkU8(32)), - binop(Iop_And64, - getIReg(rb), - mkU64(0xFFFFFFFF)))); - MARK_REG_WB(rd, t2); - break; - case 325: - /* Fall-through */ - case 326: - /* Fall-through */ - case 327: - /* Fall-through */ - case 328: - /* Fall-through */ - case 329: - /* Fall-through */ - case 330: - /* Fall-through */ - case 331: - use_dirty_helper = 1; - break; - case 332: /* "wh64" */ /* Ignore store hint */ - break; - case 333: /* "xor" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Xor64, - getIReg(ra), - getIReg(rb))); - MARK_REG_WB(rd, t2); - break; - case 334: /* "xori" */ - t2 = newTemp(Ity_I64); - assign(t2, binop(Iop_Xor64, - getIReg(ra), - mkU64(imm))); - MARK_REG_WB(rd, t2); - break; - case 335: /* "(null)" */ /* ignore */ - break; - default: - - decode_failure: - vex_printf("error: %d\n", (Int)opcode); - - /* All decode failures end up here. */ - vex_printf("vex tilegx->IR: unhandled instruction: " - "%s 0x%llx 0x%llx 0x%llx 0x%llx\n", - decoded[n].opcode->name, - opd[0], opd[1], opd[2], opd[3]); - - /* Tell the dispatcher that this insn cannot be decoded, and so has - not been executed, and (is currently) the next to be executed. */ - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), - mkU64(guest_PC_curr_instr))); - dres.whatNext = Dis_StopHere; - dres.len = 0; - return dres; - } - - /* Hook the dirty helper for rare instruxtions. */ - if (use_dirty_helper) - { - Int i = 0; - Int wbc = 0; - IRExpr *opc_oprand[5]; - - opc_oprand[0] = mkU64(opcode); - - /* Get the operand registers or immediate. */ - for (i = 0 ; i < 4; i++) - { - opc_oprand[i + 1] = NULL; - - if (opd_dst_map & (1ULL << i)) - { - tb[wbc] = newTemp(Ity_I64); - wbc++; - opc_oprand[i + 1] = getIReg(opd[i]); - } - else if (opd_imm_map & (1ULL << i)) - opc_oprand[i + 1] = mkU64(opd[i]); - else if (opd_src_map & (1ULL << i)) - opc_oprand[i + 1] = getIReg(opd[i]); - else - opc_oprand[i + 1] = mkU64(0xfeee); - } - - IRExpr **args = mkIRExprVec_5(opc_oprand[0], opc_oprand[1], - opc_oprand[2], opc_oprand[3], - opc_oprand[4]); - IRDirty *genIR = NULL; - - switch (wbc) { - case 0: - { - genIR = unsafeIRDirty_0_N (0/*regparms*/, - "tilegx_dirtyhelper_gen", - &tilegx_dirtyhelper_gen, - args); - } - break; - case 1: - { - genIR = unsafeIRDirty_1_N (tb[0], - 0/*regparms*/, - "tilegx_dirtyhelper_gen", - &tilegx_dirtyhelper_gen, - args); - } - break; - default: - vex_printf("opc = %d\n", (Int)opcode); - vassert(0); - } - - stmt(IRStmt_Dirty(genIR)); - - wbc = 0; - for (i = 0 ; i < 4; i++) - { - if(opd_dst_map & (1 << i)) - { - /* Queue the writeback destination registers. */ - MARK_REG_WB(opd[i], tb[wbc]); - wbc++; - } - } - } - } - - /* Write back registers for a bundle. Note have to get all source registers - for all instructions in a bundle before write the destinations b/c this is - an VLIW processor. */ - for (n = 0; n < rd_wb_index; n++) - putIReg(rd_wb_reg[n], mkexpr(rd_wb_temp[n])); - - /* Add branch IR if apply finally, only upto one branch per bundle. */ - if (bstmt) { - stmt(bstmt); - dres.whatNext = Dis_StopHere; - - dres.jk_StopHere = jumpkind; - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), - mkU64(guest_PC_curr_instr + 8))); - } else if (next) { - if (steering_pc != -1ULL) { - if (resteerOkFn(callback_opaque, steering_pc)) { - dres.whatNext = Dis_ResteerU; - dres.continueAt = steering_pc; - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), - mkU64(steering_pc))); - } else { - dres.whatNext = Dis_StopHere; - dres.jk_StopHere = jumpkind; - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), - mkU64(steering_pc))); - } - } else { - dres.whatNext = Dis_StopHere; - dres.jk_StopHere = jumpkind; - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), next)); - } - } else { - /* As dafault dres.whatNext = Dis_Continue. */ - stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_pc), - mkU64(guest_PC_curr_instr + 8))); - } - - irsb->jumpkind = Ijk_Boring; - irsb->next = NULL; - dres.len = 8; - - decode_success: - - return dres; -} - -/*------------------------------------------------------------*/ -/*--- Top-level fn ---*/ -/*------------------------------------------------------------*/ - -/* Disassemble a single instruction into IR. The instruction - is located in host memory at &guest_code[delta]. */ - -DisResult -disInstr_TILEGX ( IRSB* irsb_IN, - Bool (*resteerOkFn) (void *, Addr), - Bool resteerCisOk, - void* callback_opaque, - const UChar* guest_code_IN, - Long delta, - Addr guest_IP, - VexArch guest_arch, - const VexArchInfo* archinfo, - const VexAbiInfo* abiinfo, - VexEndness host_endness_IN, - Bool sigill_diag_IN ) -{ - DisResult dres; - - /* Set globals (see top of this file) */ - vassert(guest_arch == VexArchTILEGX); - - guest_code = (UChar*)(Addr)guest_code_IN; - irsb = irsb_IN; - host_endness = host_endness_IN; - guest_PC_curr_instr = (Addr64) guest_IP; - guest_PC_bbstart = (Addr64) toUInt(guest_IP - delta); - - dres = disInstr_TILEGX_WRK(resteerOkFn, resteerCisOk, - callback_opaque, - delta, archinfo, abiinfo, sigill_diag_IN); - - return dres; -} - -/*--------------------------------------------------------------------*/ -/*--- end guest_tilegx_toIR.c ---*/ -/*--------------------------------------------------------------------*/ diff --git a/VEX/priv/host_tilegx_defs.c b/VEX/priv/host_tilegx_defs.c deleted file mode 100644 index a3f756c9df..0000000000 --- a/VEX/priv/host_tilegx_defs.c +++ /dev/null @@ -1,2628 +0,0 @@ - -/*---------------------------------------------------------------*/ -/*--- begin host_tilegx_defs.c ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2010-2017 Tilera Corp. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - -/* Contributed by Zhi-Gang Liu */ - -#include "libvex_basictypes.h" -#include "libvex.h" -#include "libvex_trc_values.h" - -#include "main_util.h" -#include "host_generic_regs.h" -#include "host_tilegx_defs.h" -#include "tilegx_disasm.h" - -/* Contributed by Zhi-Gang Liu */ - -/* Register number for guest state pointer in host code, r50 */ -#define GuestSP ( 50) -/* CONTEXT_EX0 offset */ -#define OFFSET_EX0 (576) -/* CONTEXT_EX1 offset */ -#define OFFSET_EX1 (584) -/* COND offset */ -#define OFFSET_COND (608) -/* PC offset */ -#define OFFSET_PC (512) - -/* guest_COND offset. */ -#define COND_OFFSET() OFFSET_COND - -/*---------------- Registers ----------------*/ - -void ppHRegTILEGX ( HReg reg ) -{ - Int r; - static const HChar *ireg_names[64] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", - "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", - "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", - "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49", - "r50", "r51", "r52", "r53", "r54", "r55", - "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero" - }; - - /* Be generic for all virtual regs. */ - if (hregIsVirtual(reg)) { - ppHReg(reg); - return; - } - - /* But specific for real regs. */ - vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || - hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64); - - /* But specific for real regs. */ - switch (hregClass(reg)) { - case HRcInt32: - case HRcInt64: - r = hregEncoding(reg); - vassert(r >= 0 && r < 64); - vex_printf("%s", ireg_names[r]); - return; - case HRcFlt32: - r = hregEncoding(reg); - vassert(r >= 0 && r < 64); - vex_printf("%s", ireg_names[r]); - return; - case HRcFlt64: - r = hregEncoding(reg); - vassert(r >= 0 && r < 64); - vex_printf("%s", ireg_names[r]); - return; - default: - vpanic("ppHRegTILEGX"); - } - - return; -} - -static const HChar* tilegxUnaryOp [] = - { - "clz ", - "ctz ", - "nop " - }; - -static const HChar* tilegxAluOp [] = - { "Alu_invalid", - "Add ", - "Sub ", - "And ", - "Or ", - "Nor ", - "Xor " - }; - -static const HChar* tilegxShftOp [] = - { - "Shft_invalid", - "Sll ", - "Srl ", - "Sra ", - "Sll8x8 ", - "Srl8x8 ", - }; - -static const HChar* tilegxBfOp [] = - { - "BfExts ", - "BfEtxu ", - "BfIns " - }; - - -static const HChar* tilegxAcasOp [] = - { - "CmpExch ", - "Exch ", - "FetchAnd ", - "FetchAdd ", - "FetchAddgez", - "FetchOr " - }; - -static const HChar* tilegxInstrTag [] = - { - "Imm ", - "ALU ", - "Shift ", - "Unary ", - "Cmp ", - "CmpI ", - "Mul ", - "Call ", - "XDirect ", - "XIndir ", - "XAssisted", - "EvCheck ", - "ProfInc ", - "RdWrLR ", - "Load ", - "Store ", - "MovCond ", - "BitField ", - "ACAS " - }; - -/* -------- Pretty Print instructions ------------- */ -static void ppLoadImm ( HReg dst, ULong imm ) -{ - vex_printf("li "); - ppHRegTILEGX(dst); - vex_printf(",0x%016lx", (unsigned long)imm); -} - -void ppTILEGXInstr ( const TILEGXInstr * instr ) -{ - vex_printf("%s ", tilegxInstrTag[instr->tag]); - switch (instr->tag) { - case GXin_LI: { - ppHRegTILEGX(instr->GXin.LI.dst); - vex_printf(",0x%016llx", instr->GXin.LI.imm); - } - break; - - case GXin_Alu: { - HReg r_srcL = instr->GXin.Alu.srcL; - TILEGXRH *rh_srcR = instr->GXin.Alu.srcR; - /* generic */ - vex_printf("%s ", tilegxAluOp[instr->GXin.Alu.op]); - ppHRegTILEGX(instr->GXin.Alu.dst); - vex_printf(","); - ppHRegTILEGX(r_srcL); - vex_printf(","); - ppTILEGXRH(rh_srcR); - } - break; - - case GXin_Shft: { - HReg r_srcL = instr->GXin.Shft.srcL; - TILEGXRH *rh_srcR = instr->GXin.Shft.srcR; - vex_printf("%s ", tilegxShftOp[instr->GXin.Shft.op]); - ppHRegTILEGX(instr->GXin.Shft.dst); - vex_printf(","); - ppHRegTILEGX(r_srcL); - vex_printf(","); - ppTILEGXRH(rh_srcR); - } - break; - - case GXin_Unary: { - vex_printf("%s ", tilegxUnaryOp[instr->GXin.Unary.op]); - ppHRegTILEGX(instr->GXin.Unary.dst); - vex_printf(","); - ppHRegTILEGX(instr->GXin.Unary.src); - } - break; - - case GXin_Cmp: { - ppHRegTILEGX(instr->GXin.Cmp.dst); - vex_printf(" = %s ( ", showTILEGXCondCode(instr->GXin.Cmp.cond)); - ppHRegTILEGX(instr->GXin.Cmp.srcL); - vex_printf(", "); - ppHRegTILEGX(instr->GXin.Cmp.srcR); - vex_printf(" )"); - } - break; - - case GXin_CmpI: { - ppHRegTILEGX(instr->GXin.CmpI.dst); - vex_printf(" = %s ( ", showTILEGXCondCode(instr->GXin.CmpI.cond)); - ppHRegTILEGX(instr->GXin.CmpI.srcL); - vex_printf(", "); - ppTILEGXRH(instr->GXin.CmpI.srcR); - vex_printf(" )"); - } - break; - - case GXin_Mul: { - if (instr->GXin.Mul.widening == False) { - vex_printf("mul "); - ppHRegTILEGX(instr->GXin.Mul.dst); - vex_printf(", "); - ppHRegTILEGX(instr->GXin.Mul.srcL); - vex_printf(", "); - ppHRegTILEGX(instr->GXin.Mul.srcR); - - } else { - vex_printf("%s ", instr->GXin.Mul.syned ? "mull32s" : "mull32u"); - ppHRegTILEGX(instr->GXin.Mul.dst); - vex_printf(", "); - ppHRegTILEGX(instr->GXin.Mul.srcL); - vex_printf(", "); - ppHRegTILEGX(instr->GXin.Mul.srcR); - } - } - break; - - case GXin_Call: { - Int n; - if (instr->GXin.Call.cond != TILEGXcc_AL) { - vex_printf("if (%s (", showTILEGXCondCode(instr->GXin.Call.cond)); - ppHRegTILEGX(instr->GXin.Call.src); - vex_printf(",zero))"); - } - else - vex_printf("(always) "); - - vex_printf("{ "); - ppLoadImm(hregTILEGX_R11(), instr->GXin.Call.target); - - vex_printf(" ; ["); - for (n = 0; n < 56; n++) { - if (instr->GXin.Call.argiregs & (1ULL << n)) { - vex_printf("r%d", n); - if ((instr->GXin.Call.argiregs >> n) > 1) - vex_printf(","); - } - } - vex_printf("] }"); - } - break; - - case GXin_XDirect: - vex_printf("(xDirect) "); - vex_printf("if (guest_COND.%s) { ", - showTILEGXCondCode(instr->GXin.XDirect.cond)); - vex_printf("move r11, 0x%x,", (UInt)instr->GXin.XDirect.dstGA); - vex_printf("; st r11, "); - ppTILEGXAMode(instr->GXin.XDirect.amPC); - vex_printf("; move r11, $disp_cp_chain_me_to_%sEP; jalr r11; nop}", - instr->GXin.XDirect.toFastEP ? "fast" : "slow"); - return; - case GXin_XIndir: - vex_printf("(xIndir) "); - vex_printf("if (guest_COND.%s) { st ", - showTILEGXCondCode(instr->GXin.XIndir.cond)); - ppHRegTILEGX(instr->GXin.XIndir.dstGA); - vex_printf(", "); - ppTILEGXAMode(instr->GXin.XIndir.amPC); - vex_printf("; move r11, $disp_indir; jalr r11; nop}"); - return; - case GXin_XAssisted: - vex_printf("(xAssisted) "); - vex_printf("if (guest_COND.%s) { ", - showTILEGXCondCode(instr->GXin.XAssisted.cond)); - vex_printf("st "); - ppHRegTILEGX(instr->GXin.XAssisted.dstGA); - vex_printf(", "); - ppTILEGXAMode(instr->GXin.XAssisted.amPC); - vex_printf("; move r50, $IRJumpKind_to_TRCVAL(%d)", - (Int)instr->GXin.XAssisted.jk); - vex_printf("; move r11, $disp_assisted; jalr r11; nop; }"); - return; - - case GXin_EvCheck: - vex_printf("(evCheck) ld r11, "); - ppTILEGXAMode(instr->GXin.EvCheck.amCounter); - vex_printf("; addli r11, r11, -1"); - vex_printf("; st r11, "); - ppTILEGXAMode(instr->GXin.EvCheck.amCounter); - vex_printf("; bgez r11, nofail; jalr *"); - ppTILEGXAMode(instr->GXin.EvCheck.amFailAddr); - vex_printf("; nofail:"); - return; - case GXin_ProfInc: - vex_printf("(profInc) move r11, ($NotKnownYet); " - "ld r8, r11; " - "addi r8, r8, 1; " - "st r11, r8; " ); - return; - case GXin_Load: { - UChar sz = instr->GXin.Load.sz; - UChar c_sz = sz == 1 ? '1' : sz == 2 ? '2' : sz == 4 ? '4' : '8'; - vex_printf("ld%c ", c_sz); - ppHRegTILEGX(instr->GXin.Load.dst); - vex_printf(","); - ppTILEGXAMode(instr->GXin.Load.src); - } - break; - - case GXin_Store: { - UChar sz = instr->GXin.Store.sz; - UChar c_sz = sz == 1 ? '1' : sz == 2 ? '2' : sz == 4 ? '4' : '8'; - vex_printf("st%c ", c_sz); - ppTILEGXAMode(instr->GXin.Store.dst); - vex_printf(","); - ppHRegTILEGX(instr->GXin.Store.src); - } - break; - - case GXin_MovCond: { - ppHRegTILEGX(instr->GXin.MovCond.dst); - vex_printf("="); - showTILEGXCondCode(instr->GXin.MovCond.cond); - vex_printf("?"); - ppHRegTILEGX(instr->GXin.MovCond.srcL); - vex_printf(":"); - ppTILEGXRH(instr->GXin.MovCond.srcR); - } - break; - - case GXin_Acas: { - vex_printf("%s ", tilegxAcasOp[instr->GXin.Acas.op]); - ppHRegTILEGX(instr->GXin.Acas.old); - vex_printf(","); - if (instr->GXin.Acas.op == GXacas_CMPEXCH) { - ppHRegTILEGX(instr->GXin.Acas.exp); - vex_printf(","); - } - ppHRegTILEGX(instr->GXin.Acas.new); - } - break; - - case GXin_Bf: { - vex_printf("%s ", tilegxBfOp[instr->GXin.Bf.op]); - ppHRegTILEGX(instr->GXin.Bf.dst); - vex_printf(","); - ppHRegTILEGX(instr->GXin.Bf.src); - vex_printf(","); - vex_printf("%d,%d", (Int)instr->GXin.Bf.Start, (Int)instr->GXin.Bf.End); - } - break; - - default: - vassert(0); - } -} - - -const RRegUniverse* getRRegUniverse_TILEGX ( void ) -{ - /* The 'universe' is constant and BIG, do it statically. */ - static RRegUniverse rRegUniverse_TILEGX; - static UInt rRegUniverse_TILEGX_initted = False; - - /* Get a pointer of the 'universe' */ - RRegUniverse* ru = &rRegUniverse_TILEGX; - - if (LIKELY(rRegUniverse_TILEGX_initted)) - return ru; - - RRegUniverse__init(ru); - - /* Callee saves ones are listed first, since we prefer them - if they're available */ - - ru->regs[ru->size++] = hregTILEGX_R30(); - ru->regs[ru->size++] = hregTILEGX_R31(); - ru->regs[ru->size++] = hregTILEGX_R32(); - ru->regs[ru->size++] = hregTILEGX_R33(); - ru->regs[ru->size++] = hregTILEGX_R34(); - ru->regs[ru->size++] = hregTILEGX_R35(); - ru->regs[ru->size++] = hregTILEGX_R36(); - ru->regs[ru->size++] = hregTILEGX_R37(); - ru->regs[ru->size++] = hregTILEGX_R38(); - ru->regs[ru->size++] = hregTILEGX_R39(); - - ru->regs[ru->size++] = hregTILEGX_R40(); - ru->regs[ru->size++] = hregTILEGX_R41(); - ru->regs[ru->size++] = hregTILEGX_R42(); - ru->regs[ru->size++] = hregTILEGX_R43(); - ru->regs[ru->size++] = hregTILEGX_R44(); - ru->regs[ru->size++] = hregTILEGX_R45(); - ru->regs[ru->size++] = hregTILEGX_R46(); - ru->regs[ru->size++] = hregTILEGX_R47(); - ru->regs[ru->size++] = hregTILEGX_R48(); - ru->regs[ru->size++] = hregTILEGX_R49(); - - /* GPR 50 is reserved as Guest state */ - /* GPR 51 is reserved register, mainly used to do memory - load and store since TileGx has no pre-displacement - addressing mode */ - - ru->regs[ru->size++] = hregTILEGX_R10(); - - /* GPR 11 is reserved as next guest address */ - - ru->regs[ru->size++] = hregTILEGX_R13(); - ru->regs[ru->size++] = hregTILEGX_R14(); - ru->regs[ru->size++] = hregTILEGX_R15(); - ru->regs[ru->size++] = hregTILEGX_R16(); - ru->regs[ru->size++] = hregTILEGX_R17(); - ru->regs[ru->size++] = hregTILEGX_R18(); - ru->regs[ru->size++] = hregTILEGX_R19(); - ru->regs[ru->size++] = hregTILEGX_R20(); - ru->regs[ru->size++] = hregTILEGX_R21(); - ru->regs[ru->size++] = hregTILEGX_R22(); - ru->regs[ru->size++] = hregTILEGX_R23(); - ru->regs[ru->size++] = hregTILEGX_R24(); - ru->regs[ru->size++] = hregTILEGX_R25(); - ru->regs[ru->size++] = hregTILEGX_R26(); - ru->regs[ru->size++] = hregTILEGX_R27(); - ru->regs[ru->size++] = hregTILEGX_R28(); - ru->regs[ru->size++] = hregTILEGX_R29(); - - ru->allocable = ru->size; - - /* And other unallocable registers. */ - ru->regs[ru->size++] = hregTILEGX_R0(); - ru->regs[ru->size++] = hregTILEGX_R1(); - ru->regs[ru->size++] = hregTILEGX_R2(); - ru->regs[ru->size++] = hregTILEGX_R3(); - ru->regs[ru->size++] = hregTILEGX_R4(); - ru->regs[ru->size++] = hregTILEGX_R5(); - ru->regs[ru->size++] = hregTILEGX_R6(); - ru->regs[ru->size++] = hregTILEGX_R7(); - ru->regs[ru->size++] = hregTILEGX_R8(); - ru->regs[ru->size++] = hregTILEGX_R9(); - ru->regs[ru->size++] = hregTILEGX_R11(); - ru->regs[ru->size++] = hregTILEGX_R12(); - ru->regs[ru->size++] = hregTILEGX_R50(); - ru->regs[ru->size++] = hregTILEGX_R51(); - ru->regs[ru->size++] = hregTILEGX_R52(); - ru->regs[ru->size++] = hregTILEGX_R53(); - ru->regs[ru->size++] = hregTILEGX_R54(); - ru->regs[ru->size++] = hregTILEGX_R55(); - ru->regs[ru->size++] = hregTILEGX_R63(); - - rRegUniverse_TILEGX_initted = True; - - RRegUniverse__check_is_sane(ru); - - return ru; -} - -/*----------------- Condition Codes ----------------------*/ - -const HChar *showTILEGXCondCode ( TILEGXCondCode cond ) -{ - switch (cond) { - case TILEGXcc_EQ: - return "e"; /* equal */ - case TILEGXcc_EQ8x8: - return "e8x8"; /* equal */ - - case TILEGXcc_NE: - return "ne"; /* not equal */ - case TILEGXcc_NE8x8: - return "ne8x8"; /* not equal */ - - case TILEGXcc_HS: - return "hs"; /* >=u (higher or same) */ - case TILEGXcc_LO: - return "lo"; /* u (higher) */ - case TILEGXcc_LS: - return "ls"; /* <=u (lower or same) */ - - case TILEGXcc_GE: - return "ge"; /* >=s (signed greater or equal) */ - case TILEGXcc_LT: - return "lt"; /* s (signed greater) */ - case TILEGXcc_LE: - return "le"; /* <=s (signed less or equal) */ - - case TILEGXcc_AL: - return "al"; /* always (unconditional) */ - case TILEGXcc_NV: - return "nv"; /* never (unconditional): */ - case TILEGXcc_EZ: - return "ez"; /* equal 0 */ - case TILEGXcc_NZ: - return "nz"; /* not equal 0 */ - - default: - vpanic("showTILEGXCondCode"); - } -} - - -/* --------- TILEGXAMode: memory address expressions. --------- */ - -TILEGXAMode *TILEGXAMode_IR ( Int idx, HReg base ) -{ - TILEGXAMode *am = LibVEX_Alloc(sizeof(TILEGXAMode)); - am->tag = GXam_IR; - am->GXam.IR.base = base; - am->GXam.IR.index = idx; - - return am; -} - -TILEGXAMode *nextTILEGXAModeInt ( TILEGXAMode * am ) -{ - if (am->tag == GXam_IR) - return TILEGXAMode_IR(am->GXam.IR.index + 4, am->GXam.IR.base); - - vpanic("dopyTILEGXAMode"); -} - -void ppTILEGXAMode ( const TILEGXAMode * am ) -{ - if (am->tag == GXam_IR) - { - if (am->GXam.IR.index == 0) - vex_printf("("); - else - vex_printf("%d(", (Int) am->GXam.IR.index); - ppHRegTILEGX(am->GXam.IR.base); - vex_printf(")"); - return; - } - vpanic("ppTILEGXAMode"); -} - -static void addRegUsage_TILEGXAMode ( HRegUsage * u, TILEGXAMode * am ) -{ - if (am->tag == GXam_IR) - { - addHRegUse(u, HRmRead, am->GXam.IR.base); - return; - } - - vpanic("addRegUsage_TILEGXAMode"); -} - -static void mapRegs_TILEGXAMode ( HRegRemap * m, TILEGXAMode * am ) -{ - if (am->tag == GXam_IR) - { - am->GXam.IR.base = lookupHRegRemap(m, am->GXam.IR.base); - return; - } - - vpanic("mapRegs_TILEGXAMode"); -} - -/* --------- Operand, which can be a reg or a u16/s16. --------- */ - -TILEGXRH *TILEGXRH_Imm ( Bool syned, UShort imm16 ) -{ - TILEGXRH *op = LibVEX_Alloc(sizeof(TILEGXRH)); - op->tag = GXrh_Imm; - op->GXrh.Imm.syned = syned; - op->GXrh.Imm.imm16 = imm16; - /* If this is a signed value, ensure it's not -32768, so that we - are guaranteed always to be able to negate if needed. */ - if (syned) - vassert(imm16 != 0x8000); - vassert(syned == True || syned == False); - return op; -} - -TILEGXRH *TILEGXRH_Reg ( HReg reg ) -{ - TILEGXRH *op = LibVEX_Alloc(sizeof(TILEGXRH)); - op->tag = GXrh_Reg; - op->GXrh.Reg.reg = reg; - return op; -} - -void ppTILEGXRH ( const TILEGXRH * op ) -{ - TILEGXRHTag tag = op->tag; - switch (tag) { - case GXrh_Imm: - if (op->GXrh.Imm.syned) - vex_printf("%d", (Int) (Short) op->GXrh.Imm.imm16); - else - vex_printf("%u", (UInt) (UShort) op->GXrh.Imm.imm16); - return; - case GXrh_Reg: - ppHRegTILEGX(op->GXrh.Reg.reg); - return; - default: - vpanic("ppTILEGXRH"); - } -} - -/* An TILEGXRH can only be used in a "read" context (what would it mean - to write or modify a literal?) and so we enumerate its registers - accordingly. */ -static void addRegUsage_TILEGXRH ( HRegUsage * u, TILEGXRH * op ) -{ - switch (op->tag) { - case GXrh_Imm: - return; - case GXrh_Reg: - addHRegUse(u, HRmRead, op->GXrh.Reg.reg); - return; - default: - vpanic("addRegUsage_TILEGXRH"); - } -} - -static void mapRegs_TILEGXRH ( HRegRemap * m, TILEGXRH * op ) -{ - switch (op->tag) { - case GXrh_Imm: - return; - case GXrh_Reg: - op->GXrh.Reg.reg = lookupHRegRemap(m, op->GXrh.Reg.reg); - return; - default: - vpanic("mapRegs_TILEGXRH"); - } -} - -TILEGXInstr *TILEGXInstr_LI ( HReg dst, ULong imm ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_LI; - i->GXin.LI.dst = dst; - i->GXin.LI.imm = imm; - return i; -} - -TILEGXInstr *TILEGXInstr_Alu ( TILEGXAluOp op, HReg dst, HReg srcL, - TILEGXRH * srcR ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Alu; - i->GXin.Alu.op = op; - i->GXin.Alu.dst = dst; - i->GXin.Alu.srcL = srcL; - i->GXin.Alu.srcR = srcR; - return i; -} - -TILEGXInstr *TILEGXInstr_Shft ( TILEGXShftOp op, Bool sz32, HReg dst, HReg srcL, - TILEGXRH * srcR ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Shft; - i->GXin.Shft.op = op; - i->GXin.Shft.sz32 = sz32; - i->GXin.Shft.dst = dst; - i->GXin.Shft.srcL = srcL; - i->GXin.Shft.srcR = srcR; - return i; -} - -TILEGXInstr *TILEGXInstr_Unary ( TILEGXUnaryOp op, HReg dst, HReg src ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Unary; - i->GXin.Unary.op = op; - i->GXin.Unary.dst = dst; - i->GXin.Unary.src = src; - return i; -} - -TILEGXInstr *TILEGXInstr_Cmp ( Bool syned, Bool sz32, HReg dst, - HReg srcL, HReg srcR, TILEGXCondCode cond ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Cmp; - i->GXin.Cmp.syned = syned; - i->GXin.Cmp.sz32 = sz32; - i->GXin.Cmp.dst = dst; - i->GXin.Cmp.srcL = srcL; - i->GXin.Cmp.srcR = srcR; - i->GXin.Cmp.cond = cond; - return i; -} - -TILEGXInstr *TILEGXInstr_CmpI ( Bool syned, Bool sz32, HReg dst, - HReg srcL, TILEGXRH * srcR, - TILEGXCondCode cond ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_CmpI; - i->GXin.CmpI.syned = syned; - i->GXin.CmpI.sz32 = sz32; - i->GXin.CmpI.dst = dst; - i->GXin.CmpI.srcL = srcL; - i->GXin.CmpI.srcR = srcR; - i->GXin.CmpI.cond = cond; - return i; -} - -TILEGXInstr *TILEGXInstr_Bf ( TILEGXBfOp op, HReg dst, HReg src, - UInt Start, UInt End ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Bf; - i->GXin.Bf.op = op; - i->GXin.Bf.dst = dst; - i->GXin.Bf.src = src; - i->GXin.Bf.Start = Start; - i->GXin.Bf.End = End; - return i; -} - -TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old, - HReg addr, HReg exp, HReg new, UInt sz ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Acas; - i->GXin.Acas.op = op; - i->GXin.Acas.old = old; - i->GXin.Acas.addr = addr; - i->GXin.Acas.exp = exp; - i->GXin.Acas.new = new; - i->GXin.Acas.sz = sz; - return i; -} - -/* multiply */ -TILEGXInstr *TILEGXInstr_Mul ( Bool syned, Bool wid, Bool sz32, - HReg dst, HReg srcL, - HReg srcR ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Mul; - i->GXin.Mul.syned = syned; - i->GXin.Mul.widening = wid; /* widen=True else False */ - i->GXin.Mul.sz32 = sz32; /* True = 32 bits */ - i->GXin.Mul.dst = dst; - i->GXin.Mul.srcL = srcL; - i->GXin.Mul.srcR = srcR; - return i; -} - -TILEGXInstr *TILEGXInstr_Call ( TILEGXCondCode cond, Addr64 target, - ULong argiregs, - HReg src ) -{ - ULong mask; - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Call; - i->GXin.Call.cond = cond; - i->GXin.Call.target = target; - i->GXin.Call.argiregs = argiregs; - i->GXin.Call.src = src; - - /* Only r0 .. r9 inclusive may be used as arg regs. Hence: */ - mask = (1ULL << 10) - 1; - vassert(0 == (argiregs & ~mask)); - return i; -} - -TILEGXInstr *TILEGXInstr_CallAlways ( TILEGXCondCode cond, Addr64 target, - ULong argiregs ) -{ - ULong mask; - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Call; - i->GXin.Call.cond = cond; - i->GXin.Call.target = target; - i->GXin.Call.argiregs = argiregs; - - /* Only r0 .. r9 inclusive may be used as arg regs. Hence: */ - mask = (1ULL << 10) - 1; - vassert(0 == (argiregs & ~mask)); - return i; -} - -TILEGXInstr *TILEGXInstr_XDirect ( Addr64 dstGA, TILEGXAMode* amPC, - TILEGXCondCode cond, Bool toFastEP ) -{ - TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_XDirect; - i->GXin.XDirect.dstGA = dstGA; - i->GXin.XDirect.amPC = amPC; - i->GXin.XDirect.cond = cond; - i->GXin.XDirect.toFastEP = toFastEP; - return i; -} - -TILEGXInstr *TILEGXInstr_XIndir ( HReg dstGA, TILEGXAMode* amPC, - TILEGXCondCode cond ) -{ - TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_XIndir; - i->GXin.XIndir.dstGA = dstGA; - i->GXin.XIndir.amPC = amPC; - i->GXin.XIndir.cond = cond; - return i; -} - -TILEGXInstr *TILEGXInstr_XAssisted ( HReg dstGA, TILEGXAMode* amPC, - TILEGXCondCode cond, IRJumpKind jk ) -{ - TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_XAssisted; - i->GXin.XAssisted.dstGA = dstGA; - i->GXin.XAssisted.amPC = amPC; - i->GXin.XAssisted.cond = cond; - i->GXin.XAssisted.jk = jk; - return i; -} - -TILEGXInstr *TILEGXInstr_EvCheck ( TILEGXAMode* amCounter, - TILEGXAMode* amFailAddr ) { - TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_EvCheck; - i->GXin.EvCheck.amCounter = amCounter; - i->GXin.EvCheck.amFailAddr = amFailAddr; - return i; -} - -TILEGXInstr* TILEGXInstr_ProfInc ( void ) { - TILEGXInstr* i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_ProfInc; - return i; -} - -TILEGXInstr *TILEGXInstr_Load ( UChar sz, HReg dst, TILEGXAMode * src ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Load; - i->GXin.Load.sz = sz; - i->GXin.Load.src = src; - i->GXin.Load.dst = dst; - vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); - return i; -} - -TILEGXInstr *TILEGXInstr_Store(UChar sz, TILEGXAMode * dst, HReg src) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_Store; - i->GXin.Store.sz = sz; - i->GXin.Store.src = src; - i->GXin.Store.dst = dst; - vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); - return i; -} - -/* Read/Write Link Register */ -TILEGXInstr *TILEGXInstr_RdWrLR ( Bool wrLR, HReg gpr ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_RdWrLR; - i->GXin.RdWrLR.wrLR = wrLR; - i->GXin.RdWrLR.gpr = gpr; - return i; -} - -TILEGXInstr *TILEGXInstr_MovCond ( HReg dst, HReg argL, TILEGXRH * argR, - HReg condR, TILEGXCondCode cond ) -{ - TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr)); - i->tag = GXin_MovCond; - i->GXin.MovCond.dst = dst; - i->GXin.MovCond.srcL = argL; - i->GXin.MovCond.srcR = argR; - i->GXin.MovCond.condR = condR; - i->GXin.MovCond.cond = cond; - return i; -} - -/* --------- Helpers for register allocation. --------- */ - -void getRegUsage_TILEGXInstr ( HRegUsage * u, TILEGXInstr * i ) -{ - initHRegUsage(u); - switch (i->tag) { - case GXin_LI: - addHRegUse(u, HRmWrite, i->GXin.LI.dst); - break; - case GXin_Alu: - addHRegUse(u, HRmRead, i->GXin.Alu.srcL); - addRegUsage_TILEGXRH(u, i->GXin.Alu.srcR); - addHRegUse(u, HRmWrite, i->GXin.Alu.dst); - return; - case GXin_CmpI: - addHRegUse(u, HRmRead, i->GXin.CmpI.srcL); - addRegUsage_TILEGXRH(u, i->GXin.CmpI.srcR); - addHRegUse(u, HRmWrite, i->GXin.CmpI.dst); - return; - case GXin_Shft: - addHRegUse(u, HRmRead, i->GXin.Shft.srcL); - addRegUsage_TILEGXRH(u, i->GXin.Shft.srcR); - addHRegUse(u, HRmWrite, i->GXin.Shft.dst); - return; - case GXin_Cmp: - addHRegUse(u, HRmRead, i->GXin.Cmp.srcL); - addHRegUse(u, HRmRead, i->GXin.Cmp.srcR); - addHRegUse(u, HRmWrite, i->GXin.Cmp.dst); - return; - case GXin_Bf: - addHRegUse(u, HRmRead, i->GXin.Bf.src); - addHRegUse(u, HRmWrite, i->GXin.Bf.dst); - return; - case GXin_Acas: - addHRegUse(u, HRmRead, i->GXin.Acas.addr); - addHRegUse(u, HRmRead, i->GXin.Acas.new); - if (i->GXin.Acas.op == GXacas_CMPEXCH) - addHRegUse(u, HRmRead, i->GXin.Acas.exp); - addHRegUse(u, HRmWrite, i->GXin.Acas.old); - return; - case GXin_Unary: - addHRegUse(u, HRmRead, i->GXin.Unary.src); - addHRegUse(u, HRmWrite, i->GXin.Unary.dst); - return; - case GXin_Mul: - addHRegUse(u, HRmWrite, i->GXin.Mul.dst); - addHRegUse(u, HRmRead, i->GXin.Mul.srcL); - addHRegUse(u, HRmRead, i->GXin.Mul.srcR); - return; - case GXin_Call: { - if (i->GXin.Call.cond != TILEGXcc_AL) - addHRegUse(u, HRmRead, i->GXin.Call.src); - ULong argir; - - // Only need save r10-r29, and r0-r9 is not allocable. - addHRegUse(u, HRmWrite, hregTILEGX_R10()); - addHRegUse(u, HRmWrite, hregTILEGX_R11()); - addHRegUse(u, HRmWrite, hregTILEGX_R12()); - addHRegUse(u, HRmWrite, hregTILEGX_R13()); - addHRegUse(u, HRmWrite, hregTILEGX_R14()); - addHRegUse(u, HRmWrite, hregTILEGX_R15()); - - addHRegUse(u, HRmWrite, hregTILEGX_R16()); - addHRegUse(u, HRmWrite, hregTILEGX_R17()); - addHRegUse(u, HRmWrite, hregTILEGX_R18()); - addHRegUse(u, HRmWrite, hregTILEGX_R19()); - addHRegUse(u, HRmWrite, hregTILEGX_R20()); - addHRegUse(u, HRmWrite, hregTILEGX_R21()); - addHRegUse(u, HRmWrite, hregTILEGX_R22()); - addHRegUse(u, HRmWrite, hregTILEGX_R23()); - - addHRegUse(u, HRmWrite, hregTILEGX_R24()); - addHRegUse(u, HRmWrite, hregTILEGX_R25()); - addHRegUse(u, HRmWrite, hregTILEGX_R26()); - addHRegUse(u, HRmWrite, hregTILEGX_R27()); - - addHRegUse(u, HRmWrite, hregTILEGX_R28()); - addHRegUse(u, HRmWrite, hregTILEGX_R29()); - - /* Now we have to state any parameter-carrying registers - which might be read. This depends on the argiregs field. */ - argir = i->GXin.Call.argiregs; - if (argir & (1 << 9)) - addHRegUse(u, HRmRead, hregTILEGX_R9()); - if (argir & (1 << 8)) - addHRegUse(u, HRmRead, hregTILEGX_R8()); - if (argir & (1 << 7)) - addHRegUse(u, HRmRead, hregTILEGX_R7()); - if (argir & (1 << 6)) - addHRegUse(u, HRmRead, hregTILEGX_R6()); - if (argir & (1 << 5)) - addHRegUse(u, HRmRead, hregTILEGX_R5()); - if (argir & (1 << 4)) - addHRegUse(u, HRmRead, hregTILEGX_R4()); - if (argir & (1 << 3)) - addHRegUse(u, HRmRead, hregTILEGX_R3()); - if (argir & (1 << 2)) - addHRegUse(u, HRmRead, hregTILEGX_R2()); - if (argir & (1 << 1)) - addHRegUse(u, HRmRead, hregTILEGX_R1()); - if (argir & (1 << 0)) - addHRegUse(u, HRmRead, hregTILEGX_R0()); - - vassert(0 == (argir & ~((1ULL << 10) - 1))); - return; - } - case GXin_XDirect: - addRegUsage_TILEGXAMode(u, i->GXin.XDirect.amPC); - return; - case GXin_XIndir: - addHRegUse(u, HRmRead, i->GXin.XIndir.dstGA); - addRegUsage_TILEGXAMode(u, i->GXin.XIndir.amPC); - return; - case GXin_XAssisted: - addHRegUse(u, HRmRead, i->GXin.XAssisted.dstGA); - addRegUsage_TILEGXAMode(u, i->GXin.XAssisted.amPC); - return; - - case GXin_EvCheck: - addRegUsage_TILEGXAMode(u, i->GXin.EvCheck.amCounter); - addRegUsage_TILEGXAMode(u, i->GXin.EvCheck.amFailAddr); - return; - case GXin_ProfInc: - return; - case GXin_Load: - addRegUsage_TILEGXAMode(u, i->GXin.Load.src); - addHRegUse(u, HRmWrite, i->GXin.Load.dst); - return; - case GXin_Store: - addHRegUse(u, HRmRead, i->GXin.Store.src); - addRegUsage_TILEGXAMode(u, i->GXin.Store.dst); - return; - case GXin_RdWrLR: - addHRegUse(u, (i->GXin.RdWrLR.wrLR ? HRmRead : HRmWrite), - i->GXin.RdWrLR.gpr); - return; - case GXin_MovCond: - if (i->GXin.MovCond.srcR->tag == GXrh_Reg) { - addHRegUse(u, HRmRead, i->GXin.MovCond.srcR->GXrh.Reg.reg); - } - addHRegUse(u, HRmRead, i->GXin.MovCond.srcL); - addHRegUse(u, HRmRead, i->GXin.MovCond.condR); - addHRegUse(u, HRmWrite, i->GXin.MovCond.dst); - return; - default: - vpanic("getRegUsage_TILEGXInstr"); - } -} - -/* local helper */ -static void mapReg ( HRegRemap * m, HReg * r ) -{ - *r = lookupHRegRemap(m, *r); -} - -void mapRegs_TILEGXInstr ( HRegRemap * m, TILEGXInstr * i ) -{ - switch (i->tag) { - case GXin_LI: - mapReg(m, &i->GXin.LI.dst); - break; - case GXin_Alu: - mapReg(m, &i->GXin.Alu.srcL); - mapRegs_TILEGXRH(m, i->GXin.Alu.srcR); - mapReg(m, &i->GXin.Alu.dst); - return; - case GXin_CmpI: - mapReg(m, &i->GXin.CmpI.srcL); - mapRegs_TILEGXRH(m, i->GXin.CmpI.srcR); - mapReg(m, &i->GXin.CmpI.dst); - return; - case GXin_Shft: - mapReg(m, &i->GXin.Shft.srcL); - mapRegs_TILEGXRH(m, i->GXin.Shft.srcR); - mapReg(m, &i->GXin.Shft.dst); - return; - case GXin_Cmp: - mapReg(m, &i->GXin.Cmp.srcL); - mapReg(m, &i->GXin.Cmp.srcR); - mapReg(m, &i->GXin.Cmp.dst); - return; - case GXin_Acas: - mapReg(m, &i->GXin.Acas.old); - mapReg(m, &i->GXin.Acas.addr); - mapReg(m, &i->GXin.Acas.new); - if (i->GXin.Acas.op == GXacas_CMPEXCH) - mapReg(m, &i->GXin.Acas.exp); - return; - case GXin_Bf: - mapReg(m, &i->GXin.Bf.src); - mapReg(m, &i->GXin.Bf.dst); - return; - case GXin_Unary: - mapReg(m, &i->GXin.Unary.src); - mapReg(m, &i->GXin.Unary.dst); - return; - case GXin_Mul: - mapReg(m, &i->GXin.Mul.dst); - mapReg(m, &i->GXin.Mul.srcL); - mapReg(m, &i->GXin.Mul.srcR); - return; - case GXin_Call: - { - if (i->GXin.Call.cond != TILEGXcc_AL) - mapReg(m, &i->GXin.Call.src); - return; - } - case GXin_XDirect: - mapRegs_TILEGXAMode(m, i->GXin.XDirect.amPC); - return; - case GXin_XIndir: - mapReg(m, &i->GXin.XIndir.dstGA); - mapRegs_TILEGXAMode(m, i->GXin.XIndir.amPC); - return; - case GXin_XAssisted: - mapReg(m, &i->GXin.XAssisted.dstGA); - mapRegs_TILEGXAMode(m, i->GXin.XAssisted.amPC); - return; - case GXin_EvCheck: - mapRegs_TILEGXAMode(m, i->GXin.EvCheck.amCounter); - mapRegs_TILEGXAMode(m, i->GXin.EvCheck.amFailAddr); - return; - case GXin_ProfInc: - return; - case GXin_Load: - mapRegs_TILEGXAMode(m, i->GXin.Load.src); - mapReg(m, &i->GXin.Load.dst); - return; - case GXin_Store: - mapReg(m, &i->GXin.Store.src); - mapRegs_TILEGXAMode(m, i->GXin.Store.dst); - return; - case GXin_RdWrLR: - mapReg(m, &i->GXin.RdWrLR.gpr); - return; - case GXin_MovCond: - if (i->GXin.MovCond.srcR->tag == GXrh_Reg) { - mapReg(m, &(i->GXin.MovCond.srcR->GXrh.Reg.reg)); - } - mapReg(m, &i->GXin.MovCond.srcL); - mapReg(m, &i->GXin.MovCond.condR); - mapReg(m, &i->GXin.MovCond.dst); - - return; - default: - vpanic("mapRegs_TILEGXInstr"); - } -} - -/* Figure out if i represents a reg-reg move, and if so assign the - source and destination to *src and *dst. If in doubt say No. Used - by the register allocator to do move coalescing. -*/ -Bool isMove_TILEGXInstr ( TILEGXInstr * i, HReg * src, HReg * dst ) -{ - /* Moves between integer regs */ - if (i->tag == GXin_Alu) { - // or Rd,Rs,Rs == mov Rd, Rs - if (i->GXin.Alu.op != GXalu_OR) - return False; - if (i->GXin.Alu.srcR->tag != GXrh_Reg) - return False; - if (!sameHReg(i->GXin.Alu.srcR->GXrh.Reg.reg, i->GXin.Alu.srcL)) - return False; - *src = i->GXin.Alu.srcL; - *dst = i->GXin.Alu.dst; - return True; - } - return False; -} - -/* Generate tilegx spill/reload instructions under the direction of the - register allocator. -*/ -void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, - Int offsetB ) -{ - TILEGXAMode *am; - vassert(offsetB >= 0); - vassert(!hregIsVirtual(rreg)); - *i1 = *i2 = NULL; - am = TILEGXAMode_IR(offsetB, TILEGXGuestStatePointer()); - - switch (hregClass(rreg)) { - case HRcInt64: - *i1 = TILEGXInstr_Store(8, am, rreg); - break; - case HRcInt32: - *i1 = TILEGXInstr_Store(4, am, rreg); - break; - default: - ppHRegClass(hregClass(rreg)); - vpanic("genSpill_TILEGX: unimplemented regclass"); - } -} - -void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, - Int offsetB ) -{ - TILEGXAMode *am; - vassert(!hregIsVirtual(rreg)); - am = TILEGXAMode_IR(offsetB, TILEGXGuestStatePointer()); - - switch (hregClass(rreg)) { - case HRcInt64: - *i1 = TILEGXInstr_Load(8, rreg, am); - break; - case HRcInt32: - *i1 = TILEGXInstr_Load(4, rreg, am); - break; - default: - ppHRegClass(hregClass(rreg)); - vpanic("genReload_TILEGX: unimplemented regclass"); - break; - } -} - -/* --------- The tilegx assembler --------- */ - -static UChar *mkInsnBin ( UChar * p, ULong insn ) -{ - vassert(insn != (ULong)(-1)); - if (((Addr)p) & 7) { - vex_printf("p=%p\n", p); - vassert((((Addr)p) & 7) == 0); - } - *((ULong *)(Addr)p) = insn; - p += 8; - return p; -} - -static Int display_insn ( struct tilegx_decoded_instruction - decoded[1] ) -{ - Int i; - for (i = 0; - decoded[i].opcode && (i < 1); - i++) { - Int n; - vex_printf("%s ", decoded[i].opcode->name); - - for (n = 0; n < decoded[i].opcode->num_operands; n++) { - const struct tilegx_operand *op = decoded[i].operands[n]; - - if (op->type == TILEGX_OP_TYPE_REGISTER) - vex_printf("r%d", (Int) decoded[i].operand_values[n]); - else - vex_printf("%llu", (ULong)decoded[i].operand_values[n]); - - if (n != (decoded[i].opcode->num_operands - 1)) - vex_printf(", "); - } - vex_printf(" "); - } - return i; -} - - -Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc ) -{ - struct tilegx_decoded_instruction - decode[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]; - Int i; - -#ifdef TILEGX_DEBUG - vex_printf("Insn@0x%lx\n", (ULong)p); -#endif - - if (count > 0x1000) { - vex_printf("insn count: %d", count); - vassert(0); - } - - for (i = 0 ; i < count ; i++) { - if (pc) { - vex_printf("%012llx %016llx ", pc, (ULong)p[i]); - pc += 8; - } - parse_insn_tilegx(p[i], 0, decode); - - Int n, k, bundled = 0; - - for(k = 0; (k < TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE) && decode[k].opcode; - k++) { - if (decode[k].opcode->mnemonic != TILEGX_OPC_FNOP) - bundled++; - } - - /* Print "{", ";" and "}" only if multiple instructions are bundled. */ - if (bundled > 1) - vex_printf("{ "); - - n = bundled; - for(k = 0; (k < TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE) && decode[k].opcode; - k++) { - if (decode[k].opcode->mnemonic == TILEGX_OPC_FNOP) - continue; - - display_insn(&decode[k]); - - if (--n > 0) - vex_printf("; "); - } - - if (bundled > 1) - vex_printf(" }"); - - vex_printf("\n"); - } - return count; -} - -static UInt iregNo ( HReg r ) -{ - UInt n; - vassert(hregClass(r) == HRcInt64); - vassert(!hregIsVirtual(r)); - n = hregEncoding(r); - vassert(n <= 63); - return n; -} - -static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode * am ) -{ - UInt rA; - vassert(am->tag == GXam_IR); - - rA = iregNo(am->GXam.IR.base); - - if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 || - opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) { - if ( am->GXam.IR.index ) { - /* r51 is reserved scratch registers. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, rA, am->GXam.IR.index)); - /* store rSD to address in r51 */ - p = mkInsnBin(p, mkTileGxInsn(opc1, 2, 51, rSD)); - } else { - /* store rSD to address in rA */ - p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rA, rSD)); - } - } else { - if ( am->GXam.IR.index ) { - /* r51 is reserved scratch registers. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, rA, am->GXam.IR.index)); - /* load from address in r51 to rSD. */ - p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rSD, 51)); - } else { - /* load from address in rA to rSD. */ - p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rSD, rA)); - } - } - return p; -} - -/* Generate a machine-word sized load or store using exact 2 bundles. - Simplified version of the GXin_Load and GXin_Store cases below. */ -static UChar* do_load_or_store_machine_word ( UChar* p, Bool isLoad, UInt reg, - TILEGXAMode* am ) -{ - UInt rA = iregNo(am->GXam.IR.base); - - if (am->tag != GXam_IR) - vpanic(__func__); - - if (isLoad) /* load */ { - /* r51 is reserved scratch registers. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, rA, am->GXam.IR.index)); - /* load from address in r51 to rSD. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, reg, 51)); - } else /* store */ { - /* r51 is reserved scratch registers. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, rA, am->GXam.IR.index)); - /* store rSD to address in r51 */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 51, reg)); - } - return p; -} - -/* Load imm to r_dst */ -static UChar *mkLoadImm ( UChar * p, UInt r_dst, ULong imm ) -{ - vassert(r_dst < 0x40); - - if (imm == 0) - { - /* A special case, use r63 - zero register. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVE, 2, r_dst, 63)); - } - else if (imm >= 0xFFFFFFFFFFFF8000ULL || imm < 0x8000) - { - /* only need one 16-bit sign-extendable movli instructon. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2, - r_dst, imm & 0xFFFF)); - - } - else if (imm >= 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL) - { - /* Sign-extendable moveli and a shl16insli */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2, - r_dst, - (imm >> 16) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - (imm & 0xFFFF))); - - } - else - { - /* A general slower and rare case, use 4 instructions/bundles: - moveli r_dst, imm[63:48] - shl16insli r_dst, imm[47:32] - shl16insli r_dst, imm[31:16] - shl16insli r_dst, imm[15: 0] - */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2, - r_dst, - (imm >> 48) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - (imm >> 32) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - (imm >> 16) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - imm & 0xFFFF)); - } - return p; -} - -/* Load imm to r_dst using exact 4 bundles. A special case of above - mkLoadImm(...). */ -static UChar *mkLoadImm_EXACTLY4 ( UChar * p, UInt r_dst, ULong imm ) -{ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2, - r_dst, - (imm >> 48) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - (imm >> 32) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - (imm >> 16) & 0xFFFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, r_dst, - (imm) & 0xFFFF)); - return p; -} - -/* Move r_dst to r_src */ -static UChar *mkMoveReg ( UChar * p, UInt r_dst, UInt r_src ) -{ - vassert(r_dst < 0x40); - vassert(r_src < 0x40); - - if (r_dst != r_src) { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVE, 2, - r_dst, r_src)); - } - return p; -} - -/* Emit an instruction into buf and return the number of bytes used. - Note that buf is not the insn's final place, and therefore it is - imperative to emit position-independent code. */ -Int emit_TILEGXInstr ( Bool* is_profInc, - UChar* buf, - Int nbuf, - TILEGXInstr* i, - Bool mode64, - VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ) -{ - Int instr_bytes = 0; - UChar *p = &buf[0]; - UChar *ptmp = p; - vassert(nbuf >= 32); - vassert(!((Addr)p & 0x7)); - vassert (mode64); - - switch (i->tag) { - case GXin_MovCond: { - - TILEGXRH *srcR = i->GXin.MovCond.srcR; - UInt condR = iregNo(i->GXin.MovCond.condR); - UInt dst = iregNo(i->GXin.MovCond.dst); - - UInt srcL = iregNo(i->GXin.MovCond.srcL); - - if (i->GXin.MovCond.cond == TILEGXcc_EZ) { - if (srcR->tag == GXrh_Reg) { - p = mkMoveReg(p, dst, iregNo(srcR->GXrh.Reg.reg)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMOVEQZ, 3, - dst, condR, srcL)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MOVELI, 2, - dst, srcR->GXrh.Imm.imm16)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMOVEQZ, 3, - dst, condR, srcL)); - } - } else { - vassert(0); - } - - goto done; - } - case GXin_LI: - - // Tilegx, load literal - p = mkLoadImm(p, iregNo(i->GXin.LI.dst), i->GXin.LI.imm); - goto done; - - case GXin_Alu: { - TILEGXRH *srcR = i->GXin.Alu.srcR; - Bool immR = toBool(srcR->tag == GXrh_Imm); - UInt r_dst = iregNo(i->GXin.Alu.dst); - UInt r_srcL = iregNo(i->GXin.Alu.srcL); - UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->GXrh.Reg.reg); - - switch (i->GXin.Alu.op) { - /*GXalu_ADD, GXalu_SUB, GXalu_AND, GXalu_OR, GXalu_NOR, GXalu_XOR */ - case GXalu_ADD: - if (immR) { - vassert(srcR->GXrh.Imm.imm16 != 0x8000); - if (srcR->GXrh.Imm.syned) - /* addi */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - else - /* addiu, use shil16insli for tilegx */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL16INSLI, 3, - r_dst, 63, - srcR->GXrh.Imm.imm16)); - } else { - /* addu */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADD, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - case GXalu_SUB: - if (immR) { - /* addi , but with negated imm */ - vassert(srcR->GXrh.Imm.syned); - vassert(srcR->GXrh.Imm.imm16 != 0x8000); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - r_dst, r_srcL, - -srcR->GXrh.Imm.imm16)); - } else { - /* subu */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SUB, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - case GXalu_AND: - if (immR) { - /* andi */ - vassert((srcR->GXrh.Imm.imm16 >> 8 == 0) || - (srcR->GXrh.Imm.imm16 >> 8 == 0xFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ANDI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - - } else { - /* and */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_AND, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - case GXalu_OR: - if (immR) { - /* ori */ - vassert((srcR->GXrh.Imm.imm16 >> 8 == 0) || - (srcR->GXrh.Imm.imm16 >> 8 == 0xFF)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ORI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - /* or */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_OR, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - case GXalu_NOR: - /* nor */ - vassert(!immR); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOR, 3, - r_dst, r_srcL, - r_srcR)); - break; - case GXalu_XOR: - if (immR) { - /* xori */ - vassert(srcR->GXrh.Imm.syned); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_XORI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - /* xor */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_XOR, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - - default: - goto bad; - } - goto done; - } - - case GXin_Shft: { - TILEGXRH *srcR = i->GXin.Shft.srcR; - Bool sz32 = i->GXin.Shft.sz32; - Bool immR = toBool(srcR->tag == GXrh_Imm); - UInt r_dst = iregNo(i->GXin.Shft.dst); - UInt r_srcL = iregNo(i->GXin.Shft.srcL); - UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->GXrh.Reg.reg); - - switch (i->GXin.Shft.op) { - case GXshft_SLL: - if (sz32) { - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert(n >= 0 && n < 64); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHLXI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - /* shift variable */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHLX, 3, - r_dst, r_srcL, - r_srcR)); - } - } else { - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert(n >= 0 && n < 64); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHLI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHL, 3, - r_dst, r_srcL, - r_srcR)); - } - } - break; - - case GXshft_SLL8x8: - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert(n >= 0 && n < 64); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHLI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHL, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - - case GXshft_SRL8x8: - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert(n >= 0 && n < 64); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHRUI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1SHRU, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - - case GXshft_SRL: - if (sz32) { - // SRL, SRLV - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert(n >= 0 && n < 32); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRUXI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - /* shift variable */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRUX, 3, - r_dst, r_srcL, - r_srcR)); - } - } else { - // DSRL, DSRL32, DSRLV - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert((n >= 0 && n < 64)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRUI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRU, 3, - r_dst, r_srcL, - r_srcR)); - } - } - break; - - case GXshft_SRA: - if (sz32) { - // SRA, SRAV - if (immR) { - UInt n = srcR->GXrh.Imm.imm16; - vassert(n >= 0 && n < 64); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRSI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - - } else { - /* shift variable */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRS, 3, - r_dst, r_srcL, - r_srcR)); - } - } else { - // DSRA, DSRA32, DSRAV - if (immR) { - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRSI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_SHRS, 3, - r_dst, r_srcL, - r_srcR)); - } - } - break; - - default: - goto bad; - } - - goto done; - } - - case GXin_Unary: { - UInt r_dst = iregNo(i->GXin.Unary.dst); - UInt r_src = iregNo(i->GXin.Unary.src); - - switch (i->GXin.Unary.op) { - /* GXun_CLZ, GXun_NOP */ - case GXun_CLZ: //clz - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CLZ, 2, - r_dst, r_src)); - break; - case GXun_CTZ: //ctz - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CTZ, 2, - r_dst, r_src)); - break; - - case GXun_NOP: - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - break; - } - goto done; - } - - case GXin_Cmp: { - - Bool syned = i->GXin.Cmp.syned; - UInt r_srcL = iregNo(i->GXin.Cmp.srcL); - UInt r_srcR = iregNo(i->GXin.Cmp.srcR); - UInt r_dst = iregNo(i->GXin.Cmp.dst); - - switch (i->GXin.Cmp.cond) { - case TILEGXcc_EQ: - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPEQ, 3, - r_dst, r_srcL, - r_srcR)); - - break; - - case TILEGXcc_NE: - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPNE, 3, - r_dst, r_srcL, - r_srcR)); - - break; - case TILEGXcc_LT: - /* slt r_dst, r_srcL, r_srcR */ - - if (syned) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTS, 3, - r_dst, r_srcL, - r_srcR)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTU, 3, - r_dst, r_srcL, - r_srcR)); - - break; - case TILEGXcc_LO: - /* sltu r_dst, r_srcL, r_srcR */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTU, 3, - r_dst, r_srcL, - r_srcR)); - - break; - case TILEGXcc_LE: - if (syned) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLES, 3, - r_dst, r_srcL, - r_srcR)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLEU, 3, - r_dst, r_srcL, - r_srcR)); - break; - case TILEGXcc_LS: - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPLTU, 3, - r_dst, r_srcL, - r_srcR)); - break; - default: - goto bad; - } - goto done; - } - - case GXin_CmpI: { - - TILEGXRH *srcR = i->GXin.CmpI.srcR; - Bool immR = toBool(srcR->tag == GXrh_Imm); - UInt r_dst = iregNo(i->GXin.CmpI.dst); - UInt r_srcL = iregNo(i->GXin.CmpI.srcL); - UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->GXrh.Reg.reg); - - switch (i->GXin.CmpI.cond) { - case TILEGXcc_EQ8x8: - if (immR) { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1CMPEQI, 3, - r_dst, r_srcL, - srcR->GXrh.Imm.imm16)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1CMPEQ, 3, - r_dst, r_srcL, - r_srcR)); - } - break; - - case TILEGXcc_NE8x8: - if (immR) { - vassert(0); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_V1CMPNE, 3, - r_dst, r_srcR, - r_srcL)); - } - break; - default: - vassert(0); - } - goto done; - break; - } - - case GXin_Bf: { - - /* Bit Field */ - UInt r_dst = iregNo(i->GXin.Bf.dst); - UInt r_src = iregNo(i->GXin.Bf.src); - UInt Start = i->GXin.Bf.Start; - UInt End = i->GXin.Bf.End; - - switch (i->GXin.Bf.op) { - case GXbf_EXTS: - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_BFEXTS, 4, - r_dst, r_src, - Start, End)); - - break; - case GXbf_EXTU: - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_BFEXTU, 4, - r_dst, r_src, - Start, End)); - - break; - case GXbf_INS: - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_BFINS, 4, - r_dst, r_src, - Start, End)); - - break; - default: - vassert(0); - } - goto done; - break; - } - - case GXin_Acas: { - - /* Atomic */ - UInt sz = i->GXin.Acas.sz; - UInt old = iregNo(i->GXin.Acas.old); - UInt addr= iregNo(i->GXin.Acas.addr); - UInt new = iregNo(i->GXin.Acas.new); - - switch (i->GXin.Acas.op) { - case GXacas_CMPEXCH: - { - UInt exp = iregNo(i->GXin.Acas.exp); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MTSPR, 2, - 0x2780, exp)); - if (sz == 8) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPEXCH, 3, - old, addr, new)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_CMPEXCH4, 3, - old, addr, new)); - } - break; - - case GXacas_EXCH: - if (sz == 8) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_EXCH, 3, - old, addr, new)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_EXCH4, 3, - old, addr, new)); - break; - - case GXacas_FetchAnd: - if (sz == 8) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHAND, 3, - old, addr, new)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHAND4, 3, - old, addr, new)); - break; - - case GXacas_FetchAdd: - if (sz == 8) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADD, 3, - old, addr, new)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADD4, 3, - old, addr, new)); - break; - - case GXacas_FetchAddgez: - if (sz == 8) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADDGEZ, 3, - old, addr, new)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHADDGEZ4, 3, - old, addr, new)); - break; - - case GXacas_FetchOr: - if (sz == 8) - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHOR, 3, - old, addr, new)); - else - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_FETCHOR4, 3, - old, addr, new)); - break; - - default: vassert(0); - } - goto done; - break; - } - - case GXin_Mul: { - - /* Multiplication */ - Bool syned = i->GXin.Mul.syned; - Bool widening = i->GXin.Mul.widening; - Bool sz32 = i->GXin.Mul.sz32; - UInt r_srcL = iregNo(i->GXin.Mul.srcL); - UInt r_srcR = iregNo(i->GXin.Mul.srcR); - UInt r_dst = iregNo(i->GXin.Mul.dst); - - vassert(widening); // always widen. - vassert(!sz32); // always be 64 bits. - - if (syned) { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MUL_LS_LS, 3, - r_dst, r_srcL, r_srcR)); - } else { - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MUL_LU_LU, 3, - r_dst, r_srcL, r_srcR)); - } - goto done; - } - - case GXin_Call: { - - /* Function Call. */ - TILEGXCondCode cond = i->GXin.Call.cond; - UInt r_dst = 11; /* using r11 as address temporary */ - - /* jump over the following insns if conditional. */ - if (cond != TILEGXcc_AL) { - /* jmp fwds if !condition */ - /* don't know how many bytes to jump over yet... - make space for a jump instruction + nop!!! and fill in later. */ - ptmp = p; /* fill in this bit later */ - p += 8; - } - - /* load target to r_dst */ - p = mkLoadImm(p, r_dst, i->GXin.Call.target); - - /* jalr %r_dst */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALRP, 1, - r_dst)); - - /* Fix up the conditional jump, if there was one. */ - if (cond != TILEGXcc_AL) { - UInt r_src = iregNo(i->GXin.Call.src); - Int delta = p - ptmp; - - vassert(cond == TILEGXcc_EQ); - - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2, - r_src, delta / 8)); - } - goto done; - } - - case GXin_XDirect: { - /* NB: what goes on here has to be very closely coordinated - with the chainXDirect_TILEGX and unchainXDirect_TILEGX below. */ - /* We're generating chain-me requests here, so we need to be - sure this is actually allowed -- no-redir translations - can't use chain-me's. Hence: */ - vassert(disp_cp_chain_me_to_slowEP != NULL); - vassert(disp_cp_chain_me_to_fastEP != NULL); - - /* Use ptmp for backpatching conditional jumps. */ - ptmp = NULL; - - /* First, if this is conditional, create a conditional - jump over the rest of it. Or at least, leave a space for - it that we will shortly fill in. */ - if (i->GXin.XDirect.cond != TILEGXcc_AL) { - vassert(i->GXin.XDirect.cond != TILEGXcc_NV); - ptmp = p; - p += 24; - } - - /* Update the guest PC. */ - /* move r11, dstGA */ - /* st amPC, r11 */ - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, (ULong)i->GXin.XDirect.dstGA); - - p = do_load_or_store_machine_word(p, False /*!isLoad*/ , /*r*/ 11, - i->GXin.XDirect.amPC); - - /* --- FIRST PATCHABLE BYTE follows --- */ - /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're - calling to) backs up the return address, so as to find the - address of the first patchable byte. So: don't change the - number of instructions (3) below. */ - /* move r9, VG_(disp_cp_chain_me_to_{slowEP,fastEP}) */ - /* jr r11 */ - void* disp_cp_chain_me - = i->GXin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP - : disp_cp_chain_me_to_slowEP; - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, - (Addr)disp_cp_chain_me); - /* jalr r11 */ - /* nop */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - - /* --- END of PATCHABLE BYTES --- */ - - /* Fix up the conditional jump, if there was one. */ - if (i->GXin.XDirect.cond != TILEGXcc_AL) { - Int delta = p - ptmp; - delta = delta / 8 - 3; - - /* ld r11, COND_OFFSET(GuestSP=r50) - beqz r11, delta - */ - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 11, 50, COND_OFFSET())); - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_LD, 2, - 11, 11)); - - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2, - 11, delta)); - - } - goto done; - } - - case GXin_XIndir: { - /* We're generating transfers that could lead indirectly to a - chain-me, so we need to be sure this is actually allowed -- - no-redir translations are not allowed to reach normal - translations without going through the scheduler. That means - no XDirects or XIndirs out from no-redir translations. - Hence: */ - vassert(disp_cp_xindir != NULL); - - /* Use ptmp for backpatching conditional jumps. */ - ptmp = NULL; - - /* First off, if this is conditional, create a conditional - jump over the rest of it. */ - if (i->GXin.XIndir.cond != TILEGXcc_AL) { - vassert(i->GXin.XIndir.cond != TILEGXcc_NV); - ptmp = p; - p += 24; - } - - /* Update the guest PC. */ - /* st amPC, dstGA */ - p = do_load_or_store_machine_word(p, False /*!isLoad*/ , - iregNo(i->GXin.XIndir.dstGA), - i->GXin.XIndir.amPC); - - /* move r11, VG_(disp_cp_xindir), 4 bundles. */ - /* jalr r11 */ - /* nop */ - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, - (Addr)disp_cp_xindir); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - - /* Fix up the conditional jump, if there was one. */ - if (i->GXin.XIndir.cond != TILEGXcc_AL) { - Int delta = p - ptmp; - delta = delta / 8 - 3; - vassert(delta > 0 && delta < 40); - - /* ld r11, COND_OFFSET($GuestSP) - beqz r11, delta */ - - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 11, 50, COND_OFFSET())); - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_LD, 2, - 11, 11)); - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2, - 11, delta)); - } - goto done; - } - - case GXin_XAssisted: { - /* First off, if this is conditional, create a conditional jump - over the rest of it. Or at least, leave a space for it that - we will shortly fill in. */ - ptmp = NULL; - if (i->GXin.XAssisted.cond != TILEGXcc_AL) { - vassert(i->GXin.XAssisted.cond != TILEGXcc_NV); - ptmp = p; - p += 24; - } - - /* Update the guest PC. */ - /* st amPC, dstGA */ - p = do_load_or_store_machine_word(p, False /*!isLoad*/ , - iregNo(i->GXin.XIndir.dstGA), - i->GXin.XIndir.amPC); - - UInt trcval = 0; - switch (i->GXin.XAssisted.jk) { - case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break; - case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break; - case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; - case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; - case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break; - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; - case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; - case Ijk_SigILL: trcval = VEX_TRC_JMP_SIGILL; break; - case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break; - case Ijk_SigFPE_IntDiv: trcval = VEX_TRC_JMP_SIGFPE_INTDIV; break; - case Ijk_SigFPE_IntOvf: trcval = VEX_TRC_JMP_SIGFPE_INTOVF; break; - case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; - case Ijk_Ret: - { - /* Tilegx "iret" instruction. */ - trcval = VEX_TRC_JMP_BORING; - /* Interrupt return "iret", setup the jump address into EX_CONTRXT_0_0. - Read context_0_1 from guest_state */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, 50, OFFSET_EX1)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, - 11, 51)); - /* Write into host cpu's context_0_1 spr. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MTSPR, 2, - 0x2581, 11)); - /* Read context_0_0 from guest_state */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, 50, OFFSET_EX0)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, - 11, 51)); - /* Write into host cpu's context_0_0 spr */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_MTSPR, 2, - 0x2580, 11)); - /* Update the guest PC so branch to the iret target address - in EX_CONTEXT_0. */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 51, 50, 512)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, - 51, 11)); - } - break; - /* We don't expect to see the following being assisted. - case Ijk_Call: - fallthrough */ - default: - ppIRJumpKind(i->GXin.XAssisted.jk); - vpanic("emit_TILEGXInstr.GXin_XAssisted: unexpected jump kind"); - } - vassert(trcval != 0); - - /* moveli r50, trcval */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, 50, 63, trcval)); - - /* move r11, VG_(disp_cp_xassisted) */ - - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, - (Addr)disp_cp_xassisted); - /* jalr r11 - nop */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11)); - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - - /* Fix up the conditional jump, if there was one. */ - if (i->GXin.XAssisted.cond != TILEGXcc_AL) { - Int delta = p - ptmp; - delta = delta / 8 - 3; - vassert(delta > 0 && delta < 40); - - /* ld r11, COND_OFFSET($GuestSP) - beqz r11, delta - nop */ - - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_ADDLI, 3, - 11, 50, COND_OFFSET())); - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_LD, 2, - 11, 11)); - ptmp = mkInsnBin(ptmp, mkTileGxInsn(TILEGX_OPC_BEQZ, 2, - 11, delta)); - } - goto done; - } - - case GXin_EvCheck: { - /* We generate: - ld r11, amCounter - addi r11, r11, -1 - st amCounter, r11 - bgez r11, nofail - ld r11, amFailAddr - jalr r11 - nop - nofail: - */ - UChar* p0 = p; - /* ld r11, amCounter */ - p = do_load_or_store_machine_word(p, True /*isLoad*/ , /*r*/ 11, - i->GXin.EvCheck.amCounter); - - /* addi r11,r11,-1 */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDI, 3, - 11, 11, -1)); - - /* st amCounter, 11 */ - p = do_load_or_store_machine_word(p, False /*!isLoad*/ , /*r*/ 11, - i->GXin.EvCheck.amCounter); - - /* Reserve a bundle, fill it after the do_load_or_store_machine_word. - since we are not sure how many bundles it takes. */ - UChar* p1 = p; - p += 8; - /* bgez t9, nofail */ - - /* lw/ld r9, amFailAddr */ - p = do_load_or_store_machine_word(p, True /*isLoad*/ , /*r*/ 11, - i->GXin.EvCheck.amFailAddr); - - mkInsnBin(p1, mkTileGxInsn(TILEGX_OPC_BGEZ, 2, - 11, 2 + (p - p1) / 8)); - - /* jalr r11 */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11)); - - /* nop */ - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - - /* nofail: */ - - /* Crosscheck */ - vassert(evCheckSzB_TILEGX() == (UChar*)p - (UChar*)p0); - goto done; - } - - case GXin_ProfInc: { - /* Generate a code template to increment a memory location whose - address will be known later as an immediate value. This code - template will be patched once the memory location is known. - For now we do this with address == 0x65556555. */ - /* 64-bit: - move r11, 0x6555655565556555ULL - ld r51, r11 - addi r51, r51, 1 - st r11, r51 - */ - - /* move r11, 0x6555655565556555ULL */ - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, 0x6555655565556555ULL); - - /* ld r51, r11 */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, 51, 11)); - - /* addi r51, r51, 1 */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDI, 3, 51, 51, 1)); - - /* st r11, r51 */ - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 11, 51)); - - /* Tell the caller .. */ - vassert(!(*is_profInc)); - *is_profInc = True; - goto done; - } - - case GXin_Load: { - TILEGXAMode *am_addr = i->GXin.Load.src; - if (am_addr->tag == GXam_IR) { - UInt r_dst = iregNo(i->GXin.Load.dst); - UInt opc, sz = i->GXin.Load.sz; - if ((sz == 4 || sz == 8)) { - /* should be guaranteed to us by iselWordExpr_AMode */ - vassert(0 == (am_addr->GXam.IR.index & 3)); - } - - // Note: Valgrind memory load has no sign-extend. We extend explicitly. - switch (sz) { - case 1: - opc = TILEGX_OPC_LD1U; - break; - case 2: - opc = TILEGX_OPC_LD2U; - break; - case 4: - opc = TILEGX_OPC_LD4U; - break; - case 8: - opc = TILEGX_OPC_LD; - break; - default: - goto bad; - } - - p = doAMode_IR(p, opc, r_dst, am_addr); - goto done; - - } - } - - case GXin_Store: { - TILEGXAMode *am_addr = i->GXin.Store.dst; - if (am_addr->tag == GXam_IR) { - UInt r_src = iregNo(i->GXin.Store.src); - UInt opc, sz = i->GXin.Store.sz; - switch (sz) { - case 1: - opc = TILEGX_OPC_ST1; - break; - case 2: - opc = TILEGX_OPC_ST2; - break; - case 4: - opc = TILEGX_OPC_ST4; - break; - case 8: - opc = TILEGX_OPC_ST; - break; - default: - goto bad; - } - - p = doAMode_IR(p, opc, r_src, am_addr); - goto done; - } else { - vassert(0); - } - } - - case GXin_RdWrLR: { - UInt reg = iregNo(i->GXin.RdWrLR.gpr); - Bool wrLR = i->GXin.RdWrLR.wrLR; - if (wrLR) - p = mkMoveReg(p, 55, reg); - else - p = mkMoveReg(p, reg, 55); - goto done; - } - - default: - goto bad; - } - - bad: - vex_printf("\n=> "); - vpanic("emit_TILEGXInstr"); - /*NOTREACHED*/ - - done: - instr_bytes = p - &buf[0]; - /* Instr byte count must be modular of 8. */ - vassert(0 == (instr_bytes & 0x7)); - - if ( 0) { - Int k; - for (k = 0; k < instr_bytes; k += 8) - decode_and_display((ULong *)(Addr)&buf[k], 1, 0); - } - - /* Limit the JIT size. */ - vassert(instr_bytes <= 256); - return instr_bytes; -} - - -Int evCheckSzB_TILEGX ( void ) -{ - UInt kInstrSize = 8; - return 10*kInstrSize; -} - -VexInvalRange chainXDirect_TILEGX ( VexEndness endness_host, - void* place_to_chain, - const void* disp_cp_chain_me_EXPECTED, - const void* place_to_jump_to, - Bool mode64 ) -{ - vassert(mode64); - vassert(endness_host == VexEndnessLE); - /* What we're expecting to see is: - move r11, disp_cp_chain_me_to_EXPECTED - jalr r11 - nop - viz - <32 bytes generated by mkLoadImm_EXACTLY4> - jalr r11 - nop - */ - UChar* p = (UChar*)place_to_chain; - vassert(0 == (7 & (HWord)p)); - -#ifdef TILEGX_DEBUG - vex_printf("chainXDirect_TILEGX: disp_cp_chain_me_EXPECTED=%p\n", - disp_cp_chain_me_EXPECTED); - decode_and_display(p, 6, p); - - vex_printf("chainXDirect_TILEGX: place_to_jump_to=%p\n", - place_to_jump_to); -#endif - - /* And what we want to change it to is either: - move r11, place_to_jump_to - jalr r11 - nop - viz - <32 bytes generated by mkLoadImm_EXACTLY4> - jalr r11 - nop - - The replacement has the same length as the original. - */ - - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, - (Addr)place_to_jump_to); - - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - -#ifdef TILEGX_DEBUG - decode_and_display((UChar*)place_to_chain, 8, place_to_chain); -#endif - - Int len = p - (UChar*)place_to_chain; - vassert(len == 48); /* stay sane */ - VexInvalRange vir = {(HWord)place_to_chain, len}; - return vir; -} - -VexInvalRange unchainXDirect_TILEGX ( VexEndness endness_host, - void* place_to_unchain, - const void* place_to_jump_to_EXPECTED, - const void* disp_cp_chain_me, - Bool mode64 ) -{ - vassert(mode64); - vassert(endness_host == VexEndnessLE); - /* What we're expecting to see is: - move r11, place_to_jump_to_EXPECTED - jalr r11 - nop - viz - <32 bytes generated by mkLoadImm_EXACTLY4> - jalr r11 - nop - */ - UChar* p = (UChar*)place_to_unchain; - vassert(0 == (7 & (HWord)p)); - - /* And what we want to change it to is: - move r11, disp_cp_chain_me - jalr r11 - nop - viz - <32 bytes generated by mkLoadImm_EXACTLY4> - jalr r11 - nop - The replacement has the same length as the original. - */ - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, - (Addr)disp_cp_chain_me); - - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_JALR, 1, 11)); - - p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_NOP, 0)); - - Int len = p - (UChar*)place_to_unchain; - vassert(len == 48); /* stay sane */ - VexInvalRange vir = {(HWord)place_to_unchain, len}; - return vir; -} - -/* Patch the counter address into a profile inc point, as previously - created by the GXin_ProfInc case for emit_TILEGXInstr. */ -VexInvalRange patchProfInc_TILEGX ( VexEndness endness_host, - void* place_to_patch, - const ULong* location_of_counter, - Bool mode64 ) -{ - vassert(mode64); - vassert(endness_host == VexEndnessLE); - UChar* p = (UChar*)place_to_patch; - vassert(0 == (7 & (HWord)p)); - - p = mkLoadImm_EXACTLY4(p, /*r*/ 11, - (Addr)location_of_counter); - - VexInvalRange vir = {(HWord)p, 32}; - return vir; -} - -/*---------------------------------------------------------------*/ -/*--- end host_tilegx_defs.c ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/priv/host_tilegx_defs.h b/VEX/priv/host_tilegx_defs.h deleted file mode 100644 index 2c0d64e84d..0000000000 --- a/VEX/priv/host_tilegx_defs.h +++ /dev/null @@ -1,562 +0,0 @@ - -/*---------------------------------------------------------------*/ -/*--- begin host_tilegx_defs.h ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2010-2017 Tilera Corp. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - - /* Contributed by Zhi-Gang Liu */ - -#ifndef __VEX_HOST_TILEGX_DEFS_H -#define __VEX_HOST_TILEGX_DEFS_H - -#include "tilegx_disasm.h" - -/* Num registers used for function calls */ -#define TILEGX_N_REGPARMS 10 - -/* --------- Registers. --------- */ - -/* The usual HReg abstraction. - There are 56 general purpose regs. -*/ - -#define ST_IN static inline - -ST_IN HReg hregTILEGX_R30 ( void ) { return mkHReg(False, HRcInt64, 30, 0); } -ST_IN HReg hregTILEGX_R31 ( void ) { return mkHReg(False, HRcInt64, 31, 1); } -ST_IN HReg hregTILEGX_R32 ( void ) { return mkHReg(False, HRcInt64, 32, 2); } -ST_IN HReg hregTILEGX_R33 ( void ) { return mkHReg(False, HRcInt64, 33, 3); } -ST_IN HReg hregTILEGX_R34 ( void ) { return mkHReg(False, HRcInt64, 34, 4); } -ST_IN HReg hregTILEGX_R35 ( void ) { return mkHReg(False, HRcInt64, 35, 5); } -ST_IN HReg hregTILEGX_R36 ( void ) { return mkHReg(False, HRcInt64, 36, 6); } -ST_IN HReg hregTILEGX_R37 ( void ) { return mkHReg(False, HRcInt64, 37, 7); } -ST_IN HReg hregTILEGX_R38 ( void ) { return mkHReg(False, HRcInt64, 38, 8); } -ST_IN HReg hregTILEGX_R39 ( void ) { return mkHReg(False, HRcInt64, 39, 9); } - -ST_IN HReg hregTILEGX_R40 ( void ) { return mkHReg(False, HRcInt64, 40, 10); } -ST_IN HReg hregTILEGX_R41 ( void ) { return mkHReg(False, HRcInt64, 41, 11); } -ST_IN HReg hregTILEGX_R42 ( void ) { return mkHReg(False, HRcInt64, 42, 12); } -ST_IN HReg hregTILEGX_R43 ( void ) { return mkHReg(False, HRcInt64, 43, 13); } -ST_IN HReg hregTILEGX_R44 ( void ) { return mkHReg(False, HRcInt64, 44, 14); } -ST_IN HReg hregTILEGX_R45 ( void ) { return mkHReg(False, HRcInt64, 45, 15); } -ST_IN HReg hregTILEGX_R46 ( void ) { return mkHReg(False, HRcInt64, 46, 16); } -ST_IN HReg hregTILEGX_R47 ( void ) { return mkHReg(False, HRcInt64, 47, 17); } -ST_IN HReg hregTILEGX_R48 ( void ) { return mkHReg(False, HRcInt64, 48, 18); } -ST_IN HReg hregTILEGX_R49 ( void ) { return mkHReg(False, HRcInt64, 49, 19); } - -ST_IN HReg hregTILEGX_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 20); } -ST_IN HReg hregTILEGX_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 21); } -ST_IN HReg hregTILEGX_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 22); } -ST_IN HReg hregTILEGX_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 23); } -ST_IN HReg hregTILEGX_R16 ( void ) { return mkHReg(False, HRcInt64, 16, 24); } -ST_IN HReg hregTILEGX_R17 ( void ) { return mkHReg(False, HRcInt64, 17, 25); } -ST_IN HReg hregTILEGX_R18 ( void ) { return mkHReg(False, HRcInt64, 18, 26); } -ST_IN HReg hregTILEGX_R19 ( void ) { return mkHReg(False, HRcInt64, 19, 27); } -ST_IN HReg hregTILEGX_R20 ( void ) { return mkHReg(False, HRcInt64, 20, 28); } - -ST_IN HReg hregTILEGX_R21 ( void ) { return mkHReg(False, HRcInt64, 21, 29); } -ST_IN HReg hregTILEGX_R22 ( void ) { return mkHReg(False, HRcInt64, 22, 30); } -ST_IN HReg hregTILEGX_R23 ( void ) { return mkHReg(False, HRcInt64, 23, 31); } -ST_IN HReg hregTILEGX_R24 ( void ) { return mkHReg(False, HRcInt64, 24, 32); } -ST_IN HReg hregTILEGX_R25 ( void ) { return mkHReg(False, HRcInt64, 25, 33); } -ST_IN HReg hregTILEGX_R26 ( void ) { return mkHReg(False, HRcInt64, 26, 34); } -ST_IN HReg hregTILEGX_R27 ( void ) { return mkHReg(False, HRcInt64, 27, 35); } -ST_IN HReg hregTILEGX_R28 ( void ) { return mkHReg(False, HRcInt64, 28, 36); } -ST_IN HReg hregTILEGX_R29 ( void ) { return mkHReg(False, HRcInt64, 29, 37); } - -ST_IN HReg hregTILEGX_R0 ( void ) { return mkHReg(False, HRcInt64, 0, 38); } -ST_IN HReg hregTILEGX_R1 ( void ) { return mkHReg(False, HRcInt64, 1, 39); } -ST_IN HReg hregTILEGX_R2 ( void ) { return mkHReg(False, HRcInt64, 2, 40); } -ST_IN HReg hregTILEGX_R3 ( void ) { return mkHReg(False, HRcInt64, 3, 41); } -ST_IN HReg hregTILEGX_R4 ( void ) { return mkHReg(False, HRcInt64, 4, 42); } -ST_IN HReg hregTILEGX_R5 ( void ) { return mkHReg(False, HRcInt64, 5, 43); } -ST_IN HReg hregTILEGX_R6 ( void ) { return mkHReg(False, HRcInt64, 6, 44); } -ST_IN HReg hregTILEGX_R7 ( void ) { return mkHReg(False, HRcInt64, 7, 45); } -ST_IN HReg hregTILEGX_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 46); } -ST_IN HReg hregTILEGX_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 47); } - -ST_IN HReg hregTILEGX_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 48); } -ST_IN HReg hregTILEGX_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 49); } -ST_IN HReg hregTILEGX_R50 ( void ) { return mkHReg(False, HRcInt64, 50, 50); } -ST_IN HReg hregTILEGX_R51 ( void ) { return mkHReg(False, HRcInt64, 51, 51); } -ST_IN HReg hregTILEGX_R52 ( void ) { return mkHReg(False, HRcInt64, 52, 52); } -ST_IN HReg hregTILEGX_R53 ( void ) { return mkHReg(False, HRcInt64, 53, 53); } -ST_IN HReg hregTILEGX_R54 ( void ) { return mkHReg(False, HRcInt64, 54, 54); } -ST_IN HReg hregTILEGX_R55 ( void ) { return mkHReg(False, HRcInt64, 55, 55); } -ST_IN HReg hregTILEGX_R63 ( void ) { return mkHReg(False, HRcInt64, 63, 56); } - -extern void ppHRegTILEGX ( HReg ); - -#define TILEGXGuestStatePointer() hregTILEGX_R50() -#define TILEGXStackFramePointer() hregTILEGX_R52() -#define TILEGXLinkRegister() hregTILEGX_R55() -#define TILEGXStackPointer() hregTILEGX_R54() - -/* r0, r1, r2, r3 ... r9 */ -#define TILEGX_N_ARGREGS 10 - -/* --------- Condition codes, Tilegx encoding. --------- */ -typedef enum { - TILEGXcc_EQ = 0, /* equal */ - TILEGXcc_NE = 1, /* not equal */ - TILEGXcc_HS = 2, /* >=u (higher or same) */ - TILEGXcc_LO = 3, /* u (higher) */ - TILEGXcc_LS = 9, /* <=u (lower or same) */ - TILEGXcc_GE = 10, /* >=s (signed greater or equal) */ - TILEGXcc_LT = 11, /* s (signed greater) */ - TILEGXcc_LE = 13, /* <=s (signed less or equal) */ - TILEGXcc_AL = 14, /* always (unconditional) */ - TILEGXcc_NV = 15, /* never (unconditional): */ - TILEGXcc_EQ8x8 = 16,/* V1 equal */ - TILEGXcc_NE8x8 = 17,/* V1 not equal */ - TILEGXcc_EZ = 18, /* equal 0 */ - TILEGXcc_NZ = 19, /* not equal */ - -} TILEGXCondCode; - -/* --------- Memory address expressions (amodes). --------- */ -typedef enum { - GXam_IR, /* Immediate (signed 16-bit) + Reg */ -} TILEGXAModeTag; - -typedef struct { - TILEGXAModeTag tag; - union { - struct { - HReg base; - Int index; - } IR; - struct { - HReg base; - HReg index; - } RR; - } GXam; -} TILEGXAMode; - -extern TILEGXAMode *TILEGXAMode_IR ( Int, HReg ); -extern TILEGXAMode *TILEGXAMode_RR ( HReg, HReg ); -extern TILEGXAMode *dopyTILEGXAMode ( TILEGXAMode * ); -extern TILEGXAMode *nextTILEGXAModeFloat ( TILEGXAMode * ); -extern TILEGXAMode *nextTILEGXAModeInt ( TILEGXAMode * ); -extern void ppTILEGXAMode ( const TILEGXAMode * ); - -/* --------- Operand, which can be a reg or a u16/s16. --------- */ -/* ("RH" == "Register or Halfword immediate") */ -typedef enum { - GXrh_Imm, - GXrh_Reg -} TILEGXRHTag; - -typedef struct { - TILEGXRHTag tag; - union { - struct { - Bool syned; - UShort imm16; - } Imm; - struct { - HReg reg; - } Reg; - } GXrh; -} TILEGXRH; - -extern void ppTILEGXRH ( const TILEGXRH * ); -extern TILEGXRH *TILEGXRH_Imm ( Bool, UShort ); -extern TILEGXRH *TILEGXRH_Reg ( HReg ); - -/* --------- Reg or imm5 operands --------- */ -typedef enum { - TILEGXri5_I5 = 7, /* imm5, 1 .. 31 only (no zero!) */ - TILEGXri5_R /* reg */ -} TILEGXRI5Tag; - -typedef struct { - TILEGXRI5Tag tag; - union { - struct { - UInt imm5; - } I5; - struct { - HReg reg; - } R; - } TILEGXri5; -} TILEGXRI5; - -extern TILEGXRI5 *TILEGXRI5_I5 ( UInt imm5 ); -extern TILEGXRI5 *TILEGXRI5_R ( HReg ); - -extern void ppTILEGXRI5 ( const TILEGXRI5 * ); - -/* --------- Instructions. --------- */ - -/*Tags for operations*/ - -/* --------- */ -typedef enum { - GXun_CLZ, - GXun_CTZ, - GXun_NOP, -} TILEGXUnaryOp; - -/* --------- */ - -typedef enum { - GXalu_INVALID, - GXalu_ADD, - GXalu_SUB, - GXalu_AND, - GXalu_OR, - GXalu_NOR, - GXalu_XOR, -} TILEGXAluOp; - -/* --------- */ - -typedef enum { - GXshft_INVALID, - GXshft_SLL, - GXshft_SRL, - GXshft_SRA, - GXshft_SLL8x8, - GXshft_SRL8x8, - -} TILEGXShftOp; - - -/* --------- */ -typedef enum { - GXbf_EXTS, - GXbf_EXTU, - GXbf_INS -} TILEGXBfOp; - -/* --------- */ - - -/* --------- */ -typedef enum { - GXacas_CMPEXCH, - GXacas_EXCH, - GXacas_FetchAnd, - GXacas_FetchAdd, - GXacas_FetchAddgez, - GXacas_FetchOr, -} TILEGXAcasOp; - -/* --------- */ - -/* ----- Instruction tags ----- */ -typedef enum { - GXin_LI, /* load word (32/64-bit) immediate (fake insn) */ - GXin_Alu, /* word add/sub/and/or/xor/nor/others? */ - GXin_Shft, /* word sll/srl/sra */ - GXin_Unary, /* clo, clz, nop, neg */ - - GXin_Cmp, /* word compare (fake insn) */ - GXin_CmpI, - - GXin_Mul, /* widening/non-widening multiply */ - - GXin_Call, /* call to address in register */ - - GXin_XDirect, /* direct transfer to GA */ - GXin_XIndir, /* indirect transfer to GA */ - GXin_XAssisted, /* assisted transfer to GA */ - GXin_EvCheck, /* Event check */ - GXin_ProfInc, /* 64-bit profile counter increment */ - - GXin_RdWrLR, /* Read/Write Link Register */ - - GXin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ - GXin_Store, /* store a 8|16|32|64 bit value to mem */ - - GXin_MovCond, - GXin_Bf, /* Bitfield operations */ - GXin_Acas, /* Atomic Campare and swap. */ - -} TILEGXInstrTag; - -/*--------- Structure for instructions ----------*/ -/* Destinations are on the LEFT (first operand) */ - -typedef struct { - TILEGXInstrTag tag; - union { - /* Get a 32/64-bit literal into a register. - May turn into a number of real insns. */ - struct { - HReg dst; - ULong imm; - } LI; - /* Integer add/sub/and/or/xor. Limitations: - - For add, the immediate, if it exists, is a signed 16. - - For sub, the immediate, if it exists, is a signed 16 - which may not be -32768, since no such instruction - exists, and so we have to emit addi with +32768, but - that is not possible. - - For and/or/xor, the immediate, if it exists, - is an unsigned 16. - */ - struct { - TILEGXAluOp op; - HReg dst; - HReg srcL; - TILEGXRH *srcR; - } Alu; - - struct { - TILEGXBfOp op; - HReg dst; - HReg src; - UInt Start; - UInt End; - } Bf; - - struct { - TILEGXAcasOp op; - HReg addr; - HReg exp; - HReg new; - HReg old; - UInt sz; - } Acas; - - /* Integer shl/shr/sar. - Limitations: the immediate, if it exists, - is a signed 5-bit value between 1 and 31 inclusive. - */ - struct { - TILEGXShftOp op; - Bool sz32; - HReg dst; - HReg srcL; - TILEGXRH *srcR; - } Shft; - /* Clz, Ctz, Clo, nop */ - struct { - TILEGXUnaryOp op; - HReg dst; - HReg src; - } Unary; - /* Word compare. Fake instruction, used for basic block ending */ - struct { - Bool syned; - Bool sz32; - HReg dst; - HReg srcL; - HReg srcR; - TILEGXCondCode cond; - } Cmp; - struct { - Bool syned; - Bool sz32; - HReg dst; - HReg srcL; - TILEGXRH *srcR; - TILEGXCondCode cond; - } CmpI; - struct { - Bool widening; //True => widening, False => non-widening - Bool syned; //signed/unsigned - meaningless if widenind = False - Bool sz32; - HReg dst; - HReg srcL; - HReg srcR; - } Mul; - /* Pseudo-insn. Call target (an absolute address), on given - condition (which could be Mcc_ALWAYS). argiregs indicates - which of r0 .. r9 - carries argument values for this call, - using a bit mask (1< */ - -#include "libvex_basictypes.h" -#include "libvex_ir.h" -#include "libvex.h" - -#include "main_util.h" -#include "main_globals.h" -#include "host_generic_regs.h" -#include "host_tilegx_defs.h" -#include "tilegx_disasm.h" - -/*---------------------------------------------------------*/ -/*--- Register Usage Conventions ---*/ -/*---------------------------------------------------------*/ - -/* GPR register class for tilegx */ -#define HRcGPR() HRcInt64 - -/* guest_COND offset. */ -#define COND_OFFSET() (608) - -/*---------------------------------------------------------*/ -/*--- ISelEnv ---*/ -/*---------------------------------------------------------*/ - -/* This carries around: - - - A mapping from IRTemp to IRType, giving the type of any IRTemp we - might encounter. This is computed before insn selection starts, - and does not change. - - - A mapping from IRTemp to HReg. This tells the insn selector - which virtual register(s) are associated with each IRTemp - temporary. This is computed before insn selection starts, and - does not change. We expect this mapping to map precisely the - same set of IRTemps as the type mapping does. - - - vregmap holds the primary register for the IRTemp. - - vregmapHI holds the secondary register for the IRTemp, - if any is needed. That's only for Ity_I64 temps - in 32 bit mode or Ity_I128 temps in 64-bit mode. - - - The name of the vreg in which we stash a copy of the link reg, - so helper functions don't kill it. - - - The code array, that is, the insns selected so far. - - - A counter, for generating new virtual registers. - - - The host subarchitecture we are selecting insns for. - This is set at the start and does not change. - - - A Bool to tell us if the host is 32 or 64bit. - This is set at the start and does not change. - - - An IRExpr*, which may be NULL, holding the IR expression (an - IRRoundingMode-encoded value) to which the FPU's rounding mode - was most recently set. Setting to NULL is always safe. Used to - avoid redundant settings of the FPU's rounding mode, as - described in set_FPU_rounding_mode below. - - - A VexMiscInfo*, needed for knowing how to generate - function calls for this target -*/ -typedef struct { - IRTypeEnv *type_env; - - HReg *vregmap; - - Int n_vregmap; - - HInstrArray *code; - - Int vreg_ctr; - - UInt hwcaps; - - Bool mode64; - - Bool chainingAllowed; - - Addr64 max_ga; - - IRExpr *previous_rm; - - VexAbiInfo *vbi; -} ISelEnv; - -static HReg lookupIRTemp ( ISelEnv * env, IRTemp tmp ) -{ - vassert(tmp >= 0); - vassert(tmp < env->n_vregmap); - return env->vregmap[tmp]; -} - -static void addInstr ( ISelEnv * env, TILEGXInstr * instr ) -{ - addHInstr(env->code, instr); - if (vex_traceflags & VEX_TRACE_VCODE) { - ppTILEGXInstr(instr); - vex_printf("\n"); - } -} - -static HReg newVRegI ( ISelEnv * env ) -{ - HReg reg = mkHReg(True /*virtual R*/, HRcGPR(), 0, env->vreg_ctr); - env->vreg_ctr++; - return reg; -} - -/*---------------------------------------------------------*/ -/*--- ISEL: Forward declarations ---*/ -/*---------------------------------------------------------*/ - -/* These are organised as iselXXX and iselXXX_wrk pairs. The - iselXXX_wrk do the real work, but are not to be called directly. - For each XXX, iselXXX calls its iselXXX_wrk counterpart, then - checks that all returned registers are virtual. You should not - call the _wrk version directly. -*/ -/* Compute an I8/I16/I32/I64 into a RH (reg-or-halfword-immediate). - It's important to specify whether the immediate is to be regarded - as signed or not. If yes, this will never return -32768 as an - immediate; this guaranteed that all signed immediates that are - return can have their sign inverted if need be. -*/ -static TILEGXRH *iselWordExpr_RH_wrk ( ISelEnv * env, Bool syned, IRExpr * e ); -static TILEGXRH *iselWordExpr_RH ( ISelEnv * env, Bool syned, IRExpr * e ); - -static TILEGXRH *iselWordExpr_RH6u_wrk ( ISelEnv * env, IRExpr * e ); -static TILEGXRH *iselWordExpr_RH6u ( ISelEnv * env, IRExpr * e ); - -/* compute an I8/I16/I32/I64 into a GPR*/ -static HReg iselWordExpr_R_wrk ( ISelEnv * env, IRExpr * e ); -static HReg iselWordExpr_R ( ISelEnv * env, IRExpr * e ); - -/* compute an I64 into an AMode. */ -static TILEGXAMode *iselWordExpr_AMode_wrk ( ISelEnv * env, IRExpr * e, - IRType xferTy ); -static TILEGXAMode *iselWordExpr_AMode ( ISelEnv * env, IRExpr * e, - IRType xferTy ); - -static TILEGXCondCode iselCondCode_wrk ( ISelEnv * env, IRExpr * e ); -static TILEGXCondCode iselCondCode ( ISelEnv * env, IRExpr * e ); - -/*---------------------------------------------------------*/ -/*--- ISEL: Misc helpers ---*/ -/*---------------------------------------------------------*/ - -/* Make an int reg-reg move. */ -static TILEGXInstr *mk_iMOVds_RR ( HReg r_dst, HReg r_src ) -{ - vassert(hregClass(r_dst) == hregClass(r_src)); - vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64); - return TILEGXInstr_Alu(GXalu_OR, r_dst, r_src, TILEGXRH_Reg(r_src)); -} - -/*---------------------------------------------------------*/ -/*--- ISEL: Function call helpers ---*/ -/*---------------------------------------------------------*/ - -/* Used only in doHelperCall. See big comment in doHelperCall - handling of register-parameter args. This function figures out - whether evaluation of an expression might require use of a fixed - register. -*/ -static Bool mightRequireFixedRegs ( IRExpr * e ) -{ - switch (e->tag) { - case Iex_RdTmp: - case Iex_Const: - case Iex_Get: - return False; - default: - return True; - } -} - -/* Do a complete function call. guard is a Ity_Bit expression - indicating whether or not the call happens. If guard==NULL, the - call is unconditional. */ - -static void doHelperCall ( ISelEnv * env, IRExpr * guard, IRCallee * cee, - IRExpr ** args, IRType retTy ) -{ - TILEGXCondCode cc; - HReg argregs[TILEGX_N_REGPARMS]; - HReg tmpregs[TILEGX_N_REGPARMS]; - Bool go_fast; - Long n_args, i, argreg; - ULong argiregs; - ULong target; - HReg src = INVALID_HREG; - - - UInt nVECRETs = 0; - UInt nGSPTRs = 0; - - /* TILEGX calling convention: up to 10 registers (r0 ... r9) - are allowed to be used for passing integer arguments. They correspond - to regs GPR0 ... GPR9. */ - - /* Note that the cee->regparms field is meaningless on ARM64 hosts - (since there is only one calling convention) and so we always - ignore it. */ - - n_args = 0; - for (i = 0; args[i]; i++) { - n_args++; - IRExpr* arg = args[i]; - if (UNLIKELY(arg->tag == Iex_VECRET)) { - nVECRETs++; - } else if (UNLIKELY(arg->tag == Iex_GSPTR)) { - nGSPTRs++; - } - } - - if (nVECRETs || nGSPTRs) - vex_printf("nVECRETs=%u, nGSPTRs=%u\n", - nVECRETs, nGSPTRs); - - if (TILEGX_N_REGPARMS < n_args) { - vpanic("doHelperCall(TILEGX): cannot currently handle > 10 args"); - } - argregs[0] = hregTILEGX_R0(); - argregs[1] = hregTILEGX_R1(); - argregs[2] = hregTILEGX_R2(); - argregs[3] = hregTILEGX_R3(); - argregs[4] = hregTILEGX_R4(); - argregs[5] = hregTILEGX_R5(); - argregs[6] = hregTILEGX_R6(); - argregs[7] = hregTILEGX_R7(); - argregs[8] = hregTILEGX_R8(); - argregs[9] = hregTILEGX_R9(); - argiregs = 0; - - for (i = 0; i < TILEGX_N_REGPARMS; i++) - tmpregs[i] = INVALID_HREG; - - /* First decide which scheme (slow or fast) is to be used. First - assume the fast scheme, and select slow if any contraindications - (wow) appear. */ - - go_fast = True; - - if (guard) { - if (guard->tag == Iex_Const && guard->Iex.Const.con->tag == Ico_U1 - && guard->Iex.Const.con->Ico.U1 == True) { - /* unconditional */ - } else { - /* Not manifestly unconditional -- be conservative. */ - go_fast = False; - } - } - - if (go_fast) { - for (i = 0; i < n_args; i++) { - if (mightRequireFixedRegs(args[i])) { - go_fast = False; - break; - } - } - } - - /* At this point the scheme to use has been established. Generate - code to get the arg values into the argument rregs. */ - if (go_fast) { - /* FAST SCHEME */ - argreg = 0; - - for (i = 0; i < n_args; i++) { - vassert(argreg < TILEGX_N_REGPARMS); - vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32 || - typeOfIRExpr(env->type_env, args[i]) == Ity_I64); - - argiregs |= (1 << (argreg)); - addInstr(env, mk_iMOVds_RR(argregs[argreg], - iselWordExpr_R(env, - args[i]))); - argreg++; - } - /* Fast scheme only applies for unconditional calls. Hence: */ - cc = TILEGXcc_AL; - } else { - /* SLOW SCHEME; move via temporaries */ - argreg = 0; - - for (i = 0; i < n_args; i++) { - vassert(argreg < TILEGX_N_REGPARMS); - vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32 - || typeOfIRExpr(env->type_env, args[i]) == Ity_I64); - tmpregs[argreg] = iselWordExpr_R(env, args[i]); - argreg++; - } - - /* Now we can compute the condition. We can't do it earlier - because the argument computations could trash the condition - codes. Be a bit clever to handle the common case where the - guard is 1:Bit. */ - cc = TILEGXcc_AL; - if (guard) { - if (guard->tag == Iex_Const && guard->Iex.Const.con->tag == Ico_U1 - && guard->Iex.Const.con->Ico.U1 == True) { - /* unconditional -- do nothing */ - } else { - cc = iselCondCode(env, guard); - src = iselWordExpr_R(env, guard); - } - } - /* Move the args to their final destinations. */ - for (i = 0; i < argreg; i++) { - if (hregIsInvalid(tmpregs[i])) // Skip invalid regs - continue; - /* None of these insns, including any spill code that might - be generated, may alter the condition codes. */ - argiregs |= (1 << (i)); - addInstr(env, mk_iMOVds_RR(argregs[i], tmpregs[i])); - } - } - - target = (Addr)(cee->addr); - - /* Finally, the call itself. */ - if (cc == TILEGXcc_AL) - addInstr(env, TILEGXInstr_CallAlways(cc, target, argiregs)); - else - addInstr(env, TILEGXInstr_Call(cc, target, argiregs, src)); -} - -/*---------------------------------------------------------*/ -/*--- ISEL: Integer expression auxiliaries ---*/ -/*---------------------------------------------------------*/ - -/* --------------------- AMODEs --------------------- */ - -/* Return an AMode which computes the value of the specified - expression, possibly also adding insns to the code list as a - result. The expression may only be a word-size one. -*/ - -static Bool uInt_fits_in_16_bits ( UInt u ) -{ - UInt v = u & 0xFFFF; - - v = (Int)(v << 16) >> 16; /* sign extend */ - - return u == v; -} - -static Bool sane_AMode ( ISelEnv * env, TILEGXAMode * am ) -{ - if (am->tag == GXam_IR) - return toBool(hregClass(am->GXam.IR.base) == HRcGPR() && - hregIsVirtual(am->GXam.IR.base) && - uInt_fits_in_16_bits(am->GXam.IR.index)); - - vpanic("sane_AMode: unknown tilegx amode tag"); -} - -static TILEGXAMode *iselWordExpr_AMode ( ISelEnv * env, IRExpr * e, - IRType xferTy ) -{ - TILEGXAMode *am = iselWordExpr_AMode_wrk(env, e, xferTy); - vassert(sane_AMode(env, am)); - return am; -} - -/* DO NOT CALL THIS DIRECTLY ! */ -static TILEGXAMode *iselWordExpr_AMode_wrk ( ISelEnv * env, IRExpr * e, - IRType xferTy ) -{ - IRType ty = typeOfIRExpr(env->type_env, e); - - vassert(ty == Ity_I64); - /* Add64(expr,i), where i == sign-extend of (i & 0xFFFF) */ - if (e->tag == Iex_Binop - && e->Iex.Binop.op == Iop_Add64 - && e->Iex.Binop.arg2->tag == Iex_Const - && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64 - && uInt_fits_in_16_bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) { - - return TILEGXAMode_IR((Long) e->Iex.Binop.arg2->Iex.Const.con->Ico.U64, - iselWordExpr_R(env, e->Iex.Binop.arg1)); - } - - /* Doesn't match anything in particular. Generate it into - a register and use that. */ - return TILEGXAMode_IR(0, iselWordExpr_R(env, e)); -} - - - - - -/*---------------------------------------------------------*/ -/*--- ISEL: Integer expressions (64/32/16/8 bit) ---*/ -/*---------------------------------------------------------*/ - -/* Select insns for an integer-typed expression, and add them to the - code list. Return a reg holding the result. This reg will be a - virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you - want to modify it, ask for a new vreg, copy it in there, and modify - the copy. The register allocator will do its best to map both - add vregs to the same real register, so the copies will often disappear - later in the game. - - This should handle expressions of 64, 32, 16 and 8-bit type. - All results are returned in a 64bit register. -*/ -static HReg iselWordExpr_R ( ISelEnv * env, IRExpr * e ) -{ - HReg r = iselWordExpr_R_wrk(env, e); - /* sanity checks ... */ - - vassert(hregClass(r) == HRcGPR()); - vassert(hregIsVirtual(r)); - return r; -} - -/* DO NOT CALL THIS DIRECTLY ! */ -static HReg iselWordExpr_R_wrk ( ISelEnv * env, IRExpr * e ) -{ - IRType ty = typeOfIRExpr(env->type_env, e); - vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || - ty == Ity_I1 || ty == Ity_I64); - - switch (e->tag) { - /* --------- TEMP --------- */ - case Iex_RdTmp: - return lookupIRTemp(env, e->Iex.RdTmp.tmp); - - /* --------- LOAD --------- */ - case Iex_Load: { - HReg r_dst = newVRegI(env); - TILEGXAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty); - - if (e->Iex.Load.end != Iend_LE - && e->Iex.Load.end != Iend_BE) - goto irreducible; - - addInstr(env, TILEGXInstr_Load(toUChar(sizeofIRType(ty)), - r_dst, am_addr)); - return r_dst; - break; - } - /* --------- BINARY OP --------- */ - case Iex_Binop: { - TILEGXAluOp aluOp; - TILEGXShftOp shftOp; - - switch (e->Iex.Binop.op) { - - case Iop_Add8: - case Iop_Add16: - case Iop_Add32: - case Iop_Add64: - aluOp = GXalu_ADD; - break; - - case Iop_Sub8: - case Iop_Sub16: - case Iop_Sub32: - case Iop_Sub64: - aluOp = GXalu_SUB; - break; - - case Iop_And8: - case Iop_And16: - case Iop_And32: - case Iop_And64: - aluOp = GXalu_AND; - break; - - case Iop_Or8: - case Iop_Or16: - case Iop_Or32: - case Iop_Or64: - aluOp = GXalu_OR; - break; - - case Iop_Xor8: - case Iop_Xor16: - case Iop_Xor32: - case Iop_Xor64: - aluOp = GXalu_XOR; - break; - - default: - aluOp = GXalu_INVALID; - break; - } - - /* For commutative ops we assume any literal - values are on the second operand. */ - if (aluOp != GXalu_INVALID) { - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); - TILEGXRH *ri_srcR = NULL; - /* get right arg into an RH, in the appropriate way */ - switch (aluOp) { - case GXalu_ADD: - case GXalu_SUB: - ri_srcR = iselWordExpr_RH(env, True /*signed */ , - e->Iex.Binop.arg2); - break; - case GXalu_AND: - case GXalu_OR: - case GXalu_XOR: - ri_srcR = iselWordExpr_RH(env, True /*signed */, - e->Iex.Binop.arg2); - break; - default: - vpanic("iselWordExpr_R_wrk-aluOp-arg2"); - } - addInstr(env, TILEGXInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR)); - return r_dst; - } - - /* a shift? */ - switch (e->Iex.Binop.op) { - case Iop_Shl32: - case Iop_Shl64: - shftOp = GXshft_SLL; - break; - case Iop_Shr32: - case Iop_Shr64: - shftOp = GXshft_SRL; - break; - case Iop_Sar64: - shftOp = GXshft_SRA; - break; - case Iop_Shl8x8: - shftOp = GXshft_SLL8x8; - break; - case Iop_Shr8x8: - shftOp = GXshft_SRL8x8; - break; - default: - shftOp = GXshft_INVALID; - break; - } - - /* we assume any literal values are on the second operand. */ - if (shftOp != GXshft_INVALID) { - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); - TILEGXRH *ri_srcR = NULL; - /* get right arg into an RH, in the appropriate way */ - switch (shftOp) { - case GXshft_SLL: - case GXshft_SRL: - case GXshft_SRA: - //ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); - //break; - case GXshft_SLL8x8: - case GXshft_SRL8x8: - //if (e->Iex.Binop.arg2->tag == GXrh_Imm) - //{ - // ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); - // break; - //} - ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); - break; - default: - vpanic("iselIntExpr_R_wrk-shftOp-arg2"); - } - /* widen the left arg if needed */ - /*TODO do we need this? */ - if (ty == Ity_I8 || ty == Ity_I16) - goto irreducible; - if (ty == Ity_I64) { - addInstr(env, TILEGXInstr_Shft(shftOp, False/*64bit shift */, - r_dst, r_srcL, ri_srcR)); - } else { - addInstr(env, TILEGXInstr_Shft(shftOp, True /*32bit shift */, - r_dst, r_srcL, ri_srcR)); - } - return r_dst; - } - - /* Cmp*32*(x,y) ? */ - if (e->Iex.Binop.op == Iop_CasCmpEQ32 - || e->Iex.Binop.op == Iop_CmpEQ32 - || e->Iex.Binop.op == Iop_CasCmpNE32 - || e->Iex.Binop.op == Iop_CmpNE32 - || e->Iex.Binop.op == Iop_CmpNE64 - || e->Iex.Binop.op == Iop_CmpLT32S - || e->Iex.Binop.op == Iop_CmpLT32U - || e->Iex.Binop.op == Iop_CmpLT64U - || e->Iex.Binop.op == Iop_CmpLE32S - || e->Iex.Binop.op == Iop_CmpLE64S - || e->Iex.Binop.op == Iop_CmpLE64U - || e->Iex.Binop.op == Iop_CmpLT64S - || e->Iex.Binop.op == Iop_CmpEQ64 - || e->Iex.Binop.op == Iop_CasCmpEQ64 - || e->Iex.Binop.op == Iop_CasCmpNE64) { - - Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S - || e->Iex.Binop.op == Iop_CmpLE32S - || e->Iex.Binop.op == Iop_CmpLT64S - || e->Iex.Binop.op == Iop_CmpLE64S); - Bool size32; - HReg dst = newVRegI(env); - HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1); - HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2); - TILEGXCondCode cc; - - switch (e->Iex.Binop.op) { - case Iop_CasCmpEQ32: - case Iop_CmpEQ32: - cc = TILEGXcc_EQ; - size32 = True; - break; - case Iop_CasCmpNE32: - case Iop_CmpNE32: - cc = TILEGXcc_NE; - size32 = True; - break; - case Iop_CasCmpNE64: - case Iop_CmpNE64: - cc = TILEGXcc_NE; - size32 = True; - break; - case Iop_CmpLT32S: - cc = TILEGXcc_LT; - size32 = True; - break; - case Iop_CmpLT32U: - cc = TILEGXcc_LO; - size32 = True; - break; - case Iop_CmpLT64U: - cc = TILEGXcc_LT; - size32 = False; - break; - case Iop_CmpLE32S: - cc = TILEGXcc_LE; - size32 = True; - break; - case Iop_CmpLE64S: - cc = TILEGXcc_LE; - size32 = False; - break; - case Iop_CmpLE64U: - cc = TILEGXcc_LE; - size32 = False; - break; - case Iop_CmpLT64S: - cc = TILEGXcc_LT; - size32 = False; - break; - case Iop_CasCmpEQ64: - case Iop_CmpEQ64: - cc = TILEGXcc_EQ; - size32 = False; - break; - default: - vpanic - ("iselCondCode(tilegx): CmpXX32 or CmpXX64"); - } - - addInstr(env, TILEGXInstr_Cmp(syned, size32, dst, r1, r2, cc)); - return dst; - - break; - - } - - if (e->Iex.Binop.op == Iop_CmpEQ8x8) { - - Bool syned = False; - - Bool size32; - HReg dst = newVRegI(env); - HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1); - TILEGXRH *r2 = iselWordExpr_RH(env, True, e->Iex.Binop.arg2); - TILEGXCondCode cc; - - switch (e->Iex.Binop.op) { - case Iop_CmpEQ8x8: - cc = TILEGXcc_EQ8x8; - size32 = False; - break; - - default: - vassert(0); - } - - addInstr(env, TILEGXInstr_CmpI(syned, size32, dst, r1, r2, cc)); - return dst; - - break; - } - - if (e->Iex.Binop.op == Iop_Max32U) { - /* - tmp = argL - argR; - tmp &= (1<<31) - dst = (tmp) ? (argL) ? (argR) - */ - HReg argL = iselWordExpr_R(env, e->Iex.Binop.arg1); - TILEGXRH *argR = iselWordExpr_RH(env, False /*signed */ , - e->Iex.Binop.arg2); - HReg dst = newVRegI(env); - HReg tmp = newVRegI(env); - // temp = argL - argR - addInstr(env, TILEGXInstr_Alu(GXalu_SUB, tmp, argL, argR)); - // tmp &= bit31 - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, tmp, tmp , 31, 31)); - // (tmp == 0) ? (argL) : (argR) - addInstr(env, TILEGXInstr_MovCond(dst, argL, argR, tmp, TILEGXcc_EZ)); - return dst; - } - - if (e->Iex.Binop.op == Iop_MullS32 || e->Iex.Binop.op == Iop_MullU32) { - Bool syned = (e->Iex.Binop.op == Iop_MullS32); - Bool sz32 = (e->Iex.Binop.op == Iop_Mul32); - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); - HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); - addInstr(env, TILEGXInstr_Mul(syned /*Unsigned or Signed */ , - True /*widen */ , - sz32 /*32bit or 64bit */, - r_dst, r_srcL, r_srcR)); - return r_dst; - } - - if (e->Iex.Binop.op == Iop_32HLto64) { - HReg tHi = iselWordExpr_R(env, e->Iex.Binop.arg1); - HReg tLo = iselWordExpr_R(env, e->Iex.Binop.arg2); - HReg tLo_1 = newVRegI(env); - HReg tHi_1 = newVRegI(env); - HReg r_dst = newVRegI(env); - HReg mask = newVRegI(env); - - addInstr(env, TILEGXInstr_Shft(GXshft_SLL, False, tHi_1, tHi, - TILEGXRH_Imm(False, 32))); - - addInstr(env, TILEGXInstr_LI(mask, 0xffffffff)); - addInstr(env, TILEGXInstr_Alu(GXalu_AND, tLo_1, tLo, - TILEGXRH_Reg(mask))); - addInstr(env, TILEGXInstr_Alu(GXalu_OR, r_dst, tHi_1, - TILEGXRH_Reg(tLo_1))); - - return r_dst; - } - - /* Anything reached here !*/ - goto irreducible; - } - - /* --------- UNARY OP --------- */ - case Iex_Unop: { - - IROp op_unop = e->Iex.Unop.op; - - switch (op_unop) { - case Iop_Not1: { - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg); - TILEGXRH *r_srcR = TILEGXRH_Reg(r_srcL); - - addInstr(env, TILEGXInstr_LI(r_dst, 0x1)); - addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, r_dst, r_srcR)); - return r_dst; - } - - case Iop_Not8: - case Iop_Not16: - case Iop_Not32: - case Iop_Not64: { - /* not x = nor x, x */ - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg); - TILEGXRH *r_srcR = TILEGXRH_Reg(r_srcL); - - addInstr(env, TILEGXInstr_Alu(GXalu_NOR, r_dst, r_srcL, r_srcR)); - return r_dst; - } - - case Iop_CmpNEZ8x8: { - - Bool syned = False; - Bool size32; - HReg dst = newVRegI(env); - HReg r1; - TILEGXCondCode cc = TILEGXcc_NE8x8; - size32 = False; - r1 = iselWordExpr_R(env, e->Iex.Unop.arg); - addInstr(env, TILEGXInstr_CmpI(syned, size32, dst, hregTILEGX_R63(), - TILEGXRH_Reg(r1), cc)); - - return dst; - break; - } - - case Iop_16to8: - case Iop_32to8: - case Iop_64to8: - case Iop_32to16: - case Iop_64to16: - case Iop_64to32: - case Iop_128to64: - - return iselWordExpr_R(env, e->Iex.Unop.arg); - - case Iop_1Uto64: - case Iop_1Uto32: - case Iop_1Uto8: { - HReg dst = newVRegI(env); - HReg src = iselWordExpr_R(env, e->Iex.Unop.arg); - addInstr(env, TILEGXInstr_Alu(GXalu_AND, dst, src, TILEGXRH_Imm(False, 1))); - return dst; - } - case Iop_8Uto16: - case Iop_8Uto32: - case Iop_8Uto64: - case Iop_16Uto32: - case Iop_16Uto64: { - - HReg dst = newVRegI(env); - HReg src = iselWordExpr_R(env, e->Iex.Unop.arg); - Bool srcIs16 = toBool( e->Iex.Unop.op==Iop_16Uto32 - || e->Iex.Unop.op==Iop_16Uto64 ); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, dst, src, - 0, - srcIs16 ? 15 : 7)); - - return dst; - } - - case Iop_32to1: - case Iop_64to1: - { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_dst, r_src, 0, 0)); - return r_dst; - } - case Iop_1Sto32: - case Iop_1Sto64: - { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 0)); - return r_dst; - } - case Iop_8Sto16: - case Iop_8Sto32: - case Iop_8Sto64: - { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 7)); - return r_dst; - } - case Iop_16Sto32: - case Iop_16Sto64: - { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 15)); - return r_dst; - } - case Iop_32Uto64: - { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_dst, r_src, 0, 31)); - return r_dst; - } - case Iop_32Sto64: - { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Bf(GXbf_EXTS, r_dst, r_src, 0, 31)); - return r_dst; - } - - case Iop_CmpNEZ8: { - HReg r_dst = newVRegI(env); - HReg tmp = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - TILEGXCondCode cc; - - cc = TILEGXcc_NE; - addInstr(env, TILEGXInstr_Alu(GXalu_AND, tmp, r_src, - TILEGXRH_Imm(False, 0xFF))); - addInstr(env, TILEGXInstr_Cmp(False, True, r_dst, tmp, - hregTILEGX_R63(), cc)); - return r_dst; - } - - case Iop_CmpNEZ32: { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - TILEGXCondCode cc; - - cc = TILEGXcc_NE; - - addInstr(env, TILEGXInstr_Cmp(False, True, r_dst, r_src, - hregTILEGX_R63(), cc)); - return r_dst; - } - - case Iop_CmpwNEZ32: { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, hregTILEGX_R63(), - TILEGXRH_Reg(r_src))); - - addInstr(env, TILEGXInstr_Alu(GXalu_OR, r_dst, r_dst, - TILEGXRH_Reg(r_src))); - addInstr(env, TILEGXInstr_Shft(GXshft_SRA, True, r_dst, r_dst, - TILEGXRH_Imm(False, 31))); - return r_dst; - } - - case Iop_Left8: - case Iop_Left16: - case Iop_Left32: - case Iop_Left64: { - - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, hregTILEGX_R63(), - TILEGXRH_Reg(r_src))); - addInstr(env, TILEGXInstr_Alu(GXalu_OR, r_dst, r_dst, - TILEGXRH_Reg(r_src))); - return r_dst; - } - - case Iop_Ctz64: - case Iop_Clz64: { - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - if (op_unop == Iop_Clz64) - addInstr(env, TILEGXInstr_Unary(GXun_CLZ, r_dst, r_src)); - else - addInstr(env, TILEGXInstr_Unary(GXun_CTZ, r_dst, r_src)); - return r_dst; - } - - case Iop_CmpNEZ64: { - - HReg r_dst = newVRegI(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - TILEGXCondCode cc; - - cc = TILEGXcc_NE; - - addInstr(env, TILEGXInstr_Cmp(False, False, r_dst, r_src, - hregTILEGX_R63(), cc)); - return r_dst; - } - - case Iop_CmpwNEZ64: { - HReg tmp1; - HReg tmp2 = newVRegI(env); - - tmp1 = iselWordExpr_R(env, e->Iex.Unop.arg); - - addInstr(env, TILEGXInstr_Alu(GXalu_SUB, tmp2, hregTILEGX_R63(), - TILEGXRH_Reg(tmp1))); - - addInstr(env, TILEGXInstr_Alu(GXalu_OR, tmp2, tmp2, TILEGXRH_Reg(tmp1))); - addInstr(env, TILEGXInstr_Shft(GXshft_SRA, False, tmp2, tmp2, - TILEGXRH_Imm (False, 63))); - return tmp2; - } - - default: - goto irreducible; - break; - } - break; - } - - /* --------- GET --------- */ - case Iex_Get: { - if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 - || ((ty == Ity_I64))) { - HReg r_dst; - TILEGXAMode *am_addr; - r_dst = newVRegI(env); - am_addr = TILEGXAMode_IR(e->Iex.Get.offset, - TILEGXGuestStatePointer()); - addInstr(env, TILEGXInstr_Load(toUChar(sizeofIRType(ty)), - r_dst, am_addr)); - return r_dst; - } - } - - /* --------- ITE --------- */ - case Iex_ITE: { - if ((ty == Ity_I8 || ty == Ity_I16 || - ty == Ity_I32 || ((ty == Ity_I64))) && - typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) { - - HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse); - HReg r1 = iselWordExpr_R(env, e->Iex.ITE.iftrue); - HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond); - HReg r_dst = newVRegI(env); - - /* r_dst = (r_cond) ? r1 : r0 */ - - addInstr(env, TILEGXInstr_MovCond(r_dst, r0, TILEGXRH_Reg(r1), - r_cond, TILEGXcc_EZ)); - - return r_dst; - } - } - - /* --------- LITERAL --------- */ - /* 32/16/8-bit literals */ - case Iex_Const: { - Long l; - HReg r_dst = newVRegI(env); - IRConst *con = e->Iex.Const.con; - switch (con->tag) { - case Ico_U64: - - l = (Long) con->Ico.U64; - break; - case Ico_U32: - l = (Long) (Int) con->Ico.U32; - break; - case Ico_U16: - l = (Long) (Int) (Short) con->Ico.U16; - break; - case Ico_U8: - l = (Long) (Int) (Char) con->Ico.U8; - break; - default: - vpanic("iselIntExpr_R.const(tilegx)"); - } - addInstr(env, TILEGXInstr_LI(r_dst, (ULong) l)); - return r_dst; - } - - /* --------- CCALL --------- */ - case Iex_CCall: { - HReg r_dst = newVRegI(env); - vassert(ty == e->Iex.CCall.retty); - - /* Marshal args, do the call, clear stack. */ - doHelperCall(env, NULL, e->Iex.CCall.cee, e->Iex.CCall.args, - e->Iex.CCall.retty); - - /* r0 is the return value. */ - addInstr(env, mk_iMOVds_RR(r_dst, hregTILEGX_R0())); - - return r_dst; - } - - default: - goto irreducible; - break; - } /* end switch(e->tag) */ - - /* We get here if no pattern matched. */ - irreducible: - vex_printf("--------------->\n"); - if (e->tag == Iex_RdTmp) - vex_printf("Iex_RdTmp \n"); - ppIRExpr(e); - - vpanic("iselWordExpr_R(tilegx): cannot reduce tree"); -} - -/* --------------------- RH --------------------- */ - -/* Compute an I8/I16/I32/I64 into a RH - (reg-or-halfword-immediate). It's important to specify whether the - immediate is to be regarded as signed or not. If yes, this will - never return -32768 as an immediate; this guaranteed that all - signed immediates that are return can have their sign inverted if - need be. */ - -static TILEGXRH *iselWordExpr_RH ( ISelEnv * env, Bool syned, IRExpr * e ) -{ - TILEGXRH *ri = iselWordExpr_RH_wrk(env, syned, e); - /* sanity checks ... */ - switch (ri->tag) { - case GXrh_Imm: - vassert(ri->GXrh.Imm.syned == syned); - if (syned) - vassert(ri->GXrh.Imm.imm16 != 0x8000); - return ri; - case GXrh_Reg: - vassert(hregClass(ri->GXrh.Reg.reg) == HRcGPR()); - vassert(hregIsVirtual(ri->GXrh.Reg.reg)); - return ri; - default: - vpanic("iselIntExpr_RH: unknown tilegx RH tag"); - } -} - -/* DO NOT CALL THIS DIRECTLY ! */ -static TILEGXRH *iselWordExpr_RH_wrk ( ISelEnv * env, Bool syned, IRExpr * e ) -{ - ULong u; - Long l; - IRType ty = typeOfIRExpr(env->type_env, e); - vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || - ((ty == Ity_I64))); - - /* special case: immediate */ - if (e->tag == Iex_Const) { - IRConst *con = e->Iex.Const.con; - /* What value are we aiming to generate? */ - switch (con->tag) { - /* Note: Not sign-extending - we carry 'syned' around */ - case Ico_U64: - u = con->Ico.U64; - break; - case Ico_U32: - u = 0xFFFFFFFF & con->Ico.U32; - break; - case Ico_U16: - u = 0x0000FFFF & con->Ico.U16; - break; - case Ico_U8: - u = 0x000000FF & con->Ico.U8; - break; - default: - vpanic("iselIntExpr_RH.Iex_Const(tilegx)"); - } - l = (Long) u; - /* Now figure out if it's representable. */ - if (!syned && u <= 255) { - return TILEGXRH_Imm(False /*unsigned */ , toUShort(u & 0xFFFF)); - } - if (syned && l >= -127 && l <= 127) { - return TILEGXRH_Imm(True /*signed */ , toUShort(u & 0xFFFF)); - } - /* no luck; use the Slow Way. */ - } - /* default case: calculate into a register and return that */ - return TILEGXRH_Reg(iselWordExpr_R(env, e)); -} - -/* --------------------- RH6u --------------------- */ - -/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter - being an immediate in the range 0 .. 63 inclusive. Used for doing - shift amounts. */ - -static TILEGXRH *iselWordExpr_RH6u ( ISelEnv * env, IRExpr * e ) -{ - TILEGXRH *ri; - ri = iselWordExpr_RH6u_wrk(env, e); - /* sanity checks ... */ - switch (ri->tag) { - case GXrh_Imm: - vassert(ri->GXrh.Imm.imm16 >= 1 && ri->GXrh.Imm.imm16 <= 63); - vassert(!ri->GXrh.Imm.syned); - return ri; - case GXrh_Reg: - vassert(hregClass(ri->GXrh.Reg.reg) == HRcInt64); - vassert(hregIsVirtual(ri->GXrh.Reg.reg)); - return ri; - default: - vpanic("iselIntExpr_RH6u: unknown tilegx RH tag"); - } -} - -/* DO NOT CALL THIS DIRECTLY ! */ -static TILEGXRH *iselWordExpr_RH6u_wrk ( ISelEnv * env, IRExpr * e ) -{ - IRType ty = typeOfIRExpr(env->type_env, e); - - /* special case: immediate */ - if (e->tag == Iex_Const) - { - if (ty == Ity_I8) - { - if(e->Iex.Const.con->tag == Ico_U8 - && e->Iex.Const.con->Ico.U8 >= 1 && e->Iex.Const.con->Ico.U8 <= 63) - return TILEGXRH_Imm(False /*unsigned */ , e->Iex.Const.con->Ico.U8); - } - else if (ty == Ity_I64) - { - if(e->Iex.Const.con->tag == Ico_U64 - && e->Iex.Const.con->Ico.U64 >= 1 - && e->Iex.Const.con->Ico.U64 <= 63) - return TILEGXRH_Imm(False /*unsigned */, e->Iex.Const.con->Ico.U64); - } - } - - /* default case: calculate into a register and return that */ - return TILEGXRH_Reg(iselWordExpr_R(env, e)); -} - -/* --------------------- CONDCODE --------------------- */ - -/* Generate code to evaluated a bit-typed expression, returning the - condition code which would correspond when the expression would - notionally have returned 1. */ - -static TILEGXCondCode iselCondCode(ISelEnv * env, IRExpr * e) -{ - TILEGXCondCode cc = iselCondCode_wrk(env,e); - vassert(cc != TILEGXcc_NV); - return cc; -} - -/* DO NOT CALL THIS DIRECTLY ! */ -static TILEGXCondCode iselCondCode_wrk ( ISelEnv * env, IRExpr * e ) -{ - vassert(e); - vassert(typeOfIRExpr(env->type_env, e) == Ity_I1); - - /* Cmp*(x,y) ? */ - if (e->Iex.Binop.op == Iop_CmpEQ32 - || e->Iex.Binop.op == Iop_CmpNE32 - || e->Iex.Binop.op == Iop_CmpNE64 - || e->Iex.Binop.op == Iop_CmpLT32S - || e->Iex.Binop.op == Iop_CmpLT32U - || e->Iex.Binop.op == Iop_CmpLT64U - || e->Iex.Binop.op == Iop_CmpLE32S - || e->Iex.Binop.op == Iop_CmpLE64S - || e->Iex.Binop.op == Iop_CmpLT64S - || e->Iex.Binop.op == Iop_CmpEQ64 - || e->Iex.Binop.op == Iop_CasCmpEQ32 - || e->Iex.Binop.op == Iop_CasCmpEQ64) { - - Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S - || e->Iex.Binop.op == Iop_CmpLE32S - || e->Iex.Binop.op == Iop_CmpLT64S - || e->Iex.Binop.op == Iop_CmpLE64S); - Bool size32; - HReg dst = newVRegI(env); - HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1); - HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2); - - TILEGXCondCode cc; - - switch (e->Iex.Binop.op) { - case Iop_CmpEQ32: - case Iop_CasCmpEQ32: - cc = TILEGXcc_EQ; - size32 = True; - break; - case Iop_CmpNE32: - cc = TILEGXcc_NE; - size32 = True; - break; - case Iop_CmpNE64: - cc = TILEGXcc_NE; - size32 = True; - break; - case Iop_CmpLT32S: - cc = TILEGXcc_LT; - size32 = True; - break; - case Iop_CmpLT32U: - cc = TILEGXcc_LO; - size32 = True; - break; - case Iop_CmpLT64U: - cc = TILEGXcc_LO; - size32 = False; - break; - case Iop_CmpLE32S: - cc = TILEGXcc_LE; - size32 = True; - break; - case Iop_CmpLE64S: - cc = TILEGXcc_LE; - size32 = False; - break; - case Iop_CmpLT64S: - cc = TILEGXcc_LT; - size32 = False; - break; - case Iop_CmpEQ64: - case Iop_CasCmpEQ64: - cc = TILEGXcc_EQ; - size32 = False; - break; - default: - vpanic("iselCondCode(tilegx): CmpXX32 or CmpXX64"); - break; - } - - addInstr(env, TILEGXInstr_Cmp(syned, size32, dst, r1, r2, cc)); - /* Store result to guest_COND */ - TILEGXAMode *am_addr = TILEGXAMode_IR(0, TILEGXGuestStatePointer()); - - addInstr(env, TILEGXInstr_Store(8, - TILEGXAMode_IR(am_addr->GXam.IR.index + - COND_OFFSET(), - am_addr->GXam.IR.base), - dst)); - return cc; - } - - if (e->Iex.Binop.op == Iop_Not1) { - HReg r_dst = newVRegI(env); - HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg); - TILEGXRH *r_srcR = TILEGXRH_Reg(r_srcL); - - addInstr(env, TILEGXInstr_LI(r_dst, 0x1)); - addInstr(env, TILEGXInstr_Alu(GXalu_SUB, r_dst, r_dst, r_srcR)); - - /* Store result to guest_COND */ - TILEGXAMode *am_addr = TILEGXAMode_IR(0, TILEGXGuestStatePointer()); - - addInstr(env, TILEGXInstr_Store(8, - TILEGXAMode_IR(am_addr->GXam.IR.index + - COND_OFFSET(), - am_addr->GXam.IR.base), - r_dst)); - return TILEGXcc_NE; - } - - if (e->tag == Iex_RdTmp || e->tag == Iex_Unop) { - HReg r_dst = iselWordExpr_R_wrk(env, e); - /* Store result to guest_COND */ - TILEGXAMode *am_addr = TILEGXAMode_IR(0, TILEGXGuestStatePointer()); - - addInstr(env, TILEGXInstr_Store(8, - TILEGXAMode_IR(am_addr->GXam.IR.index + - COND_OFFSET(), - am_addr->GXam.IR.base), - r_dst)); - return TILEGXcc_EQ; - } - - vex_printf("iselCondCode(tilegx): No such tag(%u)\n", e->tag); - ppIRExpr(e); - vpanic("iselCondCode(tilegx)"); - - /* Constant 1:Bit */ - if (e->tag == Iex_Const && e->Iex.Const.con->Ico.U1 == True) - return TILEGXcc_AL; - - if (e->tag == Iex_RdTmp) - return TILEGXcc_EQ; - - if (e->tag == Iex_Binop) - return TILEGXcc_EQ; - - if (e->tag == Iex_Unop) - return TILEGXcc_EQ; - - vex_printf("iselCondCode(tilegx): No such tag(%u)\n", e->tag); - ppIRExpr(e); - vpanic("iselCondCode(tilegx)"); -} - -/*---------------------------------------------------------*/ -/*--- ISEL: Statements ---*/ -/*---------------------------------------------------------*/ - -static void iselStmt ( ISelEnv * env, IRStmt * stmt ) -{ - if (vex_traceflags & VEX_TRACE_VCODE) { - vex_printf("\n-- "); - ppIRStmt(stmt); - vex_printf("\n"); - } - - switch (stmt->tag) { - /* --------- STORE --------- */ - case Ist_Store: { - TILEGXAMode *am_addr; - IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); - - /*constructs addressing mode from address provided */ - am_addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd); - - if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32 || - (tyd == Ity_I64)) { - HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data); - addInstr(env, TILEGXInstr_Store(toUChar(sizeofIRType(tyd)), - am_addr, r_src)); - return; - } - break; - } - - /* --------- PUT --------- */ - case Ist_Put: { - IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data); - - if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || - (ty == Ity_I64)) { - HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data); - TILEGXAMode *am_addr = TILEGXAMode_IR(stmt->Ist.Put.offset, - TILEGXGuestStatePointer()); - addInstr(env, TILEGXInstr_Store(toUChar(sizeofIRType(ty)), - am_addr, r_src)); - return; - } - break; - } - - /* --------- TMP --------- */ - case Ist_WrTmp: { - IRTemp tmp = stmt->Ist.WrTmp.tmp; - IRType ty = typeOfIRTemp(env->type_env, tmp); - HReg r_dst = lookupIRTemp(env, tmp); - HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data); - IRType dty = typeOfIRExpr(env->type_env, stmt->Ist.WrTmp.data); - - if (ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8 || - (ty == dty)) - { - addInstr(env, mk_iMOVds_RR(r_dst, r_src)); - return; - } - else if (ty == Ity_I1) { - switch (dty) - { - case Ity_I32: - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_src, r_src, 0, 31)); - break; - case Ity_I16: - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_src, r_src, 0, 15)); - break; - case Ity_I8: - addInstr(env, TILEGXInstr_Bf(GXbf_EXTU, r_src, r_src, 0, 7)); - break; - default: - vassert(0); - } - - addInstr(env, TILEGXInstr_MovCond(r_dst, - hregTILEGX_R63(), - TILEGXRH_Imm(False, 1), - r_src, - TILEGXcc_EZ)); - return; - } - break; - } - - /* --------- Call to DIRTY helper --------- */ - case Ist_Dirty: { - IRType retty; - IRDirty *d = stmt->Ist.Dirty.details; - - /* Marshal args, do the call, clear stack. */ - doHelperCall(env, d->guard, d->cee, d->args, -1); - - /* Now figure out what to do with the returned value, if any. */ - if (d->tmp == IRTemp_INVALID) - /* No return value. Nothing to do. */ - return; - - retty = typeOfIRTemp(env->type_env, d->tmp); - - if (retty == Ity_I8 || retty == Ity_I16 || retty == Ity_I32 - || (retty == Ity_I64)) { - /* The returned value is in r0. Park it in the register - associated with tmp. */ - HReg r_dst = lookupIRTemp(env, d->tmp); - addInstr(env, mk_iMOVds_RR(r_dst, hregTILEGX_R0())); - return; - } - break; - } - - - /* --------- ACAS --------- */ - case Ist_CAS: - { - UChar sz; - IRCAS* cas = stmt->Ist.CAS.details; - IRType ty = typeOfIRExpr(env->type_env, cas->dataLo); - - TILEGXAMode *r_addr = iselWordExpr_AMode(env, cas->addr, Ity_I64); - HReg r_new = iselWordExpr_R(env, cas->dataLo); - HReg r_old = lookupIRTemp(env, cas->oldLo); - HReg r_exp = INVALID_HREG; - - vassert(cas->expdHi == NULL); - vassert(cas->dataHi == NULL); - vassert(r_addr->tag == GXam_IR); - vassert(r_addr->GXam.IR.index == 0); - - switch (ty) - { - case Ity_I64: sz = 8; break; - case Ity_I32: sz = 4; break; - default: vassert(0); - } - - if (cas->expdLo->tag != Iex_Const) - { - r_exp = iselWordExpr_R(env, cas->expdLo); - addInstr(env, TILEGXInstr_Acas(GXacas_CMPEXCH, r_old, - r_addr->GXam.IR.base, r_exp, - r_new, sz)); - } - else - { - if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 0) || - (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 0)) - { - addInstr(env, TILEGXInstr_Acas(GXacas_EXCH, r_old, - r_addr->GXam.IR.base, - r_exp, r_new, sz)); - } - else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 2) || - (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 2)) - { - addInstr(env, TILEGXInstr_Acas(GXacas_FetchAnd, r_old, - r_addr->GXam.IR.base, r_exp, - r_new, sz)); - } - else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 3) || - (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 3)) - { - addInstr(env, TILEGXInstr_Acas(GXacas_FetchAdd, r_old, - r_addr->GXam.IR.base, - r_exp, r_new, sz)); - } - else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 4) || - (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 4)) - { - addInstr(env, TILEGXInstr_Acas(GXacas_FetchOr, r_old, - r_addr->GXam.IR.base, r_exp, - r_new, sz)); - } - else if((sz == 8 && cas->expdLo->Iex.Const.con->Ico.U64 == 5) || - (sz == 4 && cas->expdLo->Iex.Const.con->Ico.U32 == 5)) - { - addInstr(env, TILEGXInstr_Acas(GXacas_FetchAddgez, r_old, - r_addr->GXam.IR.base, r_exp, - r_new, sz)); - } - else - { - vassert(0); - } - } - return; - } - - /* --------- INSTR MARK --------- */ - /* Doesn't generate any executable code ... */ - case Ist_IMark: - return; - - /* --------- ABI HINT --------- */ - /* These have no meaning (denotation in the IR) and so we ignore - them ... if any actually made it this far. */ - case Ist_AbiHint: - return; - - /* --------- NO-OP --------- */ - /* Fairly self-explanatory, wouldn't you say? */ - case Ist_NoOp: - return; - - /* --------- EXIT --------- */ - case Ist_Exit: { - - TILEGXCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard); - TILEGXAMode* amPC = TILEGXAMode_IR(stmt->Ist.Exit.offsIP, - TILEGXGuestStatePointer()); - - /* Case: boring transfer to known address */ - if (stmt->Ist.Exit.jk == Ijk_Boring - || stmt->Ist.Exit.jk == Ijk_Call - /* || stmt->Ist.Exit.jk == Ijk_Ret */) { - if (env->chainingAllowed) { - /* .. almost always true .. */ - /* Skip the event check at the dst if this is a forwards - edge. */ - Bool toFastEP = - ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > ((Addr64)env->max_ga); - - if (0) vex_printf("%s", toFastEP ? "Y" : ","); - addInstr(env, TILEGXInstr_XDirect( - (Addr64)stmt->Ist.Exit.dst->Ico.U64, - amPC, cc, toFastEP)); - } else { - /* .. very occasionally .. */ - /* We can't use chaining, so ask for an assisted transfer, - as that's the only alternative that is allowable. */ - HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); - addInstr(env, TILEGXInstr_XAssisted(r, amPC, cc, Ijk_Boring)); - } - return; - } - - /* Case: assisted transfer to arbitrary address */ - switch (stmt->Ist.Exit.jk) { - /* Keep this list in sync with that in iselNext below */ - case Ijk_ClientReq: - case Ijk_EmFail: - case Ijk_EmWarn: - case Ijk_NoDecode: - case Ijk_NoRedir: - case Ijk_SigBUS: - case Ijk_Yield: - case Ijk_SigTRAP: - case Ijk_SigFPE_IntDiv: - case Ijk_SigFPE_IntOvf: - case Ijk_Sys_syscall: - case Ijk_InvalICache: - case Ijk_Ret: - { - HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); - addInstr(env, TILEGXInstr_XAssisted(r, amPC, cc, - stmt->Ist.Exit.jk)); - return; - } - default: - break; - } - - /* Do we ever expect to see any other kind? */ - goto stmt_fail; - } - - default: - break; - } - - stmt_fail: - vex_printf("stmt_fail tag: 0x%x\n", stmt->tag); - ppIRStmt(stmt); - vpanic("iselStmt:\n"); -} - -/*---------------------------------------------------------*/ -/*--- ISEL: Basic block terminators (Nexts) ---*/ -/*---------------------------------------------------------*/ - -static void iselNext ( ISelEnv * env, IRExpr * next, IRJumpKind jk, - Int offsIP ) -{ - - if (vex_traceflags & VEX_TRACE_VCODE) { - vex_printf("\n-- PUT(%d) = ", offsIP); - ppIRExpr(next); - vex_printf( "; exit-"); - ppIRJumpKind(jk); - vex_printf( "\n"); - } - - /* Case: boring transfer to known address */ - if (next->tag == Iex_Const) { - IRConst* cdst = next->Iex.Const.con; - if (jk == Ijk_Boring || jk == Ijk_Call) { - /* Boring transfer to known address */ - TILEGXAMode* amPC = TILEGXAMode_IR(offsIP, TILEGXGuestStatePointer()); - if (env->chainingAllowed) { - /* .. almost always true .. */ - /* Skip the event check at the dst if this is a forwards - edge. */ - Bool toFastEP = ((Addr64)cdst->Ico.U64) > ((Addr64)env->max_ga); - - if (0) vex_printf("%s", toFastEP ? "X" : "."); - addInstr(env, TILEGXInstr_XDirect((Addr64)cdst->Ico.U64, - amPC, TILEGXcc_AL, toFastEP)); - } else { - /* .. very occasionally .. */ - /* We can't use chaining, so ask for an assisted transfer, - as that's the only alternative that is allowable. */ - HReg r = iselWordExpr_R(env, next); - addInstr(env, TILEGXInstr_XAssisted(r, amPC, TILEGXcc_AL, - Ijk_Boring)); - } - return; - } - } - - /* Case: call/return (==boring) transfer to any address */ - switch (jk) { - case Ijk_Boring: case Ijk_Call: { - HReg r = iselWordExpr_R(env, next); - TILEGXAMode* amPC = TILEGXAMode_IR(offsIP, - TILEGXGuestStatePointer()); - if (env->chainingAllowed) - addInstr(env, TILEGXInstr_XIndir(r, amPC, TILEGXcc_AL)); - else - addInstr(env, TILEGXInstr_XAssisted(r, amPC, TILEGXcc_AL, - Ijk_Boring)); - return; - } - default: - break; - } - - /* Case: assisted transfer to arbitrary address */ - switch (jk) { - /* Keep this list in sync with that for Ist_Exit above */ - case Ijk_ClientReq: - case Ijk_EmFail: - case Ijk_EmWarn: - case Ijk_NoDecode: - case Ijk_NoRedir: - case Ijk_SigBUS: - case Ijk_SigILL: - case Ijk_SigTRAP: - case Ijk_SigFPE_IntDiv: - case Ijk_SigFPE_IntOvf: - case Ijk_Sys_syscall: - case Ijk_InvalICache: - case Ijk_Ret: { - HReg r = iselWordExpr_R(env, next); - TILEGXAMode* amPC = TILEGXAMode_IR(offsIP, TILEGXGuestStatePointer()); - addInstr(env, TILEGXInstr_XAssisted(r, amPC, TILEGXcc_AL, jk)); - return; - } - default: - break; - } - - vex_printf("\n-- PUT(%d) = ", offsIP); - ppIRExpr(next ); - vex_printf("; exit-"); - ppIRJumpKind(jk); - vex_printf("\n"); - vassert(0); /* are we expecting any other kind? */ -} - -/*---------------------------------------------------------*/ -/*--- Insn selector top-level ---*/ -/*---------------------------------------------------------*/ - -/* Translate an entire BB to tilegx code. */ -HInstrArray *iselSB_TILEGX ( const IRSB* bb, - VexArch arch_host, - const VexArchInfo* archinfo_host, - const VexAbiInfo* vbi, - Int offs_Host_EvC_Counter, - Int offs_Host_EvC_FailAddr, - Bool chainingAllowed, - Bool addProfInc, - Addr max_ga ) -{ - Int i, j; - HReg hreg; - ISelEnv *env; - UInt hwcaps_host = archinfo_host->hwcaps; - TILEGXAMode *amCounter, *amFailAddr; - - /* sanity ... */ - vassert(arch_host == VexArchTILEGX); - - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; - env->mode64 = True; - - /* Set up output code array. */ - env->code = newHInstrArray(); - - /* Copy BB's type env. */ - env->type_env = bb->tyenv; - - /* Make up an IRTemp -> virtual HReg mapping. This doesn't - change as we go along. */ - env->n_vregmap = bb->tyenv->types_used; - env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); - - /* and finally ... */ - env->hwcaps = hwcaps_host; - env->chainingAllowed = chainingAllowed; - env->hwcaps = hwcaps_host; - env->max_ga = max_ga; - - /* For each IR temporary, allocate a suitably-kinded virtual - register. */ - j = 0; - - for (i = 0; i < env->n_vregmap; i++) { - hreg = INVALID_HREG; - switch (bb->tyenv->types[i]) { - case Ity_I1: - case Ity_I8: - case Ity_I16: - case Ity_I32: - hreg = mkHReg(True, HRcInt64, 0, j++); - break; - case Ity_I64: - hreg = mkHReg(True, HRcInt64, 0, j++); - break; - default: - ppIRType(bb->tyenv->types[i]); - vpanic("iselBB(tilegx): IRTemp type"); - } - env->vregmap[i] = hreg; - } - env->vreg_ctr = j; - - /* The very first instruction must be an event check. */ - amCounter = TILEGXAMode_IR(offs_Host_EvC_Counter, - TILEGXGuestStatePointer()); - amFailAddr = TILEGXAMode_IR(offs_Host_EvC_FailAddr, - TILEGXGuestStatePointer()); - addInstr(env, TILEGXInstr_EvCheck(amCounter, amFailAddr)); - - /* Possibly a block counter increment (for profiling). At this - point we don't know the address of the counter, so just pretend - it is zero. It will have to be patched later, but before this - translation is used, by a call to LibVEX_patchProfCtr. */ - if (addProfInc) { - addInstr(env, TILEGXInstr_ProfInc()); - } - - /* Ok, finally we can iterate over the statements. */ - for (i = 0; i < bb->stmts_used; i++) - iselStmt(env, bb->stmts[i]); - - iselNext(env, bb->next, bb->jumpkind, bb->offsIP); - - /* record the number of vregs we used. */ - env->code->n_vregs = env->vreg_ctr; - return env->code; -} - -/*---------------------------------------------------------------*/ -/*--- end host_tilegx_isel.c ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index f88e006824..d4b142daf0 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -45,7 +45,6 @@ #include "libvex_guest_s390x.h" #include "libvex_guest_mips32.h" #include "libvex_guest_mips64.h" -#include "libvex_guest_tilegx.h" #include "main_globals.h" #include "main_util.h" @@ -59,7 +58,6 @@ #include "host_arm64_defs.h" #include "host_s390_defs.h" #include "host_mips_defs.h" -#include "host_tilegx_defs.h" #include "guest_generic_bb_to_IR.h" #include "guest_x86_defs.h" @@ -69,7 +67,6 @@ #include "guest_ppc_defs.h" #include "guest_s390_defs.h" #include "guest_mips_defs.h" -#include "guest_tilegx_defs.h" #include "host_generic_simd128.h" @@ -158,14 +155,6 @@ #define MIPS64ST(f) vassert(0) #endif -#if defined(VGA_tilegx) || defined(VEXMULTIARCH) -#define TILEGXFN(f) f -#define TILEGXST(f) f -#else -#define TILEGXFN(f) NULL -#define TILEGXST(f) vassert(0) -#endif - /* This file contains the top level interface to the library. */ @@ -529,24 +518,6 @@ IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs* vta, vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8); break; - case VexArchTILEGX: - preciseMemExnsFn = - TILEGXFN(guest_tilegx_state_requires_precise_mem_exns); - disInstrFn = TILEGXFN(disInstr_TILEGX); - specHelper = TILEGXFN(guest_tilegx_spechelper); - guest_layout = TILEGXFN(&tilegxGuest_layout); - offB_CMSTART = offsetof(VexGuestTILEGXState,guest_CMSTART); - offB_CMLEN = offsetof(VexGuestTILEGXState,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestTILEGXState,guest_pc); - szB_GUEST_IP = sizeof( ((VexGuestTILEGXState*)0)->guest_pc ); - vassert(vta->archinfo_guest.endness == VexEndnessLE); - vassert(0 == - sizeof(VexGuestTILEGXState) % LibVEX_GUEST_STATE_ALIGN); - vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_CMSTART ) == 8); - vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_CMLEN ) == 8); - vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_NRADDR ) == 8); - break; - default: vpanic("LibVEX_Translate: unsupported guest insn set"); } @@ -872,14 +843,6 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); break; - case VexArchTILEGX: - preciseMemExnsFn = - TILEGXFN(guest_tilegx_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestTILEGXState); - offB_HOST_EvC_COUNTER = offsetof(VexGuestTILEGXState,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestTILEGXState,host_EvC_FAILADDR); - break; - default: vpanic("LibVEX_Codegen: unsupported guest insn set"); } @@ -1037,22 +1000,6 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, || vta->archinfo_host.endness == VexEndnessBE); break; - case VexArchTILEGX: - mode64 = True; - rRegUniv = TILEGXFN(getRRegUniverse_TILEGX()); - isMove = CAST_TO_TYPEOF(isMove) TILEGXFN(isMove_TILEGXInstr); - getRegUsage = - CAST_TO_TYPEOF(getRegUsage) TILEGXFN(getRegUsage_TILEGXInstr); - mapRegs = CAST_TO_TYPEOF(mapRegs) TILEGXFN(mapRegs_TILEGXInstr); - genSpill = CAST_TO_TYPEOF(genSpill) TILEGXFN(genSpill_TILEGX); - genReload = CAST_TO_TYPEOF(genReload) TILEGXFN(genReload_TILEGX); - ppInstr = CAST_TO_TYPEOF(ppInstr) TILEGXFN(ppTILEGXInstr); - ppReg = CAST_TO_TYPEOF(ppReg) TILEGXFN(ppHRegTILEGX); - iselSB = TILEGXFN(iselSB_TILEGX); - emit = CAST_TO_TYPEOF(emit) TILEGXFN(emit_TILEGXInstr); - vassert(vta->archinfo_host.endness == VexEndnessLE); - break; - default: vpanic("LibVEX_Translate: unsupported host insn set"); } @@ -1283,12 +1230,6 @@ VexInvalRange LibVEX_Chain ( VexArch arch_host, place_to_chain, disp_cp_chain_me_EXPECTED, place_to_jump_to, True/*!mode64*/)); - - case VexArchTILEGX: - TILEGXST(return chainXDirect_TILEGX(endness_host, - place_to_chain, - disp_cp_chain_me_EXPECTED, - place_to_jump_to, True/*!mode64*/)); default: vassert(0); } @@ -1346,13 +1287,6 @@ VexInvalRange LibVEX_UnChain ( VexArch arch_host, place_to_unchain, place_to_jump_to_EXPECTED, disp_cp_chain_me, True/*!mode64*/)); - - case VexArchTILEGX: - TILEGXST(return unchainXDirect_TILEGX(endness_host, - place_to_unchain, - place_to_jump_to_EXPECTED, - disp_cp_chain_me, True/*!mode64*/)); - default: vassert(0); } @@ -1381,8 +1315,6 @@ Int LibVEX_evCheckSzB ( VexArch arch_host ) MIPS32ST(cached = evCheckSzB_MIPS()); break; case VexArchMIPS64: MIPS64ST(cached = evCheckSzB_MIPS()); break; - case VexArchTILEGX: - TILEGXST(cached = evCheckSzB_TILEGX()); break; default: vassert(0); } @@ -1423,10 +1355,6 @@ VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, case VexArchMIPS64: MIPS64ST(return patchProfInc_MIPS(endness_host, place_to_patch, location_of_counter, True/*!mode64*/)); - case VexArchTILEGX: - TILEGXST(return patchProfInc_TILEGX(endness_host, place_to_patch, - location_of_counter, - True/*!mode64*/)); default: vassert(0); } @@ -1506,7 +1434,6 @@ const HChar* LibVEX_ppVexArch ( VexArch arch ) case VexArchS390X: return "S390X"; case VexArchMIPS32: return "MIPS32"; case VexArchMIPS64: return "MIPS64"; - case VexArchTILEGX: return "TILEGX"; default: return "VexArch???"; } } @@ -1574,7 +1501,6 @@ static IRType arch_word_size (VexArch arch) { case VexArchMIPS64: case VexArchPPC64: case VexArchS390X: - case VexArchTILEGX: return Ity_I64; default: @@ -1871,11 +1797,6 @@ static const HChar* show_hwcaps_mips64 ( UInt hwcaps ) return "Unsupported baseline"; } -static const HChar* show_hwcaps_tilegx ( UInt hwcaps ) -{ - return "tilegx-baseline"; -} - #undef NUM_HWCAPS /* Thie function must not return NULL. */ @@ -1892,7 +1813,6 @@ static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) case VexArchS390X: return show_hwcaps_s390x(hwcaps); case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); - case VexArchTILEGX: return show_hwcaps_tilegx(hwcaps); default: return NULL; } } @@ -2116,9 +2036,6 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps ) invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n"); } - case VexArchTILEGX: - return; - default: vpanic("unknown architecture"); } diff --git a/VEX/priv/tilegx_disasm.c b/VEX/priv/tilegx_disasm.c deleted file mode 100644 index bbbfa27e0c..0000000000 --- a/VEX/priv/tilegx_disasm.c +++ /dev/null @@ -1,7694 +0,0 @@ - -/*---------------------------------------------------------------*/ -/*--- begin Tilegx disassembler tilegx-disasm.c ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright Tilera Corp. 2010-2013 - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - 02110-1301, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - - /* Contributed by Zhi-Gang Liu */ - -#include "tilegx_disasm.h" -#include - -/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ -#define BFD_RELOC(x) -1 - -/* Special registers. */ -#define TREG_LR 55 -#define TREG_SN 56 -#define TREG_ZERO 63 - -#ifndef NULL -#define NULL 0 -#endif - -const struct tilegx_opcode tilegx_opcodes[336] = -{ - { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffffffff80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a44ae00000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1, - { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00fffULL, - 0xfff807ff80000000ULL, - 0x0000000078000fffULL, - 0x3c0007ff80000000ULL, - 0ULL - }, - { - 0x0000000040300fffULL, - 0x181807ff80000000ULL, - 0x0000000010000fffULL, - 0x0c0007ff80000000ULL, - -1ULL - } -#endif - }, - { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, - { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc000000070000fffULL, - 0xf80007ff80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000070000fffULL, - 0x380007ff80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1858000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18a0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, - { { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0xfffff80000000000ULL, - 0x00000000780ff000ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - 0x000000005107f000ULL, - 0x283bf80000000000ULL, - 0x00000000500bf000ULL, - 0x2c05f80000000000ULL, - -1ULL - } -#endif - }, - { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, - { { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00fc0ULL, - 0xfff807e000000000ULL, - 0x0000000078000fc0ULL, - 0x3c0007e000000000ULL, - 0ULL - }, - { - 0x0000000040100fc0ULL, - 0x180807e000000000ULL, - 0x0000000000000fc0ULL, - 0x040007e000000000ULL, - -1ULL - } -#endif - }, - { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, - { { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc000000070000fc0ULL, - 0xf80007e000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000010000fc0ULL, - 0x000007e000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286a801f80000000ULL, - -1ULL, - -1ULL, - 0x41f8000004000000ULL - } -#endif - }, - { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8001f80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1840001f80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8001f80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1838001f80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8001f80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1850001f80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8001f80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1848001f80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8001f80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1860001f80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8001f80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1858001f80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286a801f80000000ULL, - -1ULL, - -1ULL, - 0x41f8000004000000ULL - } -#endif - }, - { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286a781f80000000ULL, - -1ULL, - -1ULL, - 0x41f8000000000000ULL - } -#endif - }, - { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286a901f80000000ULL, - -1ULL, - -1ULL, - 0x43f8000004000000ULL - } -#endif - }, - { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286a881f80000000ULL, - -1ULL, - -1ULL, - 0x43f8000000000000ULL - } -#endif - }, - { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286aa01f80000000ULL, - -1ULL, - -1ULL, - 0x83f8000000000000ULL - } -#endif - }, - { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff81f80000000ULL, - 0ULL, - 0ULL, - 0xc3f8000004000000ULL - }, - { - -1ULL, - 0x286a981f80000000ULL, - -1ULL, - -1ULL, - 0x81f8000004000000ULL - } -#endif - }, - { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffffffff80000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a44ae80000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x00000000500c0000ULL, - 0x2806000000000000ULL, - 0x0000000028040000ULL, - 0x1802000000000000ULL, - -1ULL - } -#endif - }, - { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0x0000000078000000ULL, - 0x3c00000000000000ULL, - 0ULL - }, - { - 0x0000000040100000ULL, - 0x1808000000000000ULL, - 0ULL, - 0x0400000000000000ULL, - -1ULL - } -#endif - }, - { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc000000070000000ULL, - 0xf800000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000010000000ULL, - 0ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050080000ULL, - 0x2804000000000000ULL, - 0x0000000028000000ULL, - 0x1800000000000000ULL, - -1ULL - } -#endif - }, - { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0x0000000078000000ULL, - 0x3c00000000000000ULL, - 0ULL - }, - { - 0x0000000040200000ULL, - 0x1810000000000000ULL, - 0x0000000008000000ULL, - 0x0800000000000000ULL, - -1ULL - } -#endif - }, - { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc000000070000000ULL, - 0xf800000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000020000000ULL, - 0x0800000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050040000ULL, - 0x2802000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050100000ULL, - 0x2808000000000000ULL, - 0x0000000050000000ULL, - 0x2c00000000000000ULL, - -1ULL - } -#endif - }, - { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0x0000000078000000ULL, - 0x3c00000000000000ULL, - 0ULL - }, - { - 0x0000000040300000ULL, - 0x1818000000000000ULL, - 0x0000000010000000ULL, - 0x0c00000000000000ULL, - -1ULL - } -#endif - }, - { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1440000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1400000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1, - { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007f000000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000034000000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1, - { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007f000000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000035000000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1, - { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007f000000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000036000000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x14c0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1480000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1540000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1500000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x15c0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1580000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1640000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1600000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x16c0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1680000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1740000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1700000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x17c0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xffc0000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1780000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, - { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051481000ULL, - -1ULL, - 0x00000000300c1000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050140000ULL, - -1ULL, - 0x0000000048000000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050180000ULL, - -1ULL, - 0x0000000048040000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x00000000501c0000ULL, - 0x280a000000000000ULL, - 0x0000000040000000ULL, - 0x2404000000000000ULL, - -1ULL - } -#endif - }, - { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0x0000000078000000ULL, - 0x3c00000000000000ULL, - 0ULL - }, - { - 0x0000000040400000ULL, - 0x1820000000000000ULL, - 0x0000000018000000ULL, - 0x1000000000000000ULL, - -1ULL - } -#endif - }, - { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x280e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x280c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050200000ULL, - 0x2810000000000000ULL, - 0x0000000038000000ULL, - 0x2000000000000000ULL, - -1ULL - } -#endif - }, - { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050240000ULL, - 0x2812000000000000ULL, - 0x0000000038040000ULL, - 0x2002000000000000ULL, - -1ULL - } -#endif - }, - { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050280000ULL, - 0x2814000000000000ULL, - 0x0000000038080000ULL, - 0x2004000000000000ULL, - -1ULL - } -#endif - }, - { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0x0000000078000000ULL, - 0x3c00000000000000ULL, - 0ULL - }, - { - 0x0000000040500000ULL, - 0x1828000000000000ULL, - 0x0000000020000000ULL, - 0x1400000000000000ULL, - -1ULL - } -#endif - }, - { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x00000000502c0000ULL, - 0x2816000000000000ULL, - 0x00000000380c0000ULL, - 0x2006000000000000ULL, - -1ULL - } -#endif - }, - { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040600000ULL, - 0x1830000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050300000ULL, - 0x2818000000000000ULL, - 0x0000000040040000ULL, - 0x2406000000000000ULL, - -1ULL - } -#endif - }, - { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000504c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050380000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050340000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050400000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000503c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050480000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050440000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050500000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050540000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, - { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051482000ULL, - -1ULL, - 0x00000000300c2000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050640000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050580000ULL, - 0x281a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000505c0000ULL, - 0x281c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050600000ULL, - 0x281e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a080000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a100000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2822000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2820000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000506c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050680000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050700000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050740000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050780000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000507c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050800000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050840000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x282a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2824000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2828000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2826000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x282e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x282c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2832000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2830000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a180000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a280000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a200000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, - { { }, { }, { }, { }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0xfffff80000000000ULL, - 0x00000000780ff000ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - 0x0000000051483000ULL, - 0x286a300000000000ULL, - 0x00000000300c3000ULL, - 0x1c06400000000000ULL, - -1ULL - } -#endif - }, - { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050880000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000508c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050900000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050940000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1, - { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051484000ULL, - -1ULL, - 0x00000000300c4000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050980000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000509c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a380000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1, - { { 0, }, { }, { 0, }, { }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - -1ULL, - 0x286a400000000000ULL, - -1ULL, - 0x1c06480000000000ULL, - -1ULL - } -#endif - }, - { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a480000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286a500000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfc00000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2400000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1, - { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfc00000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2000000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1, - { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - -1ULL, - 0x286a600000000000ULL, - -1ULL, - 0x1c06580000000000ULL, - -1ULL - } -#endif - }, - { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1, - { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - -1ULL, - 0x286a580000000000ULL, - -1ULL, - 0x1c06500000000000ULL, - -1ULL - } -#endif - }, - { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - -1ULL, - 0x286a700000000000ULL, - -1ULL, - 0x1c06680000000000ULL, - -1ULL - } -#endif - }, - { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - -1ULL, - 0x286a680000000000ULL, - -1ULL, - 0x1c06600000000000ULL, - -1ULL - } -#endif - }, - { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286ae80000000000ULL, - -1ULL, - -1ULL, - 0x8200000004000000ULL - } -#endif - }, - { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286a780000000000ULL, - -1ULL, - -1ULL, - 0x4000000000000000ULL - } -#endif - }, - { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1838000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286a800000000000ULL, - -1ULL, - -1ULL, - 0x4000000004000000ULL - } -#endif - }, - { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1840000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286a880000000000ULL, - -1ULL, - -1ULL, - 0x4200000000000000ULL - } -#endif - }, - { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1848000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286a900000000000ULL, - -1ULL, - -1ULL, - 0x4200000004000000ULL - } -#endif - }, - { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1850000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286a980000000000ULL, - -1ULL, - -1ULL, - 0x8000000004000000ULL - } -#endif - }, - { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1858000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x286aa00000000000ULL, - -1ULL, - -1ULL, - 0x8200000000000000ULL - } -#endif - }, - { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1860000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18a0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286aa80000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18a8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ae00000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ab00000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1868000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ab80000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1870000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ac00000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1878000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ac80000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1880000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ad00000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1888000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286ad80000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1890000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1898000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1, - { { 0, }, { 6 }, { 0, }, { 12 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - -1ULL, - 0x286af00000000000ULL, - -1ULL, - 0x1c06700000000000ULL, - -1ULL - } -#endif - }, - { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286af80000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 6, 27 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18b0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1, - { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007f000000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000037000000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050a00000ULL, - 0x2834000000000000ULL, - 0x0000000048080000ULL, - 0x2804000000000000ULL, - -1ULL - } -#endif - }, - { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 28, 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18b8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050d40000ULL, - -1ULL, - 0x0000000068000000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050d80000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050dc0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050e00000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050e40000ULL, - -1ULL, - 0x0000000068040000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050e80000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050ec0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050f00000ULL, - -1ULL, - 0x0000000068080000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050f40000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050f80000ULL, - -1ULL, - 0x00000000680c0000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050a80000ULL, - -1ULL, - 0x0000000070000000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050ac0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050b00000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050b40000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050b80000ULL, - -1ULL, - 0x0000000070040000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050bc0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050c00000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050c40000ULL, - -1ULL, - 0x0000000070080000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050c80000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050cc0000ULL, - -1ULL, - 0x00000000700c0000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050a40000ULL, - -1ULL, - 0x0000000040080000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0x00000000780c0000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000050d00000ULL, - -1ULL, - 0x00000000400c0000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000050fc0000ULL, - 0x2836000000000000ULL, - 0x00000000480c0000ULL, - 0x2806000000000000ULL, - -1ULL - } -#endif - }, - { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286b000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1, - { { }, { }, { }, { }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0xfffff80000000000ULL, - 0x00000000780ff000ULL, - 0x3c07f80000000000ULL, - 0ULL - }, - { - 0x0000000051485000ULL, - 0x286b080000000000ULL, - 0x00000000300c5000ULL, - 0x1c06780000000000ULL, - -1ULL - } -#endif - }, - { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051000000ULL, - 0x2838000000000000ULL, - 0x0000000050040000ULL, - 0x2c02000000000000ULL, - -1ULL - } -#endif - }, - { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051040000ULL, - 0x283a000000000000ULL, - 0x0000000050080000ULL, - 0x2c04000000000000ULL, - -1ULL - } -#endif - }, - { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040700000ULL, - 0x18c0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, - { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051486000ULL, - -1ULL, - 0x00000000300c6000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1, - { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051487000ULL, - -1ULL, - 0x00000000300c7000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1, - { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051488000ULL, - -1ULL, - 0x00000000300c8000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051080000ULL, - 0x283c000000000000ULL, - 0x0000000058000000ULL, - 0x3000000000000000ULL, - -1ULL - } -#endif - }, - { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000060040000ULL, - 0x3002000000000000ULL, - 0x0000000078000000ULL, - 0x3800000000000000ULL, - -1ULL - } -#endif - }, - { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051280000ULL, - 0x284c000000000000ULL, - 0x0000000058040000ULL, - 0x3002000000000000ULL, - -1ULL - } -#endif - }, - { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc000000070000000ULL, - 0xf800000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000070000000ULL, - 0x3800000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051100000ULL, - 0x2840000000000000ULL, - 0x0000000030000000ULL, - 0x1c00000000000000ULL, - -1ULL - } -#endif - }, - { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x00000000510c0000ULL, - 0x283e000000000000ULL, - 0x0000000060040000ULL, - 0x3402000000000000ULL, - -1ULL - } -#endif - }, - { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051180000ULL, - 0x2844000000000000ULL, - 0x0000000030040000ULL, - 0x1c02000000000000ULL, - -1ULL - } -#endif - }, - { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051140000ULL, - 0x2842000000000000ULL, - 0x0000000060080000ULL, - 0x3404000000000000ULL, - -1ULL - } -#endif - }, - { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051200000ULL, - 0x2848000000000000ULL, - 0x0000000030080000ULL, - 0x1c04000000000000ULL, - -1ULL - } -#endif - }, - { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x00000000511c0000ULL, - 0x2846000000000000ULL, - 0x00000000600c0000ULL, - 0x3406000000000000ULL, - -1ULL - } -#endif - }, - { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000060080000ULL, - 0x3004000000000000ULL, - 0x0000000078040000ULL, - 0x3802000000000000ULL, - -1ULL - } -#endif - }, - { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051240000ULL, - 0x284a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000600c0000ULL, - 0x3006000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x00000000512c0000ULL, - 0x284e000000000000ULL, - 0x0000000058080000ULL, - 0x3004000000000000ULL, - -1ULL - } -#endif - }, - { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000060100000ULL, - 0x3008000000000000ULL, - 0x0000000078080000ULL, - 0x3804000000000000ULL, - -1ULL - } -#endif - }, - { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051340000ULL, - 0x2852000000000000ULL, - 0x00000000580c0000ULL, - 0x3006000000000000ULL, - -1ULL - } -#endif - }, - { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000060140000ULL, - 0x300a000000000000ULL, - 0x00000000780c0000ULL, - 0x3806000000000000ULL, - -1ULL - } -#endif - }, - { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051300000ULL, - 0x2850000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000060180000ULL, - 0x300c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051380000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x2862000000000000ULL, - -1ULL, - -1ULL, - 0xc200000004000000ULL - } -#endif - }, - { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x2854000000000000ULL, - -1ULL, - -1ULL, - 0xc000000000000000ULL - } -#endif - }, - { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18c8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x2856000000000000ULL, - -1ULL, - -1ULL, - 0xc000000004000000ULL - } -#endif - }, - { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18d0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 14, 33 } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0xc200000004000000ULL - }, - { - -1ULL, - 0x2858000000000000ULL, - -1ULL, - -1ULL, - 0xc200000000000000ULL - } -#endif - }, - { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18d8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x1900000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x2860000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x285a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18e0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x285c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18e8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1, - { { 0, }, { 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x285e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18f0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1, - { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x18f8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051440000ULL, - 0x2868000000000000ULL, - 0x00000000280c0000ULL, - 0x1806000000000000ULL, - -1ULL - } -#endif - }, - { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000051400000ULL, - 0x2866000000000000ULL, - 0x0000000028080000ULL, - 0x1804000000000000ULL, - -1ULL - } -#endif - }, - { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000513c0000ULL, - 0x2864000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286b100000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286b180000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286b200000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, - { { 0, }, { }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286b280000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, - { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051489000ULL, - -1ULL, - 0x00000000300c9000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, - { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x000000005148a000ULL, - -1ULL, - 0x00000000300ca000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, - { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x000000005148b000ULL, - -1ULL, - 0x00000000300cb000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, - { { 23, 9 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffff000ULL, - 0ULL, - 0x00000000780ff000ULL, - 0ULL, - 0ULL - }, - { - 0x000000005148c000ULL, - -1ULL, - 0x00000000300cc000ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051500000ULL, - 0x286e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040800000ULL, - 0x1908000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000514c0000ULL, - 0x286c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051540000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051580000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000515c0000ULL, - 0x2870000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040900000ULL, - 0x1910000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051600000ULL, - 0x2872000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051640000ULL, - 0x2874000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051680000ULL, - 0x2876000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040a00000ULL, - 0x1918000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000516c0000ULL, - 0x2878000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040b00000ULL, - 0x1920000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051700000ULL, - 0x287a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052880000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052840000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051780000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051740000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051880000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000517c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052900000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000528c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051840000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051800000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000518c0000ULL, - 0x287c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051900000ULL, - 0x287e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051940000ULL, - 0x2880000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040c00000ULL, - 0x1928000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051980000ULL, - 0x2882000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040d00000ULL, - 0x1930000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000519c0000ULL, - 0x2884000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051a00000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051a80000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051a40000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051ac0000ULL, - 0x2886000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051b00000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051b40000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051b80000ULL, - 0x2888000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000601c0000ULL, - 0x300e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051bc0000ULL, - 0x288a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000060200000ULL, - 0x3010000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051c00000ULL, - 0x288c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000060240000ULL, - 0x3012000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051c80000ULL, - 0x2890000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051c40000ULL, - 0x288e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051d00000ULL, - 0x2894000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040e00000ULL, - 0x1938000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051cc0000ULL, - 0x2892000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051d40000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051d80000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051dc0000ULL, - 0x2896000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000040f00000ULL, - 0x1940000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051e00000ULL, - 0x2898000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051e40000ULL, - 0x289a000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051e80000ULL, - 0x289c000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000041000000ULL, - 0x1948000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051ec0000ULL, - 0x289e000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000041100000ULL, - 0x1950000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051f00000ULL, - 0x28a0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051f80000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051f40000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000051fc0000ULL, - 0x28a2000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052000000ULL, - 0x28a4000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052040000ULL, - 0x28a6000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000041200000ULL, - 0x1958000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052080000ULL, - 0x28a8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000041300000ULL, - 0x1960000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000520c0000ULL, - 0x28aa000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052100000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052140000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052180000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000521c0000ULL, - 0x28ac000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052200000ULL, - 0x28ae000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052240000ULL, - 0x28b0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052280000ULL, - 0x28b2000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000522c0000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1, - { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052300000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052340000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052380000ULL, - -1ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052400000ULL, - 0x28b6000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000060280000ULL, - 0x3014000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000523c0000ULL, - 0x28b4000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052440000ULL, - 0x28b8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000602c0000ULL, - 0x3016000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052480000ULL, - 0x28ba000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 29 }, { 6, 7, 30 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000060300000ULL, - 0x3018000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052500000ULL, - 0x28be000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000524c0000ULL, - 0x28bc000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052580000ULL, - 0x28c2000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052540000ULL, - 0x28c0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000525c0000ULL, - 0x28c4000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052600000ULL, - 0x28c6000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052640000ULL, - 0x28c8000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000526c0000ULL, - 0x28cc000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052680000ULL, - 0x28ca000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052700000ULL, - 0x28ce000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052740000ULL, - 0x28d0000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x00000000527c0000ULL, - 0x28d4000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000052780000ULL, - 0x28d2000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1, - { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0ULL, - 0xfffff80000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - -1ULL, - 0x286b300000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1, - { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ffc0000ULL, - 0xfffe000000000000ULL, - 0x00000000780c0000ULL, - 0x3c06000000000000ULL, - 0ULL - }, - { - 0x0000000052800000ULL, - 0x28d6000000000000ULL, - 0x00000000500c0000ULL, - 0x2c06000000000000ULL, - -1ULL - } -#endif - }, - { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1, - { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } }, -#ifndef DISASM_ONLY - { - 0xc00000007ff00000ULL, - 0xfff8000000000000ULL, - 0ULL, - 0ULL, - 0ULL - }, - { - 0x0000000041400000ULL, - 0x1968000000000000ULL, - -1ULL, - -1ULL, - -1ULL - } -#endif - }, - { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, -#ifndef DISASM_ONLY - { 0, }, { 0, } -#endif - } -}; -#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) -#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index)) - -static const UShort decode_X0_fsm[936] = -{ - BITFIELD(22, 9) /* index 0 */, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS, - TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU, - TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS, - TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM, - TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578), - CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671), - CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865), - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), - BITFIELD(6, 2) /* index 513 */, - TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518), - BITFIELD(8, 2) /* index 518 */, - TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523), - BITFIELD(10, 2) /* index 523 */, - TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI, - BITFIELD(20, 2) /* index 528 */, - TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548), - BITFIELD(6, 2) /* index 533 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538), - BITFIELD(8, 2) /* index 538 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543), - BITFIELD(10, 2) /* index 543 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, - BITFIELD(0, 2) /* index 548 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553), - BITFIELD(2, 2) /* index 553 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558), - BITFIELD(4, 2) /* index 558 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563), - BITFIELD(6, 2) /* index 563 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568), - BITFIELD(8, 2) /* index 568 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573), - BITFIELD(10, 2) /* index 573 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, - BITFIELD(20, 2) /* index 578 */, - TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI, - BITFIELD(20, 2) /* index 583 */, - TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI, - TILEGX_OPC_V1CMPLTUI, - BITFIELD(20, 2) /* index 588 */, - TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI, - TILEGX_OPC_V2CMPEQI, - BITFIELD(20, 2) /* index 593 */, - TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI, - TILEGX_OPC_V2MINSI, - BITFIELD(20, 2) /* index 598 */, - TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(18, 4) /* index 603 */, - TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD, - TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ, - TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, - TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR, - BITFIELD(18, 4) /* index 620 */, - TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL, - TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2, - TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN, - TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS, - TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1, - TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS, - BITFIELD(18, 4) /* index 637 */, - TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN, - TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2, - TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2, - TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX, - TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS, - TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS, - BITFIELD(18, 4) /* index 654 */, - TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU, - TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS, - TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU, - TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU, - TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU, - TILEGX_OPC_MZ, - BITFIELD(18, 4) /* index 671 */, - TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL, - TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES, - TILEGX_OPC_SUBXSC, - BITFIELD(12, 2) /* index 688 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693), - BITFIELD(14, 2) /* index 693 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698), - BITFIELD(16, 2) /* index 698 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, - BITFIELD(18, 4) /* index 703 */, - TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC, - TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU, - TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU, - TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE, - TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA, - BITFIELD(12, 4) /* index 720 */, - TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757), - CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787), - CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 737 */, - TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 742 */, - TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 747 */, - TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 752 */, - TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 757 */, - TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 762 */, - TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 767 */, - TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 772 */, - TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 777 */, - TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 782 */, - TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 787 */, - TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(16, 2) /* index 792 */, - TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(18, 4) /* index 797 */, - TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP, - TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU, - TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS, - TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU, - TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, - BITFIELD(18, 4) /* index 814 */, - TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, - TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS, - TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, - TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE, - TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H, - BITFIELD(18, 4) /* index 831 */, - TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, - TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ, - TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC, - TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS, - TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC, - BITFIELD(18, 4) /* index 848 */, - TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC, - TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H, - TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC, - TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC, - TILEGX_OPC_V4SUB, - BITFIELD(18, 3) /* index 865 */, - CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(21, 1) /* index 874 */, - TILEGX_OPC_XOR, TILEGX_OPC_NONE, - BITFIELD(21, 1) /* index 877 */, - TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE, - BITFIELD(21, 1) /* index 880 */, - TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE, - BITFIELD(21, 1) /* index 883 */, - TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE, - BITFIELD(21, 1) /* index 886 */, - TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE, - BITFIELD(18, 4) /* index 889 */, - TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI, - TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI, - TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI, - TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, - BITFIELD(0, 2) /* index 906 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(911), - BITFIELD(2, 2) /* index 911 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(916), - BITFIELD(4, 2) /* index 916 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(921), - BITFIELD(6, 2) /* index 921 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(926), - BITFIELD(8, 2) /* index 926 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(931), - BITFIELD(10, 2) /* index 931 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - TILEGX_OPC_INFOL, -}; - -static const UShort decode_X1_fsm[1266] = -{ - BITFIELD(53, 9) /* index 0 */, - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), - CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT, - TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT, - TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT, - TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT, - TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST, - TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT, - TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT, - TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT, - TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578), - CHILD(598), CHILD(703), CHILD(723), CHILD(728), CHILD(753), CHILD(758), - CHILD(763), CHILD(768), CHILD(773), CHILD(778), TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, - TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J, - TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, - TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, - TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, - TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, - TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, - TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, - CHILD(783), CHILD(800), CHILD(832), CHILD(849), CHILD(1168), CHILD(1185), - CHILD(1202), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1219), TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), CHILD(1236), - CHILD(1236), - BITFIELD(37, 2) /* index 513 */, - TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518), - BITFIELD(39, 2) /* index 518 */, - TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523), - BITFIELD(41, 2) /* index 523 */, - TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI, - BITFIELD(51, 2) /* index 528 */, - TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548), - BITFIELD(37, 2) /* index 533 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538), - BITFIELD(39, 2) /* index 538 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543), - BITFIELD(41, 2) /* index 543 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, - BITFIELD(31, 2) /* index 548 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553), - BITFIELD(33, 2) /* index 553 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558), - BITFIELD(35, 2) /* index 558 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563), - BITFIELD(37, 2) /* index 563 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568), - BITFIELD(39, 2) /* index 568 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573), - BITFIELD(41, 2) /* index 573 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, - BITFIELD(51, 2) /* index 578 */, - TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583), - BITFIELD(31, 2) /* index 583 */, - TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588), - BITFIELD(33, 2) /* index 588 */, - TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593), - BITFIELD(35, 2) /* index 593 */, - TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, - TILEGX_OPC_PREFETCH_ADD_L1_FAULT, - BITFIELD(51, 2) /* index 598 */, - CHILD(603), CHILD(618), CHILD(633), CHILD(648), - BITFIELD(31, 2) /* index 603 */, - TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608), - BITFIELD(33, 2) /* index 608 */, - TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613), - BITFIELD(35, 2) /* index 613 */, - TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, - TILEGX_OPC_PREFETCH_ADD_L1, - BITFIELD(31, 2) /* index 618 */, - TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623), - BITFIELD(33, 2) /* index 623 */, - TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628), - BITFIELD(35, 2) /* index 628 */, - TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, - TILEGX_OPC_PREFETCH_ADD_L2_FAULT, - BITFIELD(31, 2) /* index 633 */, - TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638), - BITFIELD(33, 2) /* index 638 */, - TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643), - BITFIELD(35, 2) /* index 643 */, - TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, - TILEGX_OPC_PREFETCH_ADD_L2, - BITFIELD(31, 2) /* index 648 */, - CHILD(653), CHILD(653), CHILD(653), CHILD(673), - BITFIELD(43, 2) /* index 653 */, - CHILD(658), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, - BITFIELD(45, 2) /* index 658 */, - CHILD(663), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, - BITFIELD(47, 2) /* index 663 */, - CHILD(668), TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, - BITFIELD(49, 2) /* index 668 */, - TILEGX_OPC_LD4S_TLS, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, - TILEGX_OPC_LD4S_ADD, - BITFIELD(33, 2) /* index 673 */, - CHILD(653), CHILD(653), CHILD(653), CHILD(678), - BITFIELD(35, 2) /* index 678 */, - CHILD(653), CHILD(653), CHILD(653), CHILD(683), - BITFIELD(43, 2) /* index 683 */, - CHILD(688), TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - BITFIELD(45, 2) /* index 688 */, - CHILD(693), TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - BITFIELD(47, 2) /* index 693 */, - CHILD(698), TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - BITFIELD(49, 2) /* index 698 */, - TILEGX_OPC_LD4S_TLS, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - BITFIELD(51, 2) /* index 703 */, - CHILD(708), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD, - TILEGX_OPC_LDNT2S_ADD, - BITFIELD(31, 2) /* index 708 */, - TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(713), - BITFIELD(33, 2) /* index 713 */, - TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(718), - BITFIELD(35, 2) /* index 718 */, - TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, - TILEGX_OPC_PREFETCH_ADD_L3, - BITFIELD(51, 2) /* index 723 */, - TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD, - TILEGX_OPC_LDNT_ADD, - BITFIELD(51, 2) /* index 728 */, - CHILD(733), TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR, - BITFIELD(43, 2) /* index 733 */, - CHILD(738), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, - BITFIELD(45, 2) /* index 738 */, - CHILD(743), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, - BITFIELD(47, 2) /* index 743 */, - CHILD(748), TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, - BITFIELD(49, 2) /* index 748 */, - TILEGX_OPC_LD_TLS, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, TILEGX_OPC_LD_ADD, - BITFIELD(51, 2) /* index 753 */, - TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD, - BITFIELD(51, 2) /* index 758 */, - TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD, - TILEGX_OPC_STNT_ADD, - BITFIELD(51, 2) /* index 763 */, - TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, - TILEGX_OPC_V1CMPLTSI, - BITFIELD(51, 2) /* index 768 */, - TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, - TILEGX_OPC_V2ADDI, - BITFIELD(51, 2) /* index 773 */, - TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, - TILEGX_OPC_V2MAXSI, - BITFIELD(51, 2) /* index 778 */, - TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(49, 4) /* index 783 */, - TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD, - TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH, - TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, - TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4, - TILEGX_OPC_DBLALIGN6, - BITFIELD(49, 4) /* index 800 */, - TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4, - TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD, - TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4, - TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR, - CHILD(817), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX, - BITFIELD(43, 2) /* index 817 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(822), - BITFIELD(45, 2) /* index 822 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(827), - BITFIELD(47, 2) /* index 827 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, - BITFIELD(49, 4) /* index 832 */, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL, - TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1, - TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2, - TILEGX_OPC_STNT4, - BITFIELD(46, 7) /* index 849 */, - TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, - TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, - TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, - TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC, - TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, - TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX, - TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, - TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, - TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, - TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(978), CHILD(987), - CHILD(1066), CHILD(1150), CHILD(1159), TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, - TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, - TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, - TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, - TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, - TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, - TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, - TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, - TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, - TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU, - TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, - TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, - TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, - TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, - TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, - TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, - TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, - TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE, - TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, - TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, - TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, - TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, - TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, - TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, - TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, - TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, - BITFIELD(43, 3) /* index 978 */, - TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV, - TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH, - BITFIELD(43, 3) /* index 987 */, - CHILD(996), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP, - TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(1051), - BITFIELD(31, 2) /* index 996 */, - CHILD(1001), CHILD(1026), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(33, 2) /* index 1001 */, - TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1006), - BITFIELD(35, 2) /* index 1006 */, - TILEGX_OPC_ILL, CHILD(1011), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(37, 2) /* index 1011 */, - TILEGX_OPC_ILL, CHILD(1016), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(39, 2) /* index 1016 */, - TILEGX_OPC_ILL, CHILD(1021), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(41, 2) /* index 1021 */, - TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL, - BITFIELD(33, 2) /* index 1026 */, - TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(1031), - BITFIELD(35, 2) /* index 1031 */, - TILEGX_OPC_ILL, CHILD(1036), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(37, 2) /* index 1036 */, - TILEGX_OPC_ILL, CHILD(1041), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(39, 2) /* index 1041 */, - TILEGX_OPC_ILL, CHILD(1046), TILEGX_OPC_ILL, TILEGX_OPC_ILL, - BITFIELD(41, 2) /* index 1046 */, - TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL, - BITFIELD(31, 2) /* index 1051 */, - TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1056), - BITFIELD(33, 2) /* index 1056 */, - TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1061), - BITFIELD(35, 2) /* index 1061 */, - TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, - TILEGX_OPC_PREFETCH_L1_FAULT, - BITFIELD(43, 3) /* index 1066 */, - CHILD(1075), CHILD(1090), CHILD(1105), CHILD(1120), CHILD(1135), - TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U, - BITFIELD(31, 2) /* index 1075 */, - TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1080), - BITFIELD(33, 2) /* index 1080 */, - TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1085), - BITFIELD(35, 2) /* index 1085 */, - TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH, - BITFIELD(31, 2) /* index 1090 */, - TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1095), - BITFIELD(33, 2) /* index 1095 */, - TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1100), - BITFIELD(35, 2) /* index 1100 */, - TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, - TILEGX_OPC_PREFETCH_L2_FAULT, - BITFIELD(31, 2) /* index 1105 */, - TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1110), - BITFIELD(33, 2) /* index 1110 */, - TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1115), - BITFIELD(35, 2) /* index 1115 */, - TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2, - BITFIELD(31, 2) /* index 1120 */, - TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1125), - BITFIELD(33, 2) /* index 1125 */, - TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1130), - BITFIELD(35, 2) /* index 1130 */, - TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, - TILEGX_OPC_PREFETCH_L3_FAULT, - BITFIELD(31, 2) /* index 1135 */, - TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1140), - BITFIELD(33, 2) /* index 1140 */, - TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1145), - BITFIELD(35, 2) /* index 1145 */, - TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3, - BITFIELD(43, 3) /* index 1150 */, - TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U, - TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF, - BITFIELD(43, 3) /* index 1159 */, - TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1, - TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE, - BITFIELD(49, 4) /* index 1168 */, - TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ, - TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, - TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ, - TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS, - TILEGX_OPC_V2CMPLTU, - BITFIELD(49, 4) /* index 1185 */, - TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L, - TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ, - TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC, - TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, - TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB, - BITFIELD(49, 4) /* index 1202 */, - TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H, - TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC, - TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC, - TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(49, 4) /* index 1219 */, - TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI, - TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI, - TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI, - TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, - BITFIELD(31, 2) /* index 1236 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(1241), - BITFIELD(33, 2) /* index 1241 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(1246), - BITFIELD(35, 2) /* index 1246 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(1251), - BITFIELD(37, 2) /* index 1251 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(1256), - BITFIELD(39, 2) /* index 1256 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - CHILD(1261), - BITFIELD(41, 2) /* index 1261 */, - TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, - TILEGX_OPC_INFOL, -}; - -static const UShort decode_Y0_fsm[178] = -{ - BITFIELD(27, 4) /* index 0 */, - CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI, - TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123), - CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168), - CHILD(173), - BITFIELD(6, 2) /* index 17 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22), - BITFIELD(8, 2) /* index 22 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27), - BITFIELD(10, 2) /* index 27 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, - BITFIELD(0, 2) /* index 32 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37), - BITFIELD(2, 2) /* index 37 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42), - BITFIELD(4, 2) /* index 42 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47), - BITFIELD(6, 2) /* index 47 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52), - BITFIELD(8, 2) /* index 52 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57), - BITFIELD(10, 2) /* index 57 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, - BITFIELD(18, 2) /* index 62 */, - TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, - BITFIELD(15, 5) /* index 67 */, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, - TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, - TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100), - CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(12, 3) /* index 100 */, - TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP, - TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT, - TILEGX_OPC_REVBITS, - BITFIELD(12, 3) /* index 109 */, - TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1, - TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - TILEGX_OPC_NONE, - BITFIELD(18, 2) /* index 118 */, - TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, - BITFIELD(18, 2) /* index 123 */, - TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX, - BITFIELD(18, 2) /* index 128 */, - TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, - BITFIELD(18, 2) /* index 133 */, - TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR, - BITFIELD(12, 2) /* index 138 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143), - BITFIELD(14, 2) /* index 143 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148), - BITFIELD(16, 2) /* index 148 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, - BITFIELD(18, 2) /* index 153 */, - TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU, - BITFIELD(18, 2) /* index 158 */, - TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX, - TILEGX_OPC_SHL3ADDX, - BITFIELD(18, 2) /* index 163 */, - TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS, - TILEGX_OPC_MUL_LU_LU, - BITFIELD(18, 2) /* index 168 */, - TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS, - TILEGX_OPC_MULA_LU_LU, - BITFIELD(18, 2) /* index 173 */, - TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, -}; - -static const UShort decode_Y1_fsm[167] = -{ - BITFIELD(58, 4) /* index 0 */, - TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI, - TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122), - CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE, - BITFIELD(37, 2) /* index 17 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22), - BITFIELD(39, 2) /* index 22 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27), - BITFIELD(41, 2) /* index 27 */, - TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, - BITFIELD(31, 2) /* index 32 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37), - BITFIELD(33, 2) /* index 37 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42), - BITFIELD(35, 2) /* index 42 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47), - BITFIELD(37, 2) /* index 47 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52), - BITFIELD(39, 2) /* index 52 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57), - BITFIELD(41, 2) /* index 57 */, - TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, - BITFIELD(49, 2) /* index 62 */, - TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, - BITFIELD(47, 4) /* index 67 */, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, - TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, - TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84), - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, - BITFIELD(43, 3) /* index 84 */, - CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108), - CHILD(111), CHILD(114), - BITFIELD(46, 1) /* index 93 */, - TILEGX_OPC_NONE, TILEGX_OPC_FNOP, - BITFIELD(46, 1) /* index 96 */, - TILEGX_OPC_NONE, TILEGX_OPC_ILL, - BITFIELD(46, 1) /* index 99 */, - TILEGX_OPC_NONE, TILEGX_OPC_JALRP, - BITFIELD(46, 1) /* index 102 */, - TILEGX_OPC_NONE, TILEGX_OPC_JALR, - BITFIELD(46, 1) /* index 105 */, - TILEGX_OPC_NONE, TILEGX_OPC_JRP, - BITFIELD(46, 1) /* index 108 */, - TILEGX_OPC_NONE, TILEGX_OPC_JR, - BITFIELD(46, 1) /* index 111 */, - TILEGX_OPC_NONE, TILEGX_OPC_LNK, - BITFIELD(46, 1) /* index 114 */, - TILEGX_OPC_NONE, TILEGX_OPC_NOP, - BITFIELD(49, 2) /* index 117 */, - TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, - BITFIELD(49, 2) /* index 122 */, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, - BITFIELD(49, 2) /* index 127 */, - TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, - BITFIELD(49, 2) /* index 132 */, - TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR, - BITFIELD(43, 2) /* index 137 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142), - BITFIELD(45, 2) /* index 142 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147), - BITFIELD(47, 2) /* index 147 */, - TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, - BITFIELD(49, 2) /* index 152 */, - TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU, - BITFIELD(49, 2) /* index 157 */, - TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX, - TILEGX_OPC_SHL3ADDX, - BITFIELD(49, 2) /* index 162 */, - TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, -}; - -static const UShort decode_Y2_fsm[118] = -{ - BITFIELD(62, 2) /* index 0 */, - TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109), - BITFIELD(55, 3) /* index 5 */, - CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40), - CHILD(43), - BITFIELD(26, 1) /* index 14 */, - TILEGX_OPC_LD1S, TILEGX_OPC_LD1U, - BITFIELD(26, 1) /* index 17 */, - CHILD(20), CHILD(30), - BITFIELD(51, 2) /* index 20 */, - TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25), - BITFIELD(53, 2) /* index 25 */, - TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, - TILEGX_OPC_PREFETCH_L1_FAULT, - BITFIELD(51, 2) /* index 30 */, - TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35), - BITFIELD(53, 2) /* index 35 */, - TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH, - BITFIELD(26, 1) /* index 40 */, - TILEGX_OPC_LD2S, TILEGX_OPC_LD2U, - BITFIELD(26, 1) /* index 43 */, - CHILD(46), CHILD(56), - BITFIELD(51, 2) /* index 46 */, - TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51), - BITFIELD(53, 2) /* index 51 */, - TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, - TILEGX_OPC_PREFETCH_L2_FAULT, - BITFIELD(51, 2) /* index 56 */, - TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61), - BITFIELD(53, 2) /* index 61 */, - TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2, - BITFIELD(56, 2) /* index 66 */, - CHILD(71), CHILD(74), CHILD(90), CHILD(93), - BITFIELD(26, 1) /* index 71 */, - TILEGX_OPC_NONE, TILEGX_OPC_LD4S, - BITFIELD(26, 1) /* index 74 */, - TILEGX_OPC_NONE, CHILD(77), - BITFIELD(51, 2) /* index 77 */, - TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82), - BITFIELD(53, 2) /* index 82 */, - TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87), - BITFIELD(55, 1) /* index 87 */, - TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT, - BITFIELD(26, 1) /* index 90 */, - TILEGX_OPC_LD4U, TILEGX_OPC_LD, - BITFIELD(26, 1) /* index 93 */, - CHILD(96), TILEGX_OPC_LD, - BITFIELD(51, 2) /* index 96 */, - TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101), - BITFIELD(53, 2) /* index 101 */, - TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106), - BITFIELD(55, 1) /* index 106 */, - TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3, - BITFIELD(26, 1) /* index 109 */, - CHILD(112), CHILD(115), - BITFIELD(57, 1) /* index 112 */, - TILEGX_OPC_ST1, TILEGX_OPC_ST4, - BITFIELD(57, 1) /* index 115 */, - TILEGX_OPC_ST2, TILEGX_OPC_ST, -}; - -#undef BITFIELD -#undef CHILD -const UShort * const -tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] = -{ - decode_X0_fsm, - decode_X1_fsm, - decode_Y0_fsm, - decode_Y1_fsm, - decode_Y2_fsm -}; -const struct tilegx_operand tilegx_operands[35] = -{ - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0), - 8, 1, 0, 0, 0, 0, - create_Imm8_X0, get_Imm8_X0 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1), - 8, 1, 0, 0, 0, 0, - create_Imm8_X1, get_Imm8_X1 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0), - 8, 1, 0, 0, 0, 0, - create_Imm8_Y0, get_Imm8_Y0 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1), - 8, 1, 0, 0, 0, 0, - create_Imm8_Y1, get_Imm8_Y1 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST), - 16, 1, 0, 0, 0, 0, - create_Imm16_X0, get_Imm16_X0 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST), - 16, 1, 0, 0, 0, 0, - create_Imm16_X1, get_Imm16_X1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 0, 1, 0, 0, - create_Dest_X1, get_Dest_X1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcA_X1, get_SrcA_X1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 0, 1, 0, 0, - create_Dest_X0, get_Dest_X0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcA_X0, get_SrcA_X0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 0, 1, 0, 0, - create_Dest_Y0, get_Dest_Y0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcA_Y0, get_SrcA_Y0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 0, 1, 0, 0, - create_Dest_Y1, get_Dest_Y1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcA_Y1, get_SrcA_Y1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcA_Y2, get_SrcA_Y2 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 1, 0, 0, - create_SrcA_X1, get_SrcA_X1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcB_X0, get_SrcB_X0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcB_X1, get_SrcB_X1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcB_Y0, get_SrcB_Y0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcB_Y1, get_SrcB_Y1 - }, - { - TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1), - 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, - create_BrOff_X1, get_BrOff_X1 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0), - 6, 0, 0, 0, 0, 0, - create_BFStart_X0, get_BFStart_X0 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0), - 6, 0, 0, 0, 0, 0, - create_BFEnd_X0, get_BFEnd_X0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 1, 0, 0, - create_Dest_X0, get_Dest_X0 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 1, 0, 0, - create_Dest_Y0, get_Dest_Y0 - }, - { - TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1), - 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, - create_JumpOff_X1, get_JumpOff_X1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 0, 1, 0, 0, - create_SrcBDest_Y2, get_SrcBDest_Y2 - }, - { - TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1), - 14, 0, 0, 0, 0, 0, - create_MF_Imm14_X1, get_MF_Imm14_X1 - }, - { - TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1), - 14, 0, 0, 0, 0, 0, - create_MT_Imm14_X1, get_MT_Imm14_X1 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0), - 6, 0, 0, 0, 0, 0, - create_ShAmt_X0, get_ShAmt_X0 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1), - 6, 0, 0, 0, 0, 0, - create_ShAmt_X1, get_ShAmt_X1 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0), - 6, 0, 0, 0, 0, 0, - create_ShAmt_Y0, get_ShAmt_Y0 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1), - 6, 0, 0, 0, 0, 0, - create_ShAmt_Y1, get_ShAmt_Y1 - }, - { - TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), - 6, 0, 1, 0, 0, 0, - create_SrcBDest_Y2, get_SrcBDest_Y2 - }, - { - TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1), - 8, 1, 0, 0, 0, 0, - create_Dest_Imm8_X1, get_Dest_Imm8_X1 - } -}; - - -/* Given a set of bundle bits and a specific pipe, returns which - * instruction the bundle contains in that pipe. - */ -const struct tilegx_opcode * -find_opcode ( tilegx_bundle_bits bits, tilegx_pipeline pipe ) -{ - const UShort *table = tilegx_bundle_decoder_fsms[pipe]; - Int index = 0; - - while (1) - { - UShort bitspec = table[index]; - UInt bitfield = - ((UInt)(bits >> (bitspec & 63))) & (bitspec >> 6); - - UShort next = table[index + 1 + bitfield]; - if (next <= TILEGX_OPC_NONE) - return &tilegx_opcodes[next]; - - index = next - TILEGX_OPC_NONE; - } -} - - -int -parse_insn_tilegx ( tilegx_bundle_bits bits, - ULong pc, - struct tilegx_decoded_instruction - decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE] ) -{ - Int num_instructions = 0; - Int pipe; - - Int min_pipe, max_pipe; - if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0) - { - min_pipe = TILEGX_PIPELINE_X0; - max_pipe = TILEGX_PIPELINE_X1; - } - else - { - min_pipe = TILEGX_PIPELINE_Y0; - max_pipe = TILEGX_PIPELINE_Y2; - } - - /* For each pipe, find an instruction that fits. */ - for (pipe = min_pipe; pipe <= max_pipe; pipe++) - { - const struct tilegx_opcode *opc; - struct tilegx_decoded_instruction *d; - Int i; - - d = &decoded[num_instructions++]; - opc = find_opcode (bits, (tilegx_pipeline)pipe); - d->opcode = opc; - - /* Decode each operand, sign extending, etc. as appropriate. */ - for (i = 0; i < opc->num_operands; i++) - { - const struct tilegx_operand *op = - &tilegx_operands[opc->operands[pipe][i]]; - Int raw_opval = op->extract (bits); - Long opval; - - if (op->is_signed) - { - /* Sign-extend the operand. */ - Int shift = (int)((sizeof(int) * 8) - op->num_bits); - raw_opval = (raw_opval << shift) >> shift; - } - - /* Adjust PC-relative scaled branch offsets. */ - if (op->type == TILEGX_OP_TYPE_ADDRESS) - opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc; - else - opval = raw_opval; - - /* Record the final value. */ - d->operands[i] = op; - d->operand_values[i] = opval; - } - } - decoded[num_instructions].opcode = NULL; - return num_instructions; -} - -tilegx_bundle_bits mkTileGxInsn ( Int opc, Int argc, ... ) -{ - struct tilegx_decoded_instruction decoded; - decoded.opcode = &tilegx_opcodes[opc]; - Int i; - va_list argv; - - if (decoded.opcode->num_operands != argc) - return -1; - - if (opc > TILEGX_OPC_NONE) return 0; - - if (decoded.opcode->num_operands > 4) - return -1; - - va_start(argv, argc); - for (i = 0 ; i < decoded.opcode->num_operands; i++) - { - decoded.operands[i] = 0; - decoded.operand_values[i] = va_arg(argv, ULong); - } - va_end(argv); - - return encode_insn_tilegx(decoded); -} - -tilegx_bundle_bits -encode_insn_tilegx ( struct tilegx_decoded_instruction decoded ) -{ - const struct tilegx_opcode *opc = - decoded.opcode; - - tilegx_bundle_bits insn = 0; - Int pipeX01 = (opc->pipes & 0x01) ? 0 : 1; - Int op_num = opc->num_operands; - - /* Assume either X0 or X1. */ - if ((opc->pipes & 3) == 0) - return -1; - - /* Insert fnop in other pipe. */ - insn = tilegx_opcodes[TILEGX_OPC_FNOP]. - fixed_bit_values[pipeX01 ? 0 : 1]; - - insn |= opc->fixed_bit_values[pipeX01]; - - Int i; - /* loop for each operand. */ - for (i = 0 ; i < op_num; i++) - { - const struct tilegx_operand *opd = - &tilegx_operands[opc->operands[pipeX01][i]]; - Long op = decoded.operand_values[i]; - decoded.operands[i] = opd; - ULong x = opd->insert(op); - insn |= x; - } - - return insn; -} - -/*---------------------------------------------------------------*/ -/*--- end tilegx_disasm.c ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/priv/tilegx_disasm.h b/VEX/priv/tilegx_disasm.h deleted file mode 100644 index 701e3c503e..0000000000 --- a/VEX/priv/tilegx_disasm.h +++ /dev/null @@ -1,1306 +0,0 @@ - -/*---------------------------------------------------------------*/ -/*--- begin Tilegx disassembler tilegx-disasm.h ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright Tilera Corp. 2010-2013 - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - 02110-1301, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - - /* Contributed by Zhi-Gang Liu */ - -#ifndef __TILEGX_DISASM_H -#define __TILEGX_DISASM_H - -#include "libvex_basictypes.h" - -typedef ULong tilegx_bundle_bits; - -/* These are the bits that determine if a bundle is in the X encoding. */ -#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) - -enum -{ - /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ - TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, - - /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ - TILEGX_NUM_PIPELINE_ENCODINGS = 5, - - /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ - TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, - - /* Instructions take this many bytes. */ - TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, - - /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ - TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, - - /* Bundles should be aligned modulo this number of bytes. */ - TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = - (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), - - /* Number of registers (some are magic, such as network I/O). */ - TILEGX_NUM_REGISTERS = 64, -}; - -/* Make a few "tile_" variables to simplify common code between - architectures. */ - -typedef tilegx_bundle_bits tile_bundle_bits; -#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES -#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES -#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ - TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES - -/* 64-bit pattern for a { bpt ; nop } bundle. */ -#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL - -static __inline UInt -get_BFEnd_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_BFOpcodeExtension_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 24)) & 0xf); -} - -static __inline UInt -get_BFStart_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 18)) & 0x3f); -} - -static __inline UInt -get_BrOff_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 31)) & 0x0000003f) | - (((UInt)(n >> 37)) & 0x0001ffc0); -} - -static __inline UInt -get_BrType_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 54)) & 0x1f); -} - -static __inline UInt -get_Dest_Imm8_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 31)) & 0x0000003f) | - (((UInt)(n >> 43)) & 0x000000c0); -} - -static __inline UInt -get_Dest_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 0)) & 0x3f); -} - -static __inline UInt -get_Dest_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 31)) & 0x3f); -} - -static __inline UInt -get_Dest_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 0)) & 0x3f); -} - -static __inline UInt -get_Dest_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 31)) & 0x3f); -} - -static __inline UInt -get_Imm16_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0xffff); -} - -static __inline UInt -get_Imm16_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0xffff); -} - -static __inline UInt -get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 20)) & 0xff); -} - -static __inline UInt -get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 51)) & 0xff); -} - -static __inline UInt -get_Imm8_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0xff); -} - -static __inline UInt -get_Imm8_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0xff); -} - -static __inline UInt -get_Imm8_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0xff); -} - -static __inline UInt -get_Imm8_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0xff); -} - -static __inline UInt -get_JumpOff_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 31)) & 0x7ffffff); -} - -static __inline UInt -get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 58)) & 0x1); -} - -static __inline UInt -get_MF_Imm14_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 37)) & 0x3fff); -} - -static __inline UInt -get_MT_Imm14_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 31)) & 0x0000003f) | - (((UInt)(n >> 37)) & 0x00003fc0); -} - -static __inline UInt -get_Mode(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 62)) & 0x3); -} - -static __inline UInt -get_Opcode_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 28)) & 0x7); -} - -static __inline UInt -get_Opcode_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 59)) & 0x7); -} - -static __inline UInt -get_Opcode_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 27)) & 0xf); -} - -static __inline UInt -get_Opcode_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 58)) & 0xf); -} - -static __inline UInt -get_Opcode_Y2(tilegx_bundle_bits n) -{ - return (((n >> 26)) & 0x00000001) | - (((UInt)(n >> 56)) & 0x00000002); -} - -static __inline UInt -get_RRROpcodeExtension_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 18)) & 0x3ff); -} - -static __inline UInt -get_RRROpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 49)) & 0x3ff); -} - -static __inline UInt -get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 18)) & 0x3); -} - -static __inline UInt -get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 49)) & 0x3); -} - -static __inline UInt -get_ShAmt_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_ShAmt_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0x3f); -} - -static __inline UInt -get_ShAmt_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_ShAmt_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0x3f); -} - -static __inline UInt -get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 18)) & 0x3ff); -} - -static __inline UInt -get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 49)) & 0x3ff); -} - -static __inline UInt -get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 18)) & 0x3); -} - -static __inline UInt -get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 49)) & 0x3); -} - -static __inline UInt -get_SrcA_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 6)) & 0x3f); -} - -static __inline UInt -get_SrcA_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 37)) & 0x3f); -} - -static __inline UInt -get_SrcA_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 6)) & 0x3f); -} - -static __inline UInt -get_SrcA_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 37)) & 0x3f); -} - -static __inline UInt -get_SrcA_Y2(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 20)) & 0x3f); -} - -static __inline UInt -get_SrcBDest_Y2(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 51)) & 0x3f); -} - -static __inline UInt -get_SrcB_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_SrcB_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0x3f); -} - -static __inline UInt -get_SrcB_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_SrcB_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0x3f); -} - -static __inline UInt -get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0x3f); -} - -static __inline UInt -get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) -{ - const UInt n = (UInt)num; - return (((n >> 12)) & 0x3f); -} - -static __inline UInt -get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) -{ - return (((UInt)(n >> 43)) & 0x3f); -} - - -static __inline int -sign_extend(int n, int num_bits) -{ - int shift = (int)(sizeof(int) * 8 - num_bits); - return (n << shift) >> shift; -} - - - -static __inline tilegx_bundle_bits -create_BFEnd_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_BFOpcodeExtension_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0xf) << 24); -} - -static __inline tilegx_bundle_bits -create_BFStart_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 18); -} - -static __inline tilegx_bundle_bits -create_BrOff_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); -} - -static __inline tilegx_bundle_bits -create_BrType_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x1f)) << 54); -} - -static __inline tilegx_bundle_bits -create_Dest_Imm8_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); -} - -static __inline tilegx_bundle_bits -create_Dest_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 0); -} - -static __inline tilegx_bundle_bits -create_Dest_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 31); -} - -static __inline tilegx_bundle_bits -create_Dest_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 0); -} - -static __inline tilegx_bundle_bits -create_Dest_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 31); -} - -static __inline tilegx_bundle_bits -create_Imm16_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0xffff) << 12); -} - -static __inline tilegx_bundle_bits -create_Imm16_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0xffff)) << 43); -} - -static __inline tilegx_bundle_bits -create_Imm8OpcodeExtension_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0xff) << 20); -} - -static __inline tilegx_bundle_bits -create_Imm8OpcodeExtension_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0xff)) << 51); -} - -static __inline tilegx_bundle_bits -create_Imm8_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0xff) << 12); -} - -static __inline tilegx_bundle_bits -create_Imm8_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0xff)) << 43); -} - -static __inline tilegx_bundle_bits -create_Imm8_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0xff) << 12); -} - -static __inline tilegx_bundle_bits -create_Imm8_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0xff)) << 43); -} - -static __inline tilegx_bundle_bits -create_JumpOff_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); -} - -static __inline tilegx_bundle_bits -create_JumpOpcodeExtension_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x1)) << 58); -} - -static __inline tilegx_bundle_bits -create_MF_Imm14_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); -} - -static __inline tilegx_bundle_bits -create_MT_Imm14_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | - (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); -} - -static __inline tilegx_bundle_bits -create_Mode(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3)) << 62); -} - -static __inline tilegx_bundle_bits -create_Opcode_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x7) << 28); -} - -static __inline tilegx_bundle_bits -create_Opcode_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x7)) << 59); -} - -static __inline tilegx_bundle_bits -create_Opcode_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0xf) << 27); -} - -static __inline tilegx_bundle_bits -create_Opcode_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0xf)) << 58); -} - -static __inline tilegx_bundle_bits -create_Opcode_Y2(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x00000001) << 26) | - (((tilegx_bundle_bits)(n & 0x00000002)) << 56); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3ff) << 18); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3) << 18); -} - -static __inline tilegx_bundle_bits -create_RRROpcodeExtension_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3)) << 49); -} - -static __inline tilegx_bundle_bits -create_ShAmt_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_ShAmt_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_ShAmt_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_ShAmt_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3ff) << 18); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3) << 18); -} - -static __inline tilegx_bundle_bits -create_ShiftOpcodeExtension_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3)) << 49); -} - -static __inline tilegx_bundle_bits -create_SrcA_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 6); -} - -static __inline tilegx_bundle_bits -create_SrcA_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 37); -} - -static __inline tilegx_bundle_bits -create_SrcA_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 6); -} - -static __inline tilegx_bundle_bits -create_SrcA_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 37); -} - -static __inline tilegx_bundle_bits -create_SrcA_Y2(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 20); -} - -static __inline tilegx_bundle_bits -create_SrcBDest_Y2(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 51); -} - -static __inline tilegx_bundle_bits -create_SrcB_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_SrcB_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_SrcB_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_SrcB_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_X0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_X1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_Y0(int num) -{ - const UInt n = (UInt)num; - return ((n & 0x3f) << 12); -} - -static __inline tilegx_bundle_bits -create_UnaryOpcodeExtension_Y1(int num) -{ - const UInt n = (UInt)num; - return (((tilegx_bundle_bits)(n & 0x3f)) << 43); -} - -enum -{ - TILEGX_MAX_OPERANDS = 4 /* bfexts */ -}; - -typedef enum -{ - TILEGX_OPC_BPT, - TILEGX_OPC_INFO, - TILEGX_OPC_INFOL, - TILEGX_OPC_LD4S_TLS, - TILEGX_OPC_LD_TLS, - TILEGX_OPC_MOVE, - TILEGX_OPC_MOVEI, - TILEGX_OPC_MOVELI, - TILEGX_OPC_PREFETCH, - TILEGX_OPC_PREFETCH_ADD_L1, - TILEGX_OPC_PREFETCH_ADD_L1_FAULT, - TILEGX_OPC_PREFETCH_ADD_L2, - TILEGX_OPC_PREFETCH_ADD_L2_FAULT, - TILEGX_OPC_PREFETCH_ADD_L3, - TILEGX_OPC_PREFETCH_ADD_L3_FAULT, - TILEGX_OPC_PREFETCH_L1, - TILEGX_OPC_PREFETCH_L1_FAULT, - TILEGX_OPC_PREFETCH_L2, - TILEGX_OPC_PREFETCH_L2_FAULT, - TILEGX_OPC_PREFETCH_L3, - TILEGX_OPC_PREFETCH_L3_FAULT, - TILEGX_OPC_RAISE, - TILEGX_OPC_ADD, - TILEGX_OPC_ADDI, - TILEGX_OPC_ADDLI, - TILEGX_OPC_ADDX, - TILEGX_OPC_ADDXI, - TILEGX_OPC_ADDXLI, - TILEGX_OPC_ADDXSC, - TILEGX_OPC_AND, - TILEGX_OPC_ANDI, - TILEGX_OPC_BEQZ, - TILEGX_OPC_BEQZT, - TILEGX_OPC_BFEXTS, - TILEGX_OPC_BFEXTU, - TILEGX_OPC_BFINS, - TILEGX_OPC_BGEZ, - TILEGX_OPC_BGEZT, - TILEGX_OPC_BGTZ, - TILEGX_OPC_BGTZT, - TILEGX_OPC_BLBC, - TILEGX_OPC_BLBCT, - TILEGX_OPC_BLBS, - TILEGX_OPC_BLBST, - TILEGX_OPC_BLEZ, - TILEGX_OPC_BLEZT, - TILEGX_OPC_BLTZ, - TILEGX_OPC_BLTZT, - TILEGX_OPC_BNEZ, - TILEGX_OPC_BNEZT, - TILEGX_OPC_CLZ, - TILEGX_OPC_CMOVEQZ, - TILEGX_OPC_CMOVNEZ, - TILEGX_OPC_CMPEQ, - TILEGX_OPC_CMPEQI, - TILEGX_OPC_CMPEXCH, - TILEGX_OPC_CMPEXCH4, - TILEGX_OPC_CMPLES, - TILEGX_OPC_CMPLEU, - TILEGX_OPC_CMPLTS, - TILEGX_OPC_CMPLTSI, - TILEGX_OPC_CMPLTU, - TILEGX_OPC_CMPLTUI, - TILEGX_OPC_CMPNE, - TILEGX_OPC_CMUL, - TILEGX_OPC_CMULA, - TILEGX_OPC_CMULAF, - TILEGX_OPC_CMULF, - TILEGX_OPC_CMULFR, - TILEGX_OPC_CMULH, - TILEGX_OPC_CMULHR, - TILEGX_OPC_CRC32_32, - TILEGX_OPC_CRC32_8, - TILEGX_OPC_CTZ, - TILEGX_OPC_DBLALIGN, - TILEGX_OPC_DBLALIGN2, - TILEGX_OPC_DBLALIGN4, - TILEGX_OPC_DBLALIGN6, - TILEGX_OPC_DRAIN, - TILEGX_OPC_DTLBPR, - TILEGX_OPC_EXCH, - TILEGX_OPC_EXCH4, - TILEGX_OPC_FDOUBLE_ADD_FLAGS, - TILEGX_OPC_FDOUBLE_ADDSUB, - TILEGX_OPC_FDOUBLE_MUL_FLAGS, - TILEGX_OPC_FDOUBLE_PACK1, - TILEGX_OPC_FDOUBLE_PACK2, - TILEGX_OPC_FDOUBLE_SUB_FLAGS, - TILEGX_OPC_FDOUBLE_UNPACK_MAX, - TILEGX_OPC_FDOUBLE_UNPACK_MIN, - TILEGX_OPC_FETCHADD, - TILEGX_OPC_FETCHADD4, - TILEGX_OPC_FETCHADDGEZ, - TILEGX_OPC_FETCHADDGEZ4, - TILEGX_OPC_FETCHAND, - TILEGX_OPC_FETCHAND4, - TILEGX_OPC_FETCHOR, - TILEGX_OPC_FETCHOR4, - TILEGX_OPC_FINV, - TILEGX_OPC_FLUSH, - TILEGX_OPC_FLUSHWB, - TILEGX_OPC_FNOP, - TILEGX_OPC_FSINGLE_ADD1, - TILEGX_OPC_FSINGLE_ADDSUB2, - TILEGX_OPC_FSINGLE_MUL1, - TILEGX_OPC_FSINGLE_MUL2, - TILEGX_OPC_FSINGLE_PACK1, - TILEGX_OPC_FSINGLE_PACK2, - TILEGX_OPC_FSINGLE_SUB1, - TILEGX_OPC_ICOH, - TILEGX_OPC_ILL, - TILEGX_OPC_INV, - TILEGX_OPC_IRET, - TILEGX_OPC_J, - TILEGX_OPC_JAL, - TILEGX_OPC_JALR, - TILEGX_OPC_JALRP, - TILEGX_OPC_JR, - TILEGX_OPC_JRP, - TILEGX_OPC_LD, - TILEGX_OPC_LD1S, - TILEGX_OPC_LD1S_ADD, - TILEGX_OPC_LD1U, - TILEGX_OPC_LD1U_ADD, - TILEGX_OPC_LD2S, - TILEGX_OPC_LD2S_ADD, - TILEGX_OPC_LD2U, - TILEGX_OPC_LD2U_ADD, - TILEGX_OPC_LD4S, - TILEGX_OPC_LD4S_ADD, - TILEGX_OPC_LD4U, - TILEGX_OPC_LD4U_ADD, - TILEGX_OPC_LD_ADD, - TILEGX_OPC_LDNA, - TILEGX_OPC_LDNA_ADD, - TILEGX_OPC_LDNT, - TILEGX_OPC_LDNT1S, - TILEGX_OPC_LDNT1S_ADD, - TILEGX_OPC_LDNT1U, - TILEGX_OPC_LDNT1U_ADD, - TILEGX_OPC_LDNT2S, - TILEGX_OPC_LDNT2S_ADD, - TILEGX_OPC_LDNT2U, - TILEGX_OPC_LDNT2U_ADD, - TILEGX_OPC_LDNT4S, - TILEGX_OPC_LDNT4S_ADD, - TILEGX_OPC_LDNT4U, - TILEGX_OPC_LDNT4U_ADD, - TILEGX_OPC_LDNT_ADD, - TILEGX_OPC_LNK, - TILEGX_OPC_MF, - TILEGX_OPC_MFSPR, - TILEGX_OPC_MM, - TILEGX_OPC_MNZ, - TILEGX_OPC_MTSPR, - TILEGX_OPC_MUL_HS_HS, - TILEGX_OPC_MUL_HS_HU, - TILEGX_OPC_MUL_HS_LS, - TILEGX_OPC_MUL_HS_LU, - TILEGX_OPC_MUL_HU_HU, - TILEGX_OPC_MUL_HU_LS, - TILEGX_OPC_MUL_HU_LU, - TILEGX_OPC_MUL_LS_LS, - TILEGX_OPC_MUL_LS_LU, - TILEGX_OPC_MUL_LU_LU, - TILEGX_OPC_MULA_HS_HS, - TILEGX_OPC_MULA_HS_HU, - TILEGX_OPC_MULA_HS_LS, - TILEGX_OPC_MULA_HS_LU, - TILEGX_OPC_MULA_HU_HU, - TILEGX_OPC_MULA_HU_LS, - TILEGX_OPC_MULA_HU_LU, - TILEGX_OPC_MULA_LS_LS, - TILEGX_OPC_MULA_LS_LU, - TILEGX_OPC_MULA_LU_LU, - TILEGX_OPC_MULAX, - TILEGX_OPC_MULX, - TILEGX_OPC_MZ, - TILEGX_OPC_NAP, - TILEGX_OPC_NOP, - TILEGX_OPC_NOR, - TILEGX_OPC_OR, - TILEGX_OPC_ORI, - TILEGX_OPC_PCNT, - TILEGX_OPC_REVBITS, - TILEGX_OPC_REVBYTES, - TILEGX_OPC_ROTL, - TILEGX_OPC_ROTLI, - TILEGX_OPC_SHL, - TILEGX_OPC_SHL16INSLI, - TILEGX_OPC_SHL1ADD, - TILEGX_OPC_SHL1ADDX, - TILEGX_OPC_SHL2ADD, - TILEGX_OPC_SHL2ADDX, - TILEGX_OPC_SHL3ADD, - TILEGX_OPC_SHL3ADDX, - TILEGX_OPC_SHLI, - TILEGX_OPC_SHLX, - TILEGX_OPC_SHLXI, - TILEGX_OPC_SHRS, - TILEGX_OPC_SHRSI, - TILEGX_OPC_SHRU, - TILEGX_OPC_SHRUI, - TILEGX_OPC_SHRUX, - TILEGX_OPC_SHRUXI, - TILEGX_OPC_SHUFFLEBYTES, - TILEGX_OPC_ST, - TILEGX_OPC_ST1, - TILEGX_OPC_ST1_ADD, - TILEGX_OPC_ST2, - TILEGX_OPC_ST2_ADD, - TILEGX_OPC_ST4, - TILEGX_OPC_ST4_ADD, - TILEGX_OPC_ST_ADD, - TILEGX_OPC_STNT, - TILEGX_OPC_STNT1, - TILEGX_OPC_STNT1_ADD, - TILEGX_OPC_STNT2, - TILEGX_OPC_STNT2_ADD, - TILEGX_OPC_STNT4, - TILEGX_OPC_STNT4_ADD, - TILEGX_OPC_STNT_ADD, - TILEGX_OPC_SUB, - TILEGX_OPC_SUBX, - TILEGX_OPC_SUBXSC, - TILEGX_OPC_SWINT0, - TILEGX_OPC_SWINT1, - TILEGX_OPC_SWINT2, - TILEGX_OPC_SWINT3, - TILEGX_OPC_TBLIDXB0, - TILEGX_OPC_TBLIDXB1, - TILEGX_OPC_TBLIDXB2, - TILEGX_OPC_TBLIDXB3, - TILEGX_OPC_V1ADD, - TILEGX_OPC_V1ADDI, - TILEGX_OPC_V1ADDUC, - TILEGX_OPC_V1ADIFFU, - TILEGX_OPC_V1AVGU, - TILEGX_OPC_V1CMPEQ, - TILEGX_OPC_V1CMPEQI, - TILEGX_OPC_V1CMPLES, - TILEGX_OPC_V1CMPLEU, - TILEGX_OPC_V1CMPLTS, - TILEGX_OPC_V1CMPLTSI, - TILEGX_OPC_V1CMPLTU, - TILEGX_OPC_V1CMPLTUI, - TILEGX_OPC_V1CMPNE, - TILEGX_OPC_V1DDOTPU, - TILEGX_OPC_V1DDOTPUA, - TILEGX_OPC_V1DDOTPUS, - TILEGX_OPC_V1DDOTPUSA, - TILEGX_OPC_V1DOTP, - TILEGX_OPC_V1DOTPA, - TILEGX_OPC_V1DOTPU, - TILEGX_OPC_V1DOTPUA, - TILEGX_OPC_V1DOTPUS, - TILEGX_OPC_V1DOTPUSA, - TILEGX_OPC_V1INT_H, - TILEGX_OPC_V1INT_L, - TILEGX_OPC_V1MAXU, - TILEGX_OPC_V1MAXUI, - TILEGX_OPC_V1MINU, - TILEGX_OPC_V1MINUI, - TILEGX_OPC_V1MNZ, - TILEGX_OPC_V1MULTU, - TILEGX_OPC_V1MULU, - TILEGX_OPC_V1MULUS, - TILEGX_OPC_V1MZ, - TILEGX_OPC_V1SADAU, - TILEGX_OPC_V1SADU, - TILEGX_OPC_V1SHL, - TILEGX_OPC_V1SHLI, - TILEGX_OPC_V1SHRS, - TILEGX_OPC_V1SHRSI, - TILEGX_OPC_V1SHRU, - TILEGX_OPC_V1SHRUI, - TILEGX_OPC_V1SUB, - TILEGX_OPC_V1SUBUC, - TILEGX_OPC_V2ADD, - TILEGX_OPC_V2ADDI, - TILEGX_OPC_V2ADDSC, - TILEGX_OPC_V2ADIFFS, - TILEGX_OPC_V2AVGS, - TILEGX_OPC_V2CMPEQ, - TILEGX_OPC_V2CMPEQI, - TILEGX_OPC_V2CMPLES, - TILEGX_OPC_V2CMPLEU, - TILEGX_OPC_V2CMPLTS, - TILEGX_OPC_V2CMPLTSI, - TILEGX_OPC_V2CMPLTU, - TILEGX_OPC_V2CMPLTUI, - TILEGX_OPC_V2CMPNE, - TILEGX_OPC_V2DOTP, - TILEGX_OPC_V2DOTPA, - TILEGX_OPC_V2INT_H, - TILEGX_OPC_V2INT_L, - TILEGX_OPC_V2MAXS, - TILEGX_OPC_V2MAXSI, - TILEGX_OPC_V2MINS, - TILEGX_OPC_V2MINSI, - TILEGX_OPC_V2MNZ, - TILEGX_OPC_V2MULFSC, - TILEGX_OPC_V2MULS, - TILEGX_OPC_V2MULTS, - TILEGX_OPC_V2MZ, - TILEGX_OPC_V2PACKH, - TILEGX_OPC_V2PACKL, - TILEGX_OPC_V2PACKUC, - TILEGX_OPC_V2SADAS, - TILEGX_OPC_V2SADAU, - TILEGX_OPC_V2SADS, - TILEGX_OPC_V2SADU, - TILEGX_OPC_V2SHL, - TILEGX_OPC_V2SHLI, - TILEGX_OPC_V2SHLSC, - TILEGX_OPC_V2SHRS, - TILEGX_OPC_V2SHRSI, - TILEGX_OPC_V2SHRU, - TILEGX_OPC_V2SHRUI, - TILEGX_OPC_V2SUB, - TILEGX_OPC_V2SUBSC, - TILEGX_OPC_V4ADD, - TILEGX_OPC_V4ADDSC, - TILEGX_OPC_V4INT_H, - TILEGX_OPC_V4INT_L, - TILEGX_OPC_V4PACKSC, - TILEGX_OPC_V4SHL, - TILEGX_OPC_V4SHLSC, - TILEGX_OPC_V4SHRS, - TILEGX_OPC_V4SHRU, - TILEGX_OPC_V4SUB, - TILEGX_OPC_V4SUBSC, - TILEGX_OPC_WH64, - TILEGX_OPC_XOR, - TILEGX_OPC_XORI, - TILEGX_OPC_NONE -} tilegx_mnemonic; - - - -typedef enum -{ - TILEGX_PIPELINE_X0, - TILEGX_PIPELINE_X1, - TILEGX_PIPELINE_Y0, - TILEGX_PIPELINE_Y1, - TILEGX_PIPELINE_Y2, -} tilegx_pipeline; - -#define tilegx_is_x_pipeline(p) ((Int)(p) <= (Int)TILEGX_PIPELINE_X1) - -typedef enum -{ - TILEGX_OP_TYPE_REGISTER, - TILEGX_OP_TYPE_IMMEDIATE, - TILEGX_OP_TYPE_ADDRESS, - TILEGX_OP_TYPE_SPR -} tilegx_operand_type; - -struct tilegx_operand -{ - /* Is this operand a register, immediate or address? */ - tilegx_operand_type type; - - /* The default relocation type for this operand. */ - Int default_reloc : 16; - - /* How many bits is this value? (used for range checking) */ - UInt num_bits : 5; - - /* Is the value signed? (used for range checking) */ - UInt is_signed : 1; - - /* Is this operand a source register? */ - UInt is_src_reg : 1; - - /* Is this operand written? (i.e. is it a destination register) */ - UInt is_dest_reg : 1; - - /* Is this operand PC-relative? */ - UInt is_pc_relative : 1; - - /* By how many bits do we right shift the value before inserting? */ - UInt rightshift : 2; - - /* Return the bits for this operand to be ORed into an existing bundle. */ - tilegx_bundle_bits (*insert) (int op); - - /* Extract this operand and return it. */ - UInt (*extract) (tilegx_bundle_bits bundle); -}; - - -extern const struct tilegx_operand tilegx_operands[]; - -/* One finite-state machine per pipe for rapid instruction decoding. */ -extern const unsigned short * const -tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS]; - - -struct tilegx_opcode -{ - /* The opcode mnemonic, e.g. "add" */ - const char *name; - - /* The enum value for this mnemonic. */ - tilegx_mnemonic mnemonic; - - /* A bit mask of which of the five pipes this instruction - is compatible with: - X0 0x01 - X1 0x02 - Y0 0x04 - Y1 0x08 - Y2 0x10 */ - unsigned char pipes; - - /* How many operands are there? */ - unsigned char num_operands; - - /* Which register does this write implicitly, or TREG_ZERO if none? */ - unsigned char implicitly_written_register; - - /* Can this be bundled with other instructions (almost always true). */ - unsigned char can_bundle; - - /* The description of the operands. Each of these is an - * index into the tilegx_operands[] table. */ - unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS]; - - /* A mask of which bits have predefined values for each pipeline. - * This is useful for disassembly. */ - tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS]; - - /* For each bit set in fixed_bit_masks, what the value is for this - * instruction. */ - tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS]; -}; - -extern const struct tilegx_opcode tilegx_opcodes[]; - -/* Used for non-textual disassembly into structs. */ -struct tilegx_decoded_instruction -{ - const struct tilegx_opcode *opcode; - const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS]; - Long operand_values[TILEGX_MAX_OPERANDS]; -}; - - -/* Disassemble a bundle into a struct for machine processing. */ -extern Int parse_insn_tilegx ( tilegx_bundle_bits bits, - ULong pc, - struct tilegx_decoded_instruction - decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE] ); - -extern Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc ); - -extern tilegx_bundle_bits -encode_insn_tilegx ( struct tilegx_decoded_instruction decoded ); - - -extern tilegx_bundle_bits -mkTileGxInsn ( Int opc, Int argc, ... ); - -/* Given a set of bundle bits and a specific pipe, returns which - * instruction the bundle contains in that pipe. - */ -extern const struct tilegx_opcode * -find_opcode ( tilegx_bundle_bits bits, tilegx_pipeline pipe ); - - -#endif /* __TILEGX_DISASM_H */ - -/*---------------------------------------------------------------*/ -/*--- end tilegx-disasm.h ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 46b7604a91..b0ce1da517 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -60,8 +60,7 @@ typedef VexArchPPC64, VexArchS390X, VexArchMIPS32, - VexArchMIPS64, - VexArchTILEGX + VexArchMIPS64 } VexArch; @@ -177,9 +176,6 @@ typedef #define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK) #define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK) -/* Tilegx: baseline capability is TILEGX36 */ -#define VEX_HWCAPS_TILEGX_BASE (1<<16) /* TILEGX Baseline */ - /* arm: baseline capability is ARMv4 */ /* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */ #define VEX_HWCAPS_ARM_VFP (1<<6) /* VFP extension */ diff --git a/VEX/pub/libvex_basictypes.h b/VEX/pub/libvex_basictypes.h index ff5dad8660..86df4446bf 100644 --- a/VEX/pub/libvex_basictypes.h +++ b/VEX/pub/libvex_basictypes.h @@ -183,10 +183,6 @@ typedef unsigned long HWord; # define VEX_HOST_WORDSIZE 4 # define VEX_REGPARM(_n) /* */ -#elif defined(__tilegx__) -# define VEX_HOST_WORDSIZE 8 -# define VEX_REGPARM(_n) /* */ - #else # error "Vex: Fatal: Can't establish the host architecture" #endif diff --git a/VEX/pub/libvex_guest_tilegx.h b/VEX/pub/libvex_guest_tilegx.h deleted file mode 100644 index dfc9d1c9d3..0000000000 --- a/VEX/pub/libvex_guest_tilegx.h +++ /dev/null @@ -1,149 +0,0 @@ - -/*---------------------------------------------------------------*/ -/*--- begin libvex_guest_tilegx.h ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright (C) 2010-2017 Tilera Corp. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA. - - The GNU General Public License is contained in the file COPYING. -*/ - -/* Contributed by Zhi-Gang Liu */ - -#ifndef __LIBVEX_PUB_GUEST_TILEGX_H -#define __LIBVEX_PUB_GUEST_TILEGX_H - -#include "libvex_basictypes.h" -#include "libvex_emnote.h" - -#undef TILEGX_DEBUG - -/*---------------------------------------------------------------*/ -/*--- Vex's representation of the tilegx CPU state. ---*/ -/*---------------------------------------------------------------*/ - -typedef ULong ULONG; - -typedef -struct { - /* CPU Registers */ - /* 0 */ ULONG guest_r0; - /* 8 */ ULONG guest_r1; - /* 16 */ ULONG guest_r2; - /* 24 */ ULONG guest_r3; - /* 32 */ ULONG guest_r4; - /* 40 */ ULONG guest_r5; - /* 48 */ ULONG guest_r6; - /* 56 */ ULONG guest_r7; - /* 64 */ ULONG guest_r8; - /* 72 */ ULONG guest_r9; - /* 80 */ ULONG guest_r10; - /* 88 */ ULONG guest_r11; - /* 96 */ ULONG guest_r12; - /* 104 */ ULONG guest_r13; - /* 112 */ ULONG guest_r14; - /* 120 */ ULONG guest_r15; - /* 128 */ ULONG guest_r16; - /* 136 */ ULONG guest_r17; - /* 144 */ ULONG guest_r18; - /* 152 */ ULONG guest_r19; - /* 160 */ ULONG guest_r20; - /* 168 */ ULONG guest_r21; - /* 176 */ ULONG guest_r22; - /* 184 */ ULONG guest_r23; - /* 192 */ ULONG guest_r24; - /* 200 */ ULONG guest_r25; - /* 208 */ ULONG guest_r26; - /* 216 */ ULONG guest_r27; - /* 224 */ ULONG guest_r28; - /* 232 */ ULONG guest_r29; - /* 240 */ ULONG guest_r30; - /* 248 */ ULONG guest_r31; - /* 256 */ ULONG guest_r32; - /* 264 */ ULONG guest_r33; - /* 272 */ ULONG guest_r34; - /* 280 */ ULONG guest_r35; - /* 288 */ ULONG guest_r36; - /* 296 */ ULONG guest_r37; - /* 304 */ ULONG guest_r38; - /* 312 */ ULONG guest_r39; - /* 320 */ ULONG guest_r40; - /* 328 */ ULONG guest_r41; - /* 336 */ ULONG guest_r42; - /* 344 */ ULONG guest_r43; - /* 352 */ ULONG guest_r44; - /* 360 */ ULONG guest_r45; - /* 368 */ ULONG guest_r46; - /* 376 */ ULONG guest_r47; - /* 384 */ ULONG guest_r48; - /* 392 */ ULONG guest_r49; - /* 400 */ ULONG guest_r50; - /* 408 */ ULONG guest_r51; - /* 416 */ ULONG guest_r52; /* FP */ - /* 424 */ ULONG guest_r53; - /* 432 */ ULONG guest_r54; /* SP */ - /* 440 */ ULONG guest_r55; /* LR */ - /* 448 */ ULONG guest_r56; /* zero */ - /* 456 */ ULONG guest_r57; /* Reserved */ - /* 464 */ ULONG guest_r58; /* Reserved */ - /* 472 */ ULONG guest_r59; /* Reserved */ - /* 480 */ ULONG guest_r60; /* Reserved */ - /* 488 */ ULONG guest_r61; /* Reserved */ - /* 496 */ ULONG guest_r62; /* Reserved */ - /* 504 */ ULONG guest_r63; /* Reserved */ - /* 512 */ ULONG guest_pc; - /* 520 */ ULONG guest_spare; /* Reserved */ - /* 528 */ ULONG guest_EMNOTE; - /* 536 */ ULONG guest_CMSTART; - /* 544 */ ULONG guest_CMLEN; - /* 552 */ ULONG guest_NRADDR; - /* 560 */ ULong guest_cmpexch; - /* 568 */ ULong guest_zero; - /* 576 */ ULong guest_ex_context_0; - /* 584 */ ULong guest_ex_context_1; - /* 592 */ ULong host_EvC_FAILADDR; - /* 600 */ ULong host_EvC_COUNTER; - /* 608 */ ULong guest_COND; - /* 616 */ ULong PAD; - -} VexGuestTILEGXState; - -#define OFFSET_tilegx_r(_N) (8 * (_N)) - -/*---------------------------------------------------------------*/ -/*--- Utility functions for TILEGX guest stuff. ---*/ -/*---------------------------------------------------------------*/ - -/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */ - -/* Initialise all guest TILEGX state. */ - -extern -void LibVEX_GuestTILEGX_initialise ( /*OUT*/VexGuestTILEGXState* vex_state ); - - -#endif /* __LIBVEX_PUB_GUEST_TILEGX_H */ - - -/*---------------------------------------------------------------*/ -/*--- libvex_guest_tilegx.h ---*/ -/*---------------------------------------------------------------*/