From: Hugo Villeneuve Date: Fri, 17 Apr 2026 14:53:37 +0000 (-0400) Subject: serial: max310x: add comments for PLL limits X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ebd57bda9df6234d93e05dfe2fd250c6535ca3bb;p=thirdparty%2Flinux.git serial: max310x: add comments for PLL limits Add comments to help clarify the provenance of the various hardcoded values used in computing the ref clk. Assisted-by: Gemini:Pro Signed-off-by: Hugo Villeneuve Link: https://patch.msgid.link/20260417-max310x-2-v1-10-b424e105ecac@dimonoff.com Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c index 748306d1a9329..9f423b3b4201d 100644 --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c @@ -585,6 +585,23 @@ static u8 max310x_pll_mult_to_id(u8 pll_mult) } } +/* + * From table 7 in datasheet: PLLFactor Selector Guide + * + * +-----------+----------------+-------------------+-------------------+ + * | PLLFactor | MULTIPLICATION | fPLLIN | fREF | + * | (1 & 0) | FACTOR +---------+---------+---------+---------+ + * | | | MIN | MAX | MIN | MAX | + * +-----------+----------------+---------+---------+---------+---------+ + * | 0 | 6 | 500kHz | 800kHz | 3MHz | 4.8MHz | + * +-----------+----------------+---------+---------+---------+---------+ + * | 1 | 48 | 850kHz | 1.2MHz | 40.8MHz | 56MHz | + * +-----------+----------------+---------+---------+---------+---------+ + * | 2 | 96 | 425kHz | 1MHz | 40.8MHz | 96MHz | + * +-----------+----------------+---------+---------+---------+---------+ + * | 3 | 144 | 390kHz | 667kHz | 56MHz | 96MHz | + * +-----------+----------------+---------+---------+---------+---------+ + */ static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, unsigned int freq, unsigned int *fref, bool xtal) {