From: Richard Earnshaw <rearnsha@arm.com>
Date: Thu, 16 Nov 2006 08:57:50 +0000 (+0000)
Subject: arm.md (abssi2): Allow Thumb as well.
X-Git-Tag: releases/gcc-4.3.0~8437
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ecaf6f07808d7d2f5a3929de189d8799e8a085f5;p=thirdparty%2Fgcc.git

arm.md (abssi2): Allow Thumb as well.

	* arm.md (abssi2): Allow Thumb as well.	 Use an SImode scratch for
	Thumb.
	(arm_neg_abssi2): Renamed from neg_abssi2.
	(thumb_abssi2, thumb_neg_abssi2): New patterns with splitters.

From-SVN: r118884
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eb31d9ffe747..c5ae49aec635 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2006-11-16  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.md (abssi2): Allow Thumb as well.	 Use an SImode scratch for
+	Thumb.
+	(arm_neg_abssi2): Renamed from neg_abssi2.
+	(thumb_abssi2, thumb_neg_abssi2): New patterns with splitters.
+
 2006-11-16  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.c (ix86_function_sseregparm): Fix comment:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b2e3c7ee9972..83a3cf41252e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3066,12 +3066,17 @@
   [(parallel
     [(set (match_operand:SI         0 "s_register_operand" "")
 	  (abs:SI (match_operand:SI 1 "s_register_operand" "")))
-     (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_ARM"
-  "")
+     (clobber (match_dup 2))])]
+  "TARGET_EITHER"
+  "
+  if (TARGET_THUMB)
+    operands[2] = gen_rtx_SCRATCH (SImode);
+  else
+    operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
+")
 
 (define_insn "*arm_abssi2"
-  [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
+  [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 	(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"
@@ -3084,7 +3089,21 @@
    (set_attr "length" "8")]
 )
 
-(define_insn "*neg_abssi2"
+(define_insn_and_split "*thumb_abssi2"
+  [(set (match_operand:SI 0 "s_register_operand" "=l")
+	(abs:SI (match_operand:SI 1 "s_register_operand" "l")))
+   (clobber (match_scratch:SI 2 "=&l"))]
+  "TARGET_THUMB"
+  "#"
+  "TARGET_THUMB && reload_completed"
+  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
+   (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
+  ""
+  [(set_attr "length" "6")]
+)
+
+(define_insn "*arm_neg_abssi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 	(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
    (clobber (reg:CC CC_REGNUM))]
@@ -3098,6 +3117,20 @@
    (set_attr "length" "8")]
 )
 
+(define_insn_and_split "*thumb_neg_abssi2"
+  [(set (match_operand:SI 0 "s_register_operand" "=l")
+	(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "l"))))
+   (clobber (match_scratch:SI 2 "=&l"))]
+  "TARGET_THUMB"
+  "#"
+  "TARGET_THUMB && reload_completed"
+  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))
+   (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
+  ""
+  [(set_attr "length" "6")]
+)
+
 (define_expand "abssf2"
   [(set (match_operand:SF         0 "s_register_operand" "")
 	(abs:SF (match_operand:SF 1 "s_register_operand" "")))]