From: Zhenzhong Duan Date: Tue, 6 Jan 2026 06:12:43 +0000 (-0500) Subject: intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ecd0ff2d2e7897f172d7f5678eb84446ec43f4ae;p=thirdparty%2Fqemu.git intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry of rid2pasid, then it was extended to get any pasid entry. So a new name vtd_ce_get_pasid_entry is better to match what it actually does. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Michael S. Tsirkin Link: https://lore.kernel.org/qemu-devel/20260106061304.314546-2-zhenzhong.duan@intel.com Signed-off-by: Cédric Le Goater --- diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 224b7b9479..436a30288b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -954,10 +954,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s, return 0; } -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, - VTDContextEntry *ce, - VTDPASIDEntry *pe, - uint32_t pasid) +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, + VTDPASIDEntry *pe, uint32_t pasid) { dma_addr_t pasid_dir_base; int ret = 0; @@ -1035,7 +1033,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, VTDPASIDEntry pe; if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return VTD_PE_GET_FL_LEVEL(&pe); } else { @@ -1058,7 +1056,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, VTDPASIDEntry pe; if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } @@ -1126,7 +1124,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, VTDPASIDEntry pe; if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; } else { @@ -1532,7 +1530,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } /* Map a device to its corresponding domain (context-entry) */ @@ -1621,7 +1619,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, VTDPASIDEntry pe; if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } @@ -1697,7 +1695,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VTDContextEntry *ce, int ret; if (s->root_scalable) { - ret = vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + ret = vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT @@ -3083,7 +3081,7 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, return ret; } - return vtd_ce_get_rid2pasid_entry(s, &ce, pe, vtd_as->pasid); + return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid); } static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) @@ -5161,7 +5159,7 @@ static int vtd_pri_perform_implicit_invalidation(VTDAddressSpace *vtd_as, if (ret) { return -EINVAL; } - ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe, vtd_as->pasid); + ret = vtd_ce_get_pasid_entry(s, &ce, &pe, vtd_as->pasid); if (ret) { return -EINVAL; }