From: Michal Wajdeczko Date: Tue, 3 Feb 2026 21:12:37 +0000 (+0100) Subject: drm/xe: Promote struct xe_mmio definition to own file X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ed61c18617b1d95a9e0d4917749f28776eccefb7;p=thirdparty%2Flinux.git drm/xe: Promote struct xe_mmio definition to own file We already have separate .c and .h files for xe_mmio functions, time to introduce _types.h to follow what other components do. Signed-off-by: Michal Wajdeczko Reviewed-by: Stuart Summers #v1 Reviewed-by: Matt Roper Link: https://patch.msgid.link/20260203211240.745-3-michal.wajdeczko@intel.com --- diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index b4600c5069a99..2ea931c1550ac 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -18,6 +18,7 @@ #include "xe_lmtt_types.h" #include "xe_memirq_types.h" #include "xe_mert.h" +#include "xe_mmio_types.h" #include "xe_oa_types.h" #include "xe_pagefault_types.h" #include "xe_platform_types.h" @@ -100,45 +101,6 @@ enum xe_wedged_mode { const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \ struct xe_tile * : (tile__)->xe) -/** - * struct xe_mmio - register mmio structure - * - * Represents an MMIO region that the CPU may use to access registers. A - * region may share its IO map with other regions (e.g., all GTs within a - * tile share the same map with their parent tile, but represent different - * subregions of the overall IO space). - */ -struct xe_mmio { - /** @tile: Backpointer to tile, used for tracing */ - struct xe_tile *tile; - - /** @regs: Map used to access registers. */ - void __iomem *regs; - - /** - * @sriov_vf_gt: Backpointer to GT. - * - * This pointer is only set for GT MMIO regions and only when running - * as an SRIOV VF structure - */ - struct xe_gt *sriov_vf_gt; - - /** - * @regs_size: Length of the register region within the map. - * - * The size of the iomap set in *regs is generally larger than the - * register mmio space since it includes unused regions and/or - * non-register regions such as the GGTT PTEs. - */ - size_t regs_size; - - /** @adj_limit: adjust MMIO address if address is below this value */ - u32 adj_limit; - - /** @adj_offset: offset to add to MMIO address when adjusting */ - u32 adj_offset; -}; - /** * struct xe_tile - hardware tile structure * diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 5318d92fd473f..1d7360b56ac69 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -45,11 +45,6 @@ typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(XE_MAX_DSS_FUSE_BITS)]; typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(XE_MAX_EU_FUSE_BITS)]; typedef unsigned long xe_l3_bank_mask_t[BITS_TO_LONGS(XE_MAX_L3_BANK_MASK_BITS)]; -struct xe_mmio_range { - u32 start; - u32 end; -}; - /* * The hardware has multiple kinds of multicast register ranges that need * special register steering (and future platforms are expected to add diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h index 6a8faebb2c298..41ae720acbc3b 100644 --- a/drivers/gpu/drm/xe/xe_mmio.h +++ b/drivers/gpu/drm/xe/xe_mmio.h @@ -6,7 +6,7 @@ #ifndef _XE_MMIO_H_ #define _XE_MMIO_H_ -#include "xe_gt_types.h" +#include "xe_mmio_types.h" struct xe_device; struct xe_reg; diff --git a/drivers/gpu/drm/xe/xe_mmio_types.h b/drivers/gpu/drm/xe/xe_mmio_types.h new file mode 100644 index 0000000000000..99e8f269eaf2e --- /dev/null +++ b/drivers/gpu/drm/xe/xe_mmio_types.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022-2026 Intel Corporation + */ + +#ifndef _XE_MMIO_TYPES_H_ +#define _XE_MMIO_TYPES_H_ + +#include + +struct xe_gt; +struct xe_tile; + +/** + * struct xe_mmio - register mmio structure + * + * Represents an MMIO region that the CPU may use to access registers. A + * region may share its IO map with other regions (e.g., all GTs within a + * tile share the same map with their parent tile, but represent different + * subregions of the overall IO space). + */ +struct xe_mmio { + /** @tile: Backpointer to tile, used for tracing */ + struct xe_tile *tile; + + /** @regs: Map used to access registers. */ + void __iomem *regs; + + /** + * @sriov_vf_gt: Backpointer to GT. + * + * This pointer is only set for GT MMIO regions and only when running + * as an SRIOV VF structure + */ + struct xe_gt *sriov_vf_gt; + + /** + * @regs_size: Length of the register region within the map. + * + * The size of the iomap set in *regs is generally larger than the + * register mmio space since it includes unused regions and/or + * non-register regions such as the GGTT PTEs. + */ + size_t regs_size; + + /** @adj_limit: adjust MMIO address if address is below this value */ + u32 adj_limit; + + /** @adj_offset: offset to add to MMIO address when adjusting */ + u32 adj_offset; +}; + +/** + * struct xe_mmio_range - register range structure + * + * @start: first register offset in the range. + * @end: last register offset in the range. + */ +struct xe_mmio_range { + u32 start; + u32 end; +}; + +#endif