From: Lingling Kong Date: Wed, 14 Aug 2024 08:48:30 +0000 (+0800) Subject: i386: Optimization for APX NDD is always zero-uppered for shift X-Git-Tag: basepoints/gcc-16~6637 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=edb2712936368e803fd67aa520323054b2a5c5e7;p=thirdparty%2Fgcc.git i386: Optimization for APX NDD is always zero-uppered for shift gcc/ChangeLog: PR target/113729 * config/i386/i386.md (*ashlqi3_1_zext): New define_insn. (*ashlhi3_1_zext): Ditto. (*qi3_1_zext): Ditto. (*hi3_1_zext): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr113729.c: Add testcase for shift and rotate. --- diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9f933e908d3..d3ba2425f16 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15919,6 +15919,28 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "SI")]) +(define_insn "*ashlqi3_1_zext" + [(set (match_operand:SWI248x 0 "register_operand" "=r") + (zero_extend:SWI248x + (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "nonmemory_operand" "cI"))))] + "TARGET_APX_NDD && " + "sal{b}\t{%2, %1, %b0|%b0, %1, %2}" + [(set_attr "type" "ishiftx") + (set_attr "has_nf" "1") + (set_attr "mode" "QI")]) + +(define_insn "*ashlhi3_1_zext" + [(set (match_operand:SWI48x 0 "register_operand" "=r") + (zero_extend:SWI48x + (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "nonmemory_operand" "cI"))))] + "TARGET_APX_NDD && " + "sal{w}\t{%2, %1, %w0|%w0, %1, %2}" + [(set_attr "type" "ishiftx") + (set_attr "has_nf" "1") + (set_attr "mode" "HI")]) + (define_insn "*ashlsi3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") (zero_extend:DI @@ -17403,6 +17425,28 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "SI")]) +(define_insn "*qi3_1_zext" + [(set (match_operand:SWI248x 0 "register_operand" "=r") + (zero_extend:SWI248x + (any_shiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "nonmemory_operand" "cI"))))] + "TARGET_APX_NDD && " + "{b}\t{%2, %1, %b0|%b0, %1, %2}" + [(set_attr "type" "ishift") + (set_attr "has_nf" "1") + (set_attr "mode" "QI")]) + +(define_insn "*hi3_1_zext" + [(set (match_operand:SWI48x 0 "register_operand" "=r") + (zero_extend:SWI48x + (any_shiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "nonmemory_operand" "cI"))))] + "TARGET_APX_NDD && " + "{w}\t{%2, %1, %w0|%w0, %1, %2}" + [(set_attr "type" "ishift") + (set_attr "has_nf" "1") + (set_attr "mode" "HI")]) + (define_insn "*si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r,r,?k") (zero_extend:DI @@ -18179,6 +18223,28 @@ [(set_attr "type" "rotatex") (set_attr "mode" "SI")]) +(define_insn "*qi3_1_zext" + [(set (match_operand:SWI248x 0 "register_operand" "=r") + (zero_extend:SWI248x + (any_rotate:QI (match_operand:QI 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "nonmemory_operand" "cI"))))] + "TARGET_APX_NDD && " + "{b}\t{%2, %1, %b0|%b0, %1, %2}" + [(set_attr "type" "rotate") + (set_attr "has_nf" "1") + (set_attr "mode" "QI")]) + +(define_insn "*hi3_1_zext" + [(set (match_operand:SWI48x 0 "register_operand" "=r") + (zero_extend:SWI48x + (any_rotate:HI (match_operand:HI 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "nonmemory_operand" "cI"))))] + "TARGET_APX_NDD && " + "{w}\t{%2, %1, %w0|%w0, %1, %2}" + [(set_attr "type" "rotate") + (set_attr "has_nf" "1") + (set_attr "mode" "HI")]) + (define_insn "*si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r,r") (zero_extend:DI diff --git a/gcc/testsuite/gcc.target/i386/pr113729.c b/gcc/testsuite/gcc.target/i386/pr113729.c index d17e0999e6c..53b6df78c26 100644 --- a/gcc/testsuite/gcc.target/i386/pr113729.c +++ b/gcc/testsuite/gcc.target/i386/pr113729.c @@ -71,3 +71,65 @@ F (int, char, xor, ^) F (int64_t, char, xor, ^) F (int, short, xor, ^) F (int64_t, short, xor, ^) + +#define F2(TYPE1,TYPE2, OP_NAME, OP, IMM) \ +TYPE1 \ +__attribute__ ((noipa)) \ +f2_##OP_NAME##_##TYPE1##_##TYPE2 (TYPE2 a) \ +{ \ + unsigned TYPE2 b = a OP IMM; \ + return b; \ +} + +/* ashlqi3_1_zext */ +F2 (short, char, shl, <<, 7) +F2 (int, char, shl, <<, 6) +F2 (int64_t, char, shl, <<, 7) +F2 (int, short, shl, <<, 6) +F2 (int64_t, short, shl, <<, 3) + +/* ashrqi3_1_zext */ +F2 (short, char, sar, >>, 7) +F2 (int, char, sar, >>, 6) +F2 (int64_t, char, sar, >>, 7) +F2 (int, short, sar, >>, 6) +F2 (int64_t, short, sar, >>, 3) + +#define F3(TYPE1,TYPE2, OP_NAME, OP, IMM) \ +TYPE1 \ +__attribute__ ((noipa)) \ +f3_##OP_NAME##_##TYPE1##_##TYPE2 (TYPE2 a) \ +{ \ + TYPE2 b = a OP IMM; \ + return b; \ +} + +/* lshrhi3_1_zext */ +F3 (short, uint8_t, shr, >>, 7) +F3 (int, uint8_t, shr, >>, 6) +F3 (int64_t, uint8_t, shr, >>, 7) +F3 (int, uint16_t, shr, >>, 6) +F3 (int64_t, uint16_t, shr, >>, 3) + +#define F4(TYPE1,TYPE2, OP_NAME, OP1, OP2, IMM1) \ +TYPE1 \ +__attribute__ ((noipa)) \ +foo4_##OP_NAME##_##TYPE1##_##TYPE2 (unsigned TYPE2 a) \ +{ \ + unsigned TYPE2 b = (a OP1 IMM1 | a OP2 (8 * sizeof(TYPE2) - IMM1)); \ + return b; \ +} + +/* rotrqi3_1_zext */ +F4 (short, char, ror, >>, <<, 1) +F4 (int, char, ror, >>, <<, 1) +F4 (long, char, ror, >>, <<, 1) +F4 (int, short, ror, >>, <<, 1) +F4 (long, short, ror, >>, <<, 1) + +/* rotlqi3_1_zext */ +F4 (short, char, rol, <<, >>, 1) +F4 (int, char, rol, <<, >>, 1) +F4 (long, char, rol, <<, >>, 1) +F4 (int, short, rol, <<, >>, 1) +F4 (long, short, rol, <<, >>, 1)