From: David Edelsohn Date: Tue, 23 Feb 2016 22:28:23 +0000 (+0000) Subject: re PR target/69810 (PowerPC64: unrecognizable insn) X-Git-Tag: basepoints/gcc-7~792 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=edd65746c54c396b383e1e7a7e5b47641a346294;p=thirdparty%2Fgcc.git re PR target/69810 (PowerPC64: unrecognizable insn) PR target/69810 * config/rs6000/rs6000.md (zero_extendqi2_dot): Convert from define_insn_and_split to define_insn. (zero_extendqi2_dot2): Same. (extendqi2_dot): Same. (extendqi2_dot2): Same. From-SVN: r233648 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 07b50b5d3a1d..0ba100dedf24 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-02-23 David Edelsohn + + PR target/69810 + * config/rs6000/rs6000.md (zero_extendqi2_dot): Convert from + define_insn_and_split to define_insn. + (zero_extendqi2_dot2): Same. + (extendqi2_dot): Same. + (extendqi2_dot2): Same. + 2016-02-23 Evandro Menezes * config/arm/exynos-m1.md: Change cost of STP, fix bypass for stores diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 365bc5efe101..0299a0002af2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -701,7 +701,7 @@ rlwinm %0,%1,0,0xff" [(set_attr "type" "load,shift")]) -(define_insn_and_split "*zero_extendqi2_dot" +(define_insn "*zero_extendqi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -709,19 +709,12 @@ "rs6000_gen_cell_microcode" "@ andi. %0,%1,0xff - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" - [(set (match_dup 0) - (zero_extend:EXTQI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "" + rlwinm %0,%1,0,0xff\;cmpwi %2,%0,0" [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn_and_split "*zero_extendqi2_dot2" +(define_insn "*zero_extendqi2_dot2" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -730,14 +723,7 @@ "rs6000_gen_cell_microcode" "@ andi. %0,%1,0xff - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" - [(set (match_dup 0) - (zero_extend:EXTQI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "" + rlwinm %0,%1,0,0xff\;cmpwi %2,%0,0" [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) @@ -855,7 +841,7 @@ "extsb %0,%1" [(set_attr "type" "exts")]) -(define_insn_and_split "*extendqi2_dot" +(define_insn "*extendqi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -863,19 +849,12 @@ "rs6000_gen_cell_microcode" "@ extsb. %0,%1 - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" - [(set (match_dup 0) - (sign_extend:EXTQI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "" + extsb %0,%1\;cmpwi %2,%0,0" [(set_attr "type" "exts") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn_and_split "*extendqi2_dot2" +(define_insn "*extendqi2_dot2" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -884,14 +863,7 @@ "rs6000_gen_cell_microcode" "@ extsb. %0,%1 - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" - [(set (match_dup 0) - (sign_extend:EXTQI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "" + extsb %0,%1\;cmpwi %2,%0,0" [(set_attr "type" "exts") (set_attr "dot" "yes") (set_attr "length" "4,8")])