From: Carl Love Date: Tue, 29 Mar 2016 21:28:43 +0000 (+0000) Subject: Power PC Add support for ISA 3.0, part 1 X-Git-Tag: svn/VALGRIND_3_12_0~186 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=efb480318c26ee6a500f6189c70756735db3c87c;p=thirdparty%2Fvalgrind.git Power PC Add support for ISA 3.0, part 1 The Floating-point condition code bits FPCC is bits[15:12] of the FPSCR. The instructions fcmpu, fcmpo, dcmpu, dcmpq, dtstdc, dtstdcq, xscmpodq and xscmpudq set the FPCC bits in addition to the BE field of the CC register. This support is needed by the ISA 3.0 instructions to be added. Added support to emulate the modsw, moduw, modsd, modud, extswsli, maddld, maddhd, maaddhdu, xxperm, xxpermr, vabsdub, vabsduh, vabsduw, mtvsrws, xxextractuw, xxinsertw, xxspltib, xxbrh, xxbrw, xxbrd, xxbrq, vpermr, vextractub, vextractuh, vextractuw, vextractd, vinsertb, vinserth, vinsertw, vinsertd, lxvwsx, stxvb16x, stxvx, lxvb16x, lxvh8x, lxvx instructions. valgrind bugzilla 359767 VEX commit 3214 git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15837 --- diff --git a/configure.ac b/configure.ac index 888a3085b0..202e0f9d51 100644 --- a/configure.ac +++ b/configure.ac @@ -1504,6 +1504,22 @@ AM_CONDITIONAL(SUPPORTS_HTM, test x$ac_compiler_supports_htm = xyes \ -a x$ac_compiler_sees_htm_builtins = xyes \ -a x$HWCAP_HAS_HTM = xyes ) +# isa 3.0 checking +AC_MSG_CHECKING([that assembler knows ISA 3.0 ]) + +AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ +]], [[ + __asm__ __volatile__("cnttzw 1,2 "); +]])], [ +ac_asm_have_isa_3_0=yes +AC_MSG_RESULT([yes]) +], [ +ac_asm_have_isa_3_0=no +AC_MSG_RESULT([no]) +]) + +AM_CONDITIONAL(HAS_ISA_3_0, test x$ac_asm_have_isa_3_0 = xyes) + # Check for pthread_create@GLIBC2.0 AC_MSG_CHECKING([for pthread_create@GLIBC2.0()]) diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index ae8b929534..34273d7a84 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1068,7 +1068,7 @@ Bool VG_(machine_get_hwcaps)( void ) vki_sigaction_toK_t tmp_sigill_act, tmp_sigfpe_act; volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP; - volatile Bool have_isa_2_07; + volatile Bool have_isa_2_07, have_isa_3_0; Int r; /* This is a kludge. Really we ought to back-convert saved_act @@ -1171,6 +1171,14 @@ Bool VG_(machine_get_hwcaps)( void ) __asm__ __volatile__(".long 0x7c000166"); /* mtvsrd XT,RA */ } + /* Check for ISA 3.0 support. */ + have_isa_3_0 = True; + if (VG_MINIMAL_SETJMP(env_unsup_insn)) { + have_isa_3_0 = False; + } else { + __asm__ __volatile__(".long 0x7d205434"); /* cnttzw RT, RB */ + } + /* determine dcbz/dcbzl sizes while we still have the signal * handlers registered */ find_ppc_dcbz_sz(&vai); @@ -1181,10 +1189,10 @@ Bool VG_(machine_get_hwcaps)( void ) vg_assert(r == 0); r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); vg_assert(r == 0); - VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d ISA2.07 %d\n", + VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d ISA2.07 %d ISA3.0 %d\n", (Int)have_F, (Int)have_V, (Int)have_FX, (Int)have_GX, (Int)have_VX, (Int)have_DFP, - (Int)have_isa_2_07); + (Int)have_isa_2_07, (Int)have_isa_3_0); /* Make FP a prerequisite for VMX (bogusly so), and for FX and GX. */ if (have_V && !have_F) have_V = False; @@ -1207,6 +1215,7 @@ Bool VG_(machine_get_hwcaps)( void ) if (have_VX) vai.hwcaps |= VEX_HWCAPS_PPC32_VX; if (have_DFP) vai.hwcaps |= VEX_HWCAPS_PPC32_DFP; if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA2_07; + if (have_isa_3_0) vai.hwcaps |= VEX_HWCAPS_PPC32_ISA3_0; VG_(machine_get_cache_info)(&vai); @@ -1223,7 +1232,7 @@ Bool VG_(machine_get_hwcaps)( void ) vki_sigaction_toK_t tmp_sigill_act, tmp_sigfpe_act; volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP; - volatile Bool have_isa_2_07; + volatile Bool have_isa_2_07, have_isa_3_0; Int r; /* This is a kludge. Really we ought to back-convert saved_act @@ -1318,6 +1327,14 @@ Bool VG_(machine_get_hwcaps)( void ) __asm__ __volatile__(".long 0x7c000166"); /* mtvsrd XT,RA */ } + /* Check for ISA 3.0 support. */ + have_isa_3_0 = True; + if (VG_MINIMAL_SETJMP(env_unsup_insn)) { + have_isa_3_0 = False; + } else { + __asm__ __volatile__(".long 0x7d205434"); /* cnttzw RT, RB */ + } + /* determine dcbz/dcbzl sizes while we still have the signal * handlers registered */ find_ppc_dcbz_sz(&vai); @@ -1325,10 +1342,10 @@ Bool VG_(machine_get_hwcaps)( void ) VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL); VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL); VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); - VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d ISA2.07 %d\n", + VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d ISA2.07 %d ISA3.0 %d\n", (Int)have_F, (Int)have_V, (Int)have_FX, (Int)have_GX, (Int)have_VX, (Int)have_DFP, - (Int)have_isa_2_07); + (Int)have_isa_2_07, (int)have_isa_3_0); /* on ppc64be, if we don't even have FP, just give up. */ if (!have_F) return False; @@ -1351,6 +1368,7 @@ Bool VG_(machine_get_hwcaps)( void ) if (have_VX) vai.hwcaps |= VEX_HWCAPS_PPC64_VX; if (have_DFP) vai.hwcaps |= VEX_HWCAPS_PPC64_DFP; if (have_isa_2_07) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA2_07; + if (have_isa_3_0) vai.hwcaps |= VEX_HWCAPS_PPC64_ISA3_0; VG_(machine_get_cache_info)(&vai);