From: Ryan Wanner <Ryan.Wanner@microchip.com>
Date: Mon, 7 Jul 2025 11:31:27 +0000 (+0530)
Subject: clk: at91: Update MAX PLL and master clk ID
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=eff0e49d1c6c75c92665c285216cf9bd785e5ac1;p=thirdparty%2Fu-boot.git

clk: at91: Update MAX PLL and master clk ID

Update the MAX PLL and master CLK ID to support sama7d65
SoC family.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---

diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index d28775d64d3..cdc5271fa83 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -37,7 +37,7 @@
 
 #define PMC_MCR_ID(x)		((x) & PMC_MCR_ID_MSK)
 
-#define MASTER_MAX_ID		4
+#define MASTER_MAX_ID		10
 
 struct clk_master {
 	void __iomem *base;
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index df8172bccac..65be2775ac3 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -32,7 +32,7 @@
 #define UPLL_DIV		2
 #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
 
-#define PLL_MAX_ID		7
+#define PLL_MAX_ID		8
 
 struct sam9x60_pll {
 	void __iomem *base;