From: Florian Krohm Date: Wed, 24 Sep 2014 15:18:09 +0000 (+0000) Subject: Constification part 4. X-Git-Tag: svn/VALGRIND_3_11_0^2~192 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f2f2f6245ef074b457433e7cd2eb462e1c6138ee;p=thirdparty%2Fvalgrind.git Constification part 4. Constify pointer typed members of VexTanslateArgs. Fix ripple. git-svn-id: svn://svn.valgrind.org/vex/trunk@2959 --- diff --git a/VEX/priv/guest_amd64_defs.h b/VEX/priv/guest_amd64_defs.h index c321127065..6968e3d146 100644 --- a/VEX/priv/guest_amd64_defs.h +++ b/VEX/priv/guest_amd64_defs.h @@ -54,7 +54,7 @@ DisResult disInstr_AMD64 ( IRSB* irbb, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 0f85ecab13..7dbd7a9176 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -189,7 +189,7 @@ static VexEndness host_endness; /* Pointer to the guest code area (points to start of BB, not to the insn being processed). */ -static UChar* guest_code; +static const UChar* guest_code; /* The guest address corresponding to guest_code[0]. */ static Addr64 guest_RIP_bbstart; @@ -9868,7 +9868,7 @@ static void gen_SEGV_if_not_32_aligned ( IRTemp effective_addr ) { Same for BTS, BTR */ -static Bool can_be_used_with_LOCK_prefix ( UChar* opc ) +static Bool can_be_used_with_LOCK_prefix ( const UChar* opc ) { switch (opc[0]) { case 0x00: case 0x01: case 0x08: case 0x09: @@ -31167,7 +31167,7 @@ DisResult disInstr_AMD64_WRK ( /* Spot "Special" instructions (see comment at top of file). */ { - UChar* code = (UChar*)(guest_code + delta); + const UChar* code = guest_code + delta; /* Spot the 16-byte preamble: 48C1C703 rolq $3, %rdi 48C1C70D rolq $13, %rdi @@ -31379,7 +31379,7 @@ DisResult disInstr_AMD64_WRK ( leading escapes. Check that any LOCK prefix is actually allowed. */ if (haveLOCK(pfx)) { - if (can_be_used_with_LOCK_prefix( (UChar*)&guest_code[delta] )) { + if (can_be_used_with_LOCK_prefix( &guest_code[delta] )) { DIP("lock "); } else { *expect_CAS = False; @@ -31500,7 +31500,7 @@ DisResult disInstr_AMD64_WRK ( SSE2 as a minimum so there is no point distinguishing SSE1 vs SSE2. */ - insn = (UChar*)&guest_code[delta]; + insn = &guest_code[delta]; /* FXSAVE is spuriously at the start here only because it is thusly placed in guest-x86/toIR.c. */ @@ -31757,7 +31757,7 @@ DisResult disInstr_AMD64 ( IRSB* irsb_IN, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code_IN, + const UChar* guest_code_IN, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_arm64_defs.h b/VEX/priv/guest_arm64_defs.h index 7d772c831d..5656786ccc 100644 --- a/VEX/priv/guest_arm64_defs.h +++ b/VEX/priv/guest_arm64_defs.h @@ -44,7 +44,7 @@ DisResult disInstr_ARM64 ( IRSB* irbb, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index 15b71eb595..2aa145cc92 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -152,7 +152,7 @@ static IRSB* irsb; /* Do a little-endian load of a 32-bit word, regardless of the endianness of the underlying host. */ -static inline UInt getUIntLittleEndianly ( UChar* p ) +static inline UInt getUIntLittleEndianly ( const UChar* p ) { UInt w = 0; w = (w << 8) | p[3]; @@ -11230,7 +11230,7 @@ Bool disInstr_ARM64_WRK ( Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_instr, + const UChar* guest_instr, VexArchInfo* archinfo, VexAbiInfo* abiinfo ) @@ -11271,7 +11271,7 @@ Bool disInstr_ARM64_WRK ( /* Spot "Special" instructions (see comment at top of file). */ { - UChar* code = (UChar*)guest_instr; + const UChar* code = guest_instr; /* Spot the 16-byte preamble: 93CC0D8C ror x12, x12, #3 93CC358C ror x12, x12, #13 @@ -11409,7 +11409,7 @@ DisResult disInstr_ARM64 ( IRSB* irsb_IN, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code_IN, + const UChar* guest_code_IN, Long delta_IN, Addr64 guest_IP, VexArch guest_arch, @@ -11436,7 +11436,7 @@ DisResult disInstr_ARM64 ( IRSB* irsb_IN, /* Try to decode */ Bool ok = disInstr_ARM64_WRK( &dres, resteerOkFn, resteerCisOk, callback_opaque, - (UChar*)&guest_code_IN[delta_IN], + &guest_code_IN[delta_IN], archinfo, abiinfo ); if (ok) { /* All decode successes end up here. */ @@ -11461,7 +11461,7 @@ DisResult disInstr_ARM64 ( IRSB* irsb_IN, Int i, j; UChar buf[64]; UInt insn - = getUIntLittleEndianly( (UChar*)&guest_code_IN[delta_IN] ); + = getUIntLittleEndianly( &guest_code_IN[delta_IN] ); vex_bzero(buf, sizeof(buf)); for (i = j = 0; i < 32; i++) { if (i > 0) { diff --git a/VEX/priv/guest_arm_defs.h b/VEX/priv/guest_arm_defs.h index ce1801707c..a931644327 100644 --- a/VEX/priv/guest_arm_defs.h +++ b/VEX/priv/guest_arm_defs.h @@ -46,7 +46,7 @@ DisResult disInstr_ARM ( IRSB* irbb, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index ab2bfe522b..abe9c3a035 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -190,7 +190,7 @@ static IRTemp r15kind; /* Do a little-endian load of a 32-bit word, regardless of the endianness of the underlying host. */ -static inline UInt getUIntLittleEndianly ( UChar* p ) +static inline UInt getUIntLittleEndianly ( const UChar* p ) { UInt w = 0; w = (w << 8) | p[3]; @@ -202,7 +202,7 @@ static inline UInt getUIntLittleEndianly ( UChar* p ) /* Do a little-endian load of a 16-bit word, regardless of the endianness of the underlying host. */ -static inline UShort getUShortLittleEndianly ( UChar* p ) +static inline UShort getUShortLittleEndianly ( const UChar* p ) { UShort w = 0; w = (w << 8) | p[1]; @@ -14546,7 +14546,7 @@ DisResult disInstr_ARM_WRK ( Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_instr, + const UChar* guest_instr, VexArchInfo* archinfo, VexAbiInfo* abiinfo, Bool sigill_diag @@ -14595,7 +14595,7 @@ DisResult disInstr_ARM_WRK ( /* Spot "Special" instructions (see comment at top of file). */ { - UChar* code = (UChar*)guest_instr; + const UChar* code = guest_instr; /* Spot the 16-byte preamble: e1a0c1ec mov r12, r12, ROR #3 @@ -17378,7 +17378,7 @@ DisResult disInstr_THUMB_WRK ( Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_instr, + const UChar* guest_instr, VexArchInfo* archinfo, VexAbiInfo* abiinfo, Bool sigill_diag @@ -17437,7 +17437,7 @@ DisResult disInstr_THUMB_WRK ( /* ----------------------------------------------------------- */ /* Spot "Special" instructions (see comment at top of file). */ { - UChar* code = (UChar*)guest_instr; + const UChar* code = guest_instr; /* Spot the 16-byte preamble: ea4f 0cfc mov.w ip, ip, ror #3 @@ -21974,7 +21974,7 @@ DisResult disInstr_ARM ( IRSB* irsb_IN, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code_IN, + const UChar* guest_code_IN, Long delta_ENCODED, Addr64 guest_IP_ENCODED, VexArch guest_arch, diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c index 76d0d43b25..38681207c1 100644 --- a/VEX/priv/guest_generic_bb_to_IR.c +++ b/VEX/priv/guest_generic_bb_to_IR.c @@ -183,7 +183,7 @@ IRSB* bb_to_IR ( /*OUT*/UInt* n_guest_instrs, /* stats only */ /*IN*/ void* callback_opaque, /*IN*/ DisOneInstrFn dis_instr_fn, - /*IN*/ UChar* guest_code, + /*IN*/ const UChar* guest_code, /*IN*/ Addr64 guest_IP_bbstart, /*IN*/ Bool (*chase_into_ok)(void*,Addr64), /*IN*/ VexEndness host_endness, diff --git a/VEX/priv/guest_generic_bb_to_IR.h b/VEX/priv/guest_generic_bb_to_IR.h index e06bd27f16..f0b9f760da 100644 --- a/VEX/priv/guest_generic_bb_to_IR.h +++ b/VEX/priv/guest_generic_bb_to_IR.h @@ -137,7 +137,7 @@ typedef /*IN*/ void* callback_opaque, /* Where is the guest code? */ - /*IN*/ UChar* guest_code, + /*IN*/ const UChar* guest_code, /* Where is the actual insn? Note: it's at &guest_code[delta] */ /*IN*/ Long delta, @@ -173,7 +173,7 @@ IRSB* bb_to_IR ( /*OUT*/UInt* n_guest_instrs, /* stats only */ /*IN*/ void* callback_opaque, /*IN*/ DisOneInstrFn dis_instr_fn, - /*IN*/ UChar* guest_code, + /*IN*/ const UChar* guest_code, /*IN*/ Addr64 guest_IP_bbstart, /*IN*/ Bool (*chase_into_ok)(void*,Addr64), /*IN*/ VexEndness host_endness, diff --git a/VEX/priv/guest_mips_defs.h b/VEX/priv/guest_mips_defs.h index 1092aca73a..c540c15673 100644 --- a/VEX/priv/guest_mips_defs.h +++ b/VEX/priv/guest_mips_defs.h @@ -45,7 +45,7 @@ extern DisResult disInstr_MIPS ( IRSB* irbb, Bool (*resteerOkFn) (void *, Addr64), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index 26d3c71e63..c47ff9280c 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -55,7 +55,7 @@ static VexEndness host_endness; /* Pointer to the guest code area. */ -static UChar *guest_code; +static const UChar *guest_code; /* CONST: The guest address for the instruction currently being translated. */ @@ -423,7 +423,7 @@ static UInt accumulatorGuestRegOffset(UInt acNo) /* Do a endian load of a 32-bit word, regardless of the endianness of the underlying host. */ -static inline UInt getUInt(UChar * p) +static inline UInt getUInt(const UChar * p) { UInt w = 0; #if defined (_MIPSEL) @@ -716,7 +716,7 @@ static UInt get_dspImm(UInt mipsins) return (0x03ff0000 & mipsins) >> 16; } -static Bool branch_or_jump(UChar * addr) +static Bool branch_or_jump(const UChar * addr) { UInt fmt; UInt cins = getUInt(addr); @@ -782,7 +782,7 @@ static Bool branch_or_jump(UChar * addr) return False; } -static Bool is_Branch_or_Jump_and_Link(UChar * addr) +static Bool is_Branch_or_Jump_and_Link(const UChar * addr) { UInt cins = getUInt(addr); @@ -813,7 +813,7 @@ static Bool is_Branch_or_Jump_and_Link(UChar * addr) return False; } -static Bool branch_or_link_likely(UChar * addr) +static Bool branch_or_link_likely(const UChar * addr) { UInt cins = getUInt(addr); UInt opcode = get_opcode(cins); @@ -12045,7 +12045,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, delay_slot_branch = likely_delay_slot = delay_slot_jump = False; - UChar *code = (UChar *) (guest_code + delta); + const UChar *code = guest_code + delta; cins = getUInt(code); DIP("\t0x%lx:\t0x%08x\t", (long)guest_PC_curr_instr, cins); @@ -17242,7 +17242,7 @@ DisResult disInstr_MIPS( IRSB* irsb_IN, Bool (*resteerOkFn) ( void *, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code_IN, + const UChar* guest_code_IN, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h index 3d677e8eea..25d9fe3aa0 100644 --- a/VEX/priv/guest_ppc_defs.h +++ b/VEX/priv/guest_ppc_defs.h @@ -55,7 +55,7 @@ DisResult disInstr_PPC ( IRSB* irbb, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 8c1e70a3f9..60c52fe8e5 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -205,7 +205,7 @@ static VexEndness host_endness; /* Pointer to the guest code area. */ -static UChar* guest_code; +static const UChar* guest_code; /* The guest address corresponding to guest_code[0]. */ static Addr64 guest_CIA_bbstart; @@ -553,7 +553,7 @@ static ULong extend_s_32to64 ( UInt x ) /* Do a proper-endian load of a 32-bit word, regardless of the endianness of the underlying host. */ -static UInt getUIntPPCendianly ( UChar* p ) +static UInt getUIntPPCendianly ( const UChar* p ) { UInt w = 0; if (host_endness == VexEndnessBE) { @@ -18756,7 +18756,7 @@ DisResult disInstr_PPC_WRK ( /* At least this is simple on PPC32: insns are all 4 bytes long, and 4-aligned. So just fish the whole thing out of memory right now and have done. */ - theInstr = getUIntPPCendianly( (UChar*)(&guest_code[delta]) ); + theInstr = getUIntPPCendianly( &guest_code[delta] ); if (0) vex_printf("insn: 0x%x\n", theInstr); @@ -18764,7 +18764,7 @@ DisResult disInstr_PPC_WRK ( /* Spot "Special" instructions (see comment at top of file). */ { - UChar* code = (UChar*)(guest_code + delta); + const UChar* code = guest_code + delta; /* Spot the 16-byte preamble: 32-bit mode: 5400183E rlwinm 0,0,3,0,31 @@ -19555,7 +19555,7 @@ DisResult disInstr_PPC_WRK ( case 0x32E: case 0x34E: case 0x36E: // tabortdc., tabortwci., tabortdci. case 0x38E: case 0x3AE: case 0x3EE: // tabort., treclaim., trechkpt. if (dis_transactional_memory( theInstr, - getUIntPPCendianly( (UChar*)(&guest_code[delta + 4])), + getUIntPPCendianly( &guest_code[delta + 4]), abiinfo, &dres, resteerOkFn, callback_opaque)) goto decode_success; @@ -20169,7 +20169,7 @@ DisResult disInstr_PPC ( IRSB* irsb_IN, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code_IN, + const UChar* guest_code_IN, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h index 6aca7f530f..97c2a02320 100644 --- a/VEX/priv/guest_s390_defs.h +++ b/VEX/priv/guest_s390_defs.h @@ -44,7 +44,7 @@ DisResult disInstr_S390 ( IRSB* irbb, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 65cd0e9811..ec7e370ad2 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -48,7 +48,7 @@ /*------------------------------------------------------------*/ /*--- Forward declarations ---*/ /*------------------------------------------------------------*/ -static UInt s390_decode_and_irgen(UChar *, UInt, DisResult *); +static UInt s390_decode_and_irgen(const UChar *, UInt, DisResult *); static void s390_irgen_xonc(IROp, IRTemp, IRTemp, IRTemp); static void s390_irgen_CLC_EX(IRTemp, IRTemp, IRTemp); @@ -13904,7 +13904,7 @@ s390_irgen_call_noredir(void) static s390_decode_t -s390_decode_2byte_and_irgen(UChar *bytes) +s390_decode_2byte_and_irgen(const UChar *bytes) { typedef union { struct { @@ -14037,7 +14037,7 @@ unimplemented: } static s390_decode_t -s390_decode_4byte_and_irgen(UChar *bytes) +s390_decode_4byte_and_irgen(const UChar *bytes) { typedef union { struct { @@ -15091,7 +15091,7 @@ unimplemented: } static s390_decode_t -s390_decode_6byte_and_irgen(UChar *bytes) +s390_decode_6byte_and_irgen(const UChar *bytes) { typedef union { struct { @@ -16356,7 +16356,7 @@ unimplemented: /* Handle "special" instructions. */ static s390_decode_t -s390_decode_special_and_irgen(UChar *bytes) +s390_decode_special_and_irgen(const UChar *bytes) { s390_decode_t status = S390_DECODE_OK; @@ -16397,7 +16397,7 @@ s390_decode_special_and_irgen(UChar *bytes) /* Function returns # bytes that were decoded or 0 in case of failure */ static UInt -s390_decode_and_irgen(UChar *bytes, UInt insn_length, DisResult *dres) +s390_decode_and_irgen(const UChar *bytes, UInt insn_length, DisResult *dres) { s390_decode_t status; @@ -16488,7 +16488,7 @@ s390_decode_and_irgen(UChar *bytes, UInt insn_length, DisResult *dres) /* Disassemble a single instruction INSN into IR. */ static DisResult -disInstr_S390_WRK(UChar *insn) +disInstr_S390_WRK(const UChar *insn) { UChar byte; UInt insn_length; @@ -16572,7 +16572,7 @@ disInstr_S390(IRSB *irsb_IN, Bool (*resteerOkFn)(void *, Addr64), Bool resteerCisOk, void *callback_opaque, - UChar *guest_code, + const UChar *guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_x86_defs.h b/VEX/priv/guest_x86_defs.h index e7bc53094f..dd030566f9 100644 --- a/VEX/priv/guest_x86_defs.h +++ b/VEX/priv/guest_x86_defs.h @@ -54,7 +54,7 @@ DisResult disInstr_X86 ( IRSB* irbb, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code, + const UChar* guest_code, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c index 7f492e899c..1defdcb467 100644 --- a/VEX/priv/guest_x86_toIR.c +++ b/VEX/priv/guest_x86_toIR.c @@ -199,7 +199,7 @@ static VexEndness host_endness; /* Pointer to the guest code area (points to start of BB, not to the insn being processed). */ -static UChar* guest_code; +static const UChar* guest_code; /* The guest address corresponding to guest_code[0]. */ static Addr32 guest_EIP_bbstart; @@ -405,7 +405,7 @@ static UInt getSDisp8 ( Int delta ) static UInt getSDisp16 ( Int delta0 ) { - UChar* eip = (UChar*)(&guest_code[delta0]); + const UChar* eip = &guest_code[delta0]; UInt d = *eip++; d |= ((*eip++) << 8); return extend_s_16to32(d); @@ -7940,7 +7940,7 @@ static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr ) Same for BTS, BTR */ -static Bool can_be_used_with_LOCK_prefix ( UChar* opc ) +static Bool can_be_used_with_LOCK_prefix ( const UChar* opc ) { switch (opc[0]) { case 0x00: case 0x01: case 0x08: case 0x09: @@ -8078,7 +8078,7 @@ DisResult disInstr_X86_WRK ( HChar dis_buf[50]; Int am_sz, d_sz, n_prefixes; DisResult dres; - UChar* insn; /* used in SSE decoders */ + const UChar* insn; /* used in SSE decoders */ /* The running delta */ Int delta = (Int)delta64; @@ -8114,7 +8114,7 @@ DisResult disInstr_X86_WRK ( /* Spot "Special" instructions (see comment at top of file). */ { - UChar* code = (UChar*)(guest_code + delta); + const UChar* code = guest_code + delta; /* Spot the 12-byte preamble: C1C703 roll $3, %edi C1C70D roll $13, %edi @@ -8186,7 +8186,7 @@ DisResult disInstr_X86_WRK ( /* Handle a couple of weird-ass NOPs that have been observed in the wild. */ { - UChar* code = (UChar*)(guest_code + delta); + const UChar* code = guest_code + delta; /* Sun's JVM 1.5.0 uses the following as a NOP: 26 2E 64 65 90 %es:%cs:%fs:%gs:nop */ if (code[0] == 0x26 && code[1] == 0x2E && code[2] == 0x64 @@ -8282,7 +8282,7 @@ DisResult disInstr_X86_WRK ( allowed. */ if (pfx_lock) { - if (can_be_used_with_LOCK_prefix( (UChar*)&guest_code[delta] )) { + if (can_be_used_with_LOCK_prefix( &guest_code[delta] )) { DIP("lock "); } else { *expect_CAS = False; @@ -8301,7 +8301,7 @@ DisResult disInstr_X86_WRK ( /* Note, this doesn't handle SSE2 or SSE3. That is handled in a later section, further on. */ - insn = (UChar*)&guest_code[delta]; + insn = &guest_code[delta]; /* Treat fxsave specially. It should be doable even on an SSE0 (Pentium-II class) CPU. Hence be prepared to handle it on @@ -9537,7 +9537,7 @@ DisResult disInstr_X86_WRK ( if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2)) goto after_sse_decoders; /* no SSE2 capabilities */ - insn = (UChar*)&guest_code[delta]; + insn = &guest_code[delta]; /* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */ if (sz == 2 && insn[0] == 0x0F && insn[1] == 0x58) { @@ -11784,7 +11784,7 @@ DisResult disInstr_X86_WRK ( if (0 == (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2)) goto after_sse_decoders; /* no SSE3 capabilities */ - insn = (UChar*)&guest_code[delta]; + insn = &guest_code[delta]; /* F3 0F 12 = MOVSLDUP -- move from E (mem or xmm) to G (xmm), duplicating some lanes (2:2:0:0). */ @@ -15415,7 +15415,7 @@ DisResult disInstr_X86 ( IRSB* irsb_IN, Bool (*resteerOkFn) ( void*, Addr64 ), Bool resteerCisOk, void* callback_opaque, - UChar* guest_code_IN, + const UChar* guest_code_IN, Long delta, Addr64 guest_IP, VexArch guest_arch, diff --git a/VEX/priv/host_amd64_defs.c b/VEX/priv/host_amd64_defs.c index f13a35f48d..434d870637 100644 --- a/VEX/priv/host_amd64_defs.c +++ b/VEX/priv/host_amd64_defs.c @@ -2266,10 +2266,10 @@ static UChar* do_ffree_st ( UChar* p, Int n ) Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, AMD64Instr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ) + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ) { UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; UInt xtra; @@ -2762,7 +2762,7 @@ Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, /* movabsq $disp_cp_chain_me_to_{slow,fast}EP,%r11; */ *p++ = 0x49; *p++ = 0xBB; - void* disp_cp_chain_me + const void* disp_cp_chain_me = i->Ain.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP : disp_cp_chain_me_to_slowEP; p = emit64(p, Ptr_to_ULong(disp_cp_chain_me)); diff --git a/VEX/priv/host_amd64_defs.h b/VEX/priv/host_amd64_defs.h index e16ed8e32c..d1c55dd018 100644 --- a/VEX/priv/host_amd64_defs.h +++ b/VEX/priv/host_amd64_defs.h @@ -753,15 +753,15 @@ extern void ppAMD64Instr ( AMD64Instr*, Bool ); extern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bool ); extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); -extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, - AMD64Instr* i, - Bool mode64, - VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ); +extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, + UChar* buf, Int nbuf, + AMD64Instr* i, + Bool mode64, + VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); extern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, HReg rreg, Int offset, Bool ); diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c index d08748e473..38e29fae48 100644 --- a/VEX/priv/host_arm64_defs.c +++ b/VEX/priv/host_arm64_defs.c @@ -3109,10 +3109,10 @@ static UInt* do_load_or_store64 ( UInt* p, Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, ARM64Instr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ) + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ) { UInt* p = (UInt*)buf; vassert(nbuf >= 32); @@ -3387,7 +3387,7 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[47:32], lsl 32 */ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[63:48], lsl 48 */ /* blr x9 */ - void* disp_cp_chain_me + const void* disp_cp_chain_me = i->ARM64in.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP : disp_cp_chain_me_to_slowEP; p = imm64_to_iregNo_EXACTLY4(p, /*x*/9, diff --git a/VEX/priv/host_arm64_defs.h b/VEX/priv/host_arm64_defs.h index 0b37338a26..d5fffa63cc 100644 --- a/VEX/priv/host_arm64_defs.h +++ b/VEX/priv/host_arm64_defs.h @@ -924,10 +924,10 @@ extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, ARM64Instr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ); + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); extern void genSpill_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, HReg rreg, Int offset, Bool ); diff --git a/VEX/priv/host_arm_defs.c b/VEX/priv/host_arm_defs.c index 98e3c11ae9..ca7bad01ed 100644 --- a/VEX/priv/host_arm_defs.c +++ b/VEX/priv/host_arm_defs.c @@ -2972,10 +2972,10 @@ static UInt* do_load_or_store32 ( UInt* p, Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, ARMInstr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ) + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ) { UInt* p = (UInt*)buf; vassert(nbuf >= 32); @@ -3238,7 +3238,7 @@ Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, /* movw r12, lo16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */ /* movt r12, hi16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */ /* blx r12 (A1) */ - void* disp_cp_chain_me + const void* disp_cp_chain_me = i->ARMin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP : disp_cp_chain_me_to_slowEP; p = imm32_to_iregNo_EXACTLY2(p, /*r*/12, diff --git a/VEX/priv/host_arm_defs.h b/VEX/priv/host_arm_defs.h index 15316c4d56..d9d8c38dc2 100644 --- a/VEX/priv/host_arm_defs.h +++ b/VEX/priv/host_arm_defs.h @@ -1028,10 +1028,10 @@ extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, ARMInstr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ); + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); extern void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, HReg rreg, Int offset, Bool ); diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c index 28663c2b72..2d316c008f 100644 --- a/VEX/priv/host_mips_defs.c +++ b/VEX/priv/host_mips_defs.c @@ -2921,10 +2921,10 @@ Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, MIPSInstr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ) + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ) { UChar *p = &buf[0]; UChar *ptmp = p; @@ -3439,7 +3439,7 @@ Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc, number of instructions (3) below. */ /* move r9, VG_(disp_cp_chain_me_to_{slowEP,fastEP}) */ /* jr r9 */ - void* disp_cp_chain_me + const void* disp_cp_chain_me = i->Min.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP : disp_cp_chain_me_to_slowEP; p = mkLoadImm_EXACTLY2or6(p, /*r*/ 9, diff --git a/VEX/priv/host_mips_defs.h b/VEX/priv/host_mips_defs.h index f3039938e4..19dc798dce 100644 --- a/VEX/priv/host_mips_defs.h +++ b/VEX/priv/host_mips_defs.h @@ -712,14 +712,14 @@ extern void ppMIPSInstr(MIPSInstr *, Bool mode64); extern void getRegUsage_MIPSInstr (HRegUsage *, MIPSInstr *, Bool); extern void mapRegs_MIPSInstr (HRegRemap *, MIPSInstr *, Bool mode64); extern Bool isMove_MIPSInstr (MIPSInstr *, HReg *, HReg *); -extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, MIPSInstr* i, - Bool mode64, - VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ); +extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc, + UChar* buf, Int nbuf, MIPSInstr* i, + Bool mode64, + VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); extern void genSpill_MIPS ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, Int offset, Bool); diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c index e4c8b91415..dc7faddf39 100644 --- a/VEX/priv/host_ppc_defs.c +++ b/VEX/priv/host_ppc_defs.c @@ -3751,10 +3751,10 @@ static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2, Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, PPCInstr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted) + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted) { UChar* p = &buf[0]; vassert(nbuf >= 32); @@ -4208,7 +4208,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, the first patchable byte. So: don't change the number of instructions (32-bit: 4, 64-bit: 7) below. */ /* imm32/64-fixed r30, VG_(disp_cp_chain_me_to_{slowEP,fastEP} */ - void* disp_cp_chain_me + const void* disp_cp_chain_me = i->Pin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP : disp_cp_chain_me_to_slowEP; p = mkLoadImm_EXACTLY2or5( diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index c32eea5a4c..e4493523fc 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -1135,14 +1135,14 @@ extern void ppPPCInstr(PPCInstr*, Bool mode64); extern void getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 ); extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* ); -extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, PPCInstr* i, - Bool mode64, - VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ); +extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, + UChar* buf, Int nbuf, PPCInstr* i, + Bool mode64, + VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ); diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index bf178f83df..9b18f46507 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -9601,8 +9601,8 @@ s390_tchain_patch_load64(UChar *code, ULong imm64) chainXDirect_S390 and unchainXDirect_S390 below. */ static UChar * s390_insn_xdirect_emit(UChar *buf, const s390_insn *insn, - void *disp_cp_chain_me_to_slowEP, - void *disp_cp_chain_me_to_fastEP) + const void *disp_cp_chain_me_to_slowEP, + const void *disp_cp_chain_me_to_fastEP) { /* We're generating chain-me requests here, so we need to be sure this is actually allowed -- no-redir translations can't @@ -9641,7 +9641,7 @@ s390_insn_xdirect_emit(UChar *buf, const s390_insn *insn, buf = s390_emit_STG(buf, R0, 0, b, DISP20(d)); /* Load the chosen entry point into the scratch reg */ - void *disp_cp_chain_me; + const void *disp_cp_chain_me; disp_cp_chain_me = insn->variant.xdirect.to_fast_entry ? disp_cp_chain_me_to_fastEP @@ -9681,7 +9681,8 @@ s390_xdirect_patchable_len(void) static UChar * -s390_insn_xindir_emit(UChar *buf, const s390_insn *insn, void *disp_cp_xindir) +s390_insn_xindir_emit(UChar *buf, const s390_insn *insn, + const void *disp_cp_xindir) { /* We're generating transfers that could lead indirectly to a chain-me, so we need to be sure this is actually allowed -- @@ -9741,7 +9742,7 @@ s390_insn_xindir_emit(UChar *buf, const s390_insn *insn, void *disp_cp_xindir) static UChar * s390_insn_xassisted_emit(UChar *buf, const s390_insn *insn, - void *disp_cp_xassisted) + const void *disp_cp_xassisted) { /* Use ptmp for backpatching conditional jumps. */ UChar *ptmp = buf; @@ -9898,9 +9899,10 @@ s390_insn_profinc_emit(UChar *buf, Int emit_S390Instr(Bool *is_profinc, UChar *buf, Int nbuf, s390_insn *insn, Bool mode64, VexEndness endness_host, - void *disp_cp_chain_me_to_slowEP, - void *disp_cp_chain_me_to_fastEP, void *disp_cp_xindir, - void *disp_cp_xassisted) + const void *disp_cp_chain_me_to_slowEP, + const void *disp_cp_chain_me_to_fastEP, + const void *disp_cp_xindir, + const void *disp_cp_xassisted) { UChar *end; diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h index 8706a6c706..4884c5b129 100644 --- a/VEX/priv/host_s390_defs.h +++ b/VEX/priv/host_s390_defs.h @@ -736,7 +736,8 @@ void getRegUsage_S390Instr( HRegUsage *, s390_insn *, Bool ); void mapRegs_S390Instr ( HRegRemap *, s390_insn *, Bool ); Bool isMove_S390Instr ( s390_insn *, HReg *, HReg * ); Int emit_S390Instr ( Bool *, UChar *, Int, s390_insn *, Bool, - VexEndness, void *, void *, void *, void *); + VexEndness, const void *, const void *, + const void *, const void *); void getAllocableRegs_S390( Int *, HReg **, Bool ); void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); diff --git a/VEX/priv/host_x86_defs.c b/VEX/priv/host_x86_defs.c index 3a5546d12e..b77d58a3eb 100644 --- a/VEX/priv/host_x86_defs.c +++ b/VEX/priv/host_x86_defs.c @@ -2103,10 +2103,10 @@ static UChar* push_word_from_tags ( UChar* p, UShort tags ) Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, UChar* buf, Int nbuf, X86Instr* i, Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ) + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ) { UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; @@ -2465,7 +2465,7 @@ Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, two instructions below. */ /* movl $disp_cp_chain_me_to_{slow,fast}EP,%edx; */ *p++ = 0xBA; - void* disp_cp_chain_me + const void* disp_cp_chain_me = i->Xin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP : disp_cp_chain_me_to_slowEP; p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_chain_me)); diff --git a/VEX/priv/host_x86_defs.h b/VEX/priv/host_x86_defs.h index a2c71076d1..af344179c7 100644 --- a/VEX/priv/host_x86_defs.h +++ b/VEX/priv/host_x86_defs.h @@ -714,14 +714,14 @@ extern void ppX86Instr ( X86Instr*, Bool ); extern void getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool ); extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool ); extern Bool isMove_X86Instr ( X86Instr*, HReg*, HReg* ); -extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, X86Instr* i, - Bool mode64, - VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, - void* disp_cp_xassisted ); +extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, + UChar* buf, Int nbuf, X86Instr* i, + Bool mode64, + VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, + const void* disp_cp_chain_me_to_fastEP, + const void* disp_cp_xindir, + const void* disp_cp_xassisted ); extern void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, HReg rreg, Int offset, Bool ); diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index bd29019a6b..98ab2d213d 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -222,7 +222,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) Int, Int, Bool, Bool, Addr64 ); Int (*emit) ( /*MB_MOD*/Bool*, UChar*, Int, HInstr*, Bool, VexEndness, - void*, void*, void*, void* ); + const void*, const void*, const void*, + const void* ); IRExpr* (*specHelper) ( const HChar*, IRExpr**, IRStmt**, Int ); Bool (*preciseMemExnsFn) ( Int, Int ); @@ -308,7 +309,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegX86; iselSB = iselSB_X86; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_X86Instr; host_word_type = Ity_I32; vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); @@ -331,7 +333,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegAMD64; iselSB = iselSB_AMD64; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_AMD64Instr; host_word_type = Ity_I64; vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); @@ -351,7 +354,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegPPC; iselSB = iselSB_PPC; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_PPCInstr; host_word_type = Ity_I32; vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); @@ -371,7 +375,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegPPC; iselSB = iselSB_PPC; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_PPCInstr; host_word_type = Ity_I64; vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); @@ -392,7 +397,9 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegS390; iselSB = iselSB_S390; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) emit_S390Instr; + const void*,const void*,const void*, + const void*)) + emit_S390Instr; host_word_type = Ity_I64; vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps)); vassert(vta->archinfo_host.endness == VexEndnessBE); @@ -411,7 +418,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegARM; iselSB = iselSB_ARM; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_ARMInstr; host_word_type = Ity_I32; vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); @@ -435,7 +443,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegARM64; iselSB = iselSB_ARM64; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_ARM64Instr; host_word_type = Ity_I64; vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_host.hwcaps)); @@ -455,7 +464,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegMIPS; iselSB = iselSB_MIPS; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_MIPSInstr; host_word_type = Ity_I32; vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps)); @@ -476,7 +486,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) ppReg = (void(*)(HReg)) ppHRegMIPS; iselSB = iselSB_MIPS; emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) + const void*,const void*,const void*, + const void*)) emit_MIPSInstr; host_word_type = Ity_I64; vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_host.hwcaps)); @@ -754,7 +765,7 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) vex_printf("can't show code due to extents > 1\n"); } else { /* HACK */ - UChar* p = (UChar*)vta->guest_bytes; + const UChar* p = vta->guest_bytes; UInt sum = 0; UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index b1f18076be..7ebe26fa0a 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -642,7 +642,7 @@ typedef /* IN: the block to translate, and its guest address. */ /* where are the actual bytes in the host's address space? */ - UChar* guest_bytes; + const UChar* guest_bytes; /* where do the bytes really come from in the guest's aspace? This is the post-redirection guest address. Not that Vex understands anything about redirection; that is all done on @@ -743,10 +743,10 @@ typedef FIXME: update this comment */ - void* disp_cp_chain_me_to_slowEP; - void* disp_cp_chain_me_to_fastEP; - void* disp_cp_xindir; - void* disp_cp_xassisted; + const void* disp_cp_chain_me_to_slowEP; + const void* disp_cp_chain_me_to_fastEP; + const void* disp_cp_xindir; + const void* disp_cp_xassisted; } VexTranslateArgs;