From: Carl Love <cel@us.ibm.com>
Date: Tue, 7 Oct 2014 18:20:39 +0000 (+0000)
Subject: This commit just makes white space changes to the three files in commit
X-Git-Tag: svn/VALGRIND_3_11_0^2~184
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f3712383cd26ccbf55e3629f7c8a66f1d392e804;p=thirdparty%2Fvalgrind.git

This commit just makes white space changes to the three files in commit
r2966 so I can fix the commit message for that commit.  The previous
commit message was "msg".  The "msg" was the file with the commit message below.

The first attempt to fix the false positive message "Invalid read of size"
was to change to a V128 read instead of four 32-bit reads.  Unfortunately,
this caused some regression test failures that were not caught before
committing the change.

This patch implements the V128 read without creating any regression failures.
The issue with the previous fix is that the lvx instruction was used to
do the V128 fetch.  Unfortunately, that instruction takes the effective
address masks it to make it 16 byte aligned and then does the fetch.  So,
non-aligned fetches do not work correctly.  The fix in this patch does
two aligned fetches with the lvx instruction, calculates a how to permute
the data from the two loads and then permutes the data so the result in the
vector register is the correct value for an unaligned fetch.

The fix is for bugzilla 339433.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2967
---

diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
index 183e577007..560c51d251 100644
--- a/VEX/priv/host_ppc_defs.c
+++ b/VEX/priv/host_ppc_defs.c
@@ -1427,7 +1427,7 @@ PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ) {
    return i;
 }
 PPCInstr* PPCInstr_AvSh ( Bool shLeft, HReg dst, PPCAMode* addr ) {
-   PPCInstr* i        = LibVEX_Alloc(sizeof(PPCInstr));
+   PPCInstr*  i       = LibVEX_Alloc(sizeof(PPCInstr));
    i->tag             = Pin_AvSh;
    i->Pin.AvSh.shLeft = shLeft;
    i->Pin.AvSh.dst    = dst;
@@ -5277,7 +5277,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
       r_base = iregNo(i->Pin.AvSh.addr->Pam.RR.base, mode64);
 
       if (!idxd) {
-         r_idx = 30;                       // XXX: Using r30 as temp
+         r_idx = 30; // XXX: Using r30 as temp
          p = mkLoadImm(p, r_idx,
                        i->Pin.AvSh.addr->Pam.IR.index, mode64, endness_host);
       } else {
diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h
index 4aa910ad4f..0525722068 100644
--- a/VEX/priv/host_ppc_defs.h
+++ b/VEX/priv/host_ppc_defs.h
@@ -858,7 +858,7 @@ typedef
          struct {
             Bool  shLeft;
             HReg  dst;
-            PPCAMode*  addr;
+            PPCAMode* addr;
          } AvSh;
          struct {
             UChar shift;
diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index 9e4137faeb..7793005296 100644
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -4871,7 +4871,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
    }
 
    if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) {
-      /* Need to be able to do V128 unaligned loads.  The unaligned load can
+      /* Need to be able to do V128 unaligned loads. The unaligned load can
        * be accomplised using the following code sequece from the ISA.  It
        * uses the lvx instruction that does two aligned loads and then
        * permute the data to store the required data as if it had been an