From: Kaustabh Chakraborty Date: Fri, 1 Nov 2024 02:31:10 +0000 (+0900) Subject: drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz X-Git-Tag: v6.13-rc1~122^2~9^2~2 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f3cb045e2603e80a1633883423b2621aad77989d;p=thirdparty%2Fkernel%2Flinux.git drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz The clkdiv values are incorrect as ideal_clk is in kHz and the clock rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae --- diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index e994779694f03..76a3f4b0341df 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx) static u32 decon_calc_clkdiv(struct decon_context *ctx, const struct drm_display_mode *mode) { - unsigned long ideal_clk = mode->clock; + unsigned long ideal_clk = mode->clock * 1000; u32 clkdiv; /* Find the clock divider value that gets us closest to ideal_clk */