From: Max Filippov Date: Fri, 27 Apr 2018 20:07:53 +0000 (-0700) Subject: target/xtensa: check zero overhead loop alignment X-Git-Tag: v3.0.0-rc0~41^2~5 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f40385c959d01bf33a0e3c12ef0fdb402ad98a1c;p=thirdparty%2Fqemu.git target/xtensa: check zero overhead loop alignment ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov --- diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e9d2e109f79..51b45514649 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -369,6 +369,7 @@ struct XtensaConfig { unsigned nareg; int excm_level; int ndepc; + unsigned inst_fetch_width; uint32_t vecbase; uint32_t exception_vector[EXC_MAX]; unsigned ninterrupt; diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index b24ad11fec1..ee37a04a176 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -456,6 +456,7 @@ .options = XTENSA_OPTIONS, \ .nareg = XCHAL_NUM_AREGS, \ .ndepc = (XCHAL_XEA_VERSION >= 2), \ + .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \ EXCEPTIONS_SECTION, \ INTERRUPTS_SECTION, \ TLB_SECTION, \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a11162eebe0..7dd8b55d4a5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -970,6 +970,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } dc->next_pc = dc->pc + len; + if (xtensa_option_enabled(dc->config, XTENSA_OPTION_LOOP) && + dc->lbeg == dc->pc && + ((dc->pc ^ (dc->next_pc - 1)) & -dc->config->inst_fetch_width)) { + qemu_log_mask(LOG_GUEST_ERROR, + "unaligned first instruction of a loop (pc = %08x)\n", + dc->pc); + } for (i = 1; i < len; ++i) { b[i] = cpu_ldub_code(env, dc->pc + i); }