From: Primoz Fiser Date: Tue, 8 Jul 2025 04:22:06 +0000 (+0200) Subject: arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay X-Git-Tag: v6.17-rc1~172^2~19^2~15 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f478e7ae181730966601e420e44d534aab1a0b9e;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay Add overlay to support PHYTEC PEB-WLBT-07 WiFi/Bluetooth evaluation adapter on phyBOARD-Nash-i.MX93 board. Adapter uses the u-blox MAYA-W2 module (IW612 chipset) which is capable of Wi-Fi 6 and Bluetooth 5.4 LE. Signed-off-by: Primoz Fiser Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 44736435700f9..784fbcd40175c 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -333,9 +333,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb +imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso new file mode 100644 index 0000000000000..7381b87444e8a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash-peb-wlbt-07.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx93-pinfunc.h" + +&{/} { + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; +}; + +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* + * NOTE: When uSDHC3 port is multiplexed on GPIO_IO[27:22] pads, it only + * supports 50 MHz mode, due to introduction of potential variations in + * trace impedance, drive strength, and timing skew. Refer to i.MX 93 + * Application Processors Data Sheet, Rev. 3, page 60 for more details. + */ +&usdhc3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wlbt>; + pinctrl-1 = <&pinctrl_usdhc3_sleep>, <&pinctrl_wlbt>; + mmc-pwrseq = <&usdhc3_pwrseq>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000178e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + pinctrl_usdhc3_sleep: usdhc3sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__USDHC3_CLK 0x31e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x31e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x31e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x31e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x31e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x31e + >; + }; + + pinctrl_wlbt: wlbtgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* WAKE_DEV */ + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* WAKE_HOST */ + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* PDn */ + >; + }; +};