From: Tom Rini Date: Thu, 31 Jul 2025 14:45:50 +0000 (-0600) Subject: Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f5e968a28e7cdc2c4365f5a382e02f074ee03fac;p=thirdparty%2Fu-boot.git Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236 - Add support for STM32 TIMERS and STM32 PWM on STM32MP25 - Add STM32MP13xx SPL and OpTee-OS start support - Fix header misuse in stm32 reset drivers - Fix STMicroelectronics spelling - Fix clk-stm32h7 wrong macros used in register read - Fix PRE_CON_BUF_ADDR on STM32MP13 - Fix clock identifier passed to struct scmi_clk_parent_set_in - Fix stm32 reset for STM32F4/F7 and H7 - Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig - Add STM32MP23 SoC and stm32mp235f-dk board support --- f5e968a28e7cdc2c4365f5a382e02f074ee03fac diff --cc arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index 9ff42ab8248,f76fe63281b..699ba15d6ea --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@@ -48,6 -54,138 +54,138 @@@ }; }; + &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + }; + + &qspi { + bootph-all; + }; + + &qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; + }; + + &qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; + }; + + &qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; + }; + }; + + &pinctrl { + bootph-all; + i2c3_pins_a: i2c3-0 { - bootph-all; ++ bootph-all; + pins { + bootph-all; + pinmux = , /* I2C3_SCL */ + ; /* I2C3_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + }; + + #if !defined(CONFIG_TFABOOT) + &rcc { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; + + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_CKPER_HSE + CLK_RTC_LSE + CLK_MCO1_LSI + CLK_MCO2_HSI + >; + + st,clkdiv = < + 0 /*AXI*/ + 0 /*MLHAB*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 1 /*APB6*/ + 0 /*RTC*/ + >; + + st,pkcs = < + CLK_I2C12_HSI + CLK_I2C3_HSI + CLK_QSPI_PLL3R + CLK_SAES_AXI + CLK_SDMMC1_PLL3R + CLK_SDMMC2_PLL3R + CLK_STGEN_HSE + CLK_UART2_HSI + CLK_UART4_HSI + CLK_USBO_USBPHY + CLK_USBPHY_HSE + >; + + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 1 0 PQR(1,1,1) >; + frac = < 0x1400 >; + bootph-all; + }; + + /* VCO = 600 MHz => P = 200, Q = 150, R = 200 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 2 74 2 3 2 PQR(1,1,1) >; + bootph-all; + }; + + /* VCO = 750.0 MHz => P = 125, Q = 83, R = 75 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 124 5 8 9 PQR(1,1,1) >; + bootph-all; + }; + }; + #endif + &sdmmc1 { status = "disabled"; }; diff --cc configs/stm32mp15_dhsom.config index 565b49584e3,f7ff5db5943..210ec201bf5 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@@ -76,4 -35,10 +35,11 @@@ CONFIG_PREBOOT="run dh_preboot CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_USE_SERVERIP=y +CONFIG_WATCHDOG_AUTOSTART=y + CONFIG_SPI_FLASH_MACRONIX=y + CONFIG_SPI_FLASH_SPANSION=y + CONFIG_SPI_FLASH_STMICRO=y + CONFIG_SPL_LEGACY_IMAGE_FORMAT=y + CONFIG_SPL_TEXT_BASE=0x2FFC2500 + CONFIG_SPL_BLOCK_CACHE=y + CONFIG_SPL_MMC=y