From: Jeff Law <jlaw@ventanamicro.com>
Date: Sun, 4 Jun 2023 17:38:55 +0000 (-0600)
Subject: Convert H8 port to LRA
X-Git-Tag: basepoints/gcc-15~8606
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f66e0a94ad7bc18538c8207fc2c86b62e4a51bb2;p=thirdparty%2Fgcc.git

Convert H8 port to LRA

With Vlad's recent LRA fix to the elimination code, the H8 can be converted
to LRA.

This patch has two changes of note.

First, this turns Zz into a standard constraint.  This helps reloading for
the H8/SX movqi pattern.

Second, this drops the whole pattern for the SX bit memory operations.  I
can't see why those exist to begin with.  They should be handled by the
standard bit manipulation patterns.   If someone wants to try and improve SX
bit support, that'd be great and they can do so within the LRA framework :-)

Pushed to the trunk...

gcc/
	* config/h8300/constraints.md (Zz): Make this a normal
	constraint.
	* config/h8300/h8300.cc (TARGET_LRA_P): Remove.
	* config/h8300/logical.md (H8/SX bit patterns): Remove.
---

diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md
index 3aef1205fef9..3e2526ccbbcc 100644
--- a/gcc/config/h8300/constraints.md
+++ b/gcc/config/h8300/constraints.md
@@ -211,7 +211,7 @@
   (and (match_code "const_int")
        (match_test "exact_log2 (ival & 0xff) != -1")))
 
-(define_special_memory_constraint "Zz"
+(define_constraint "Zz"
   "@internal"
   (and (match_test "TARGET_H8300SX")
        (match_code "mem")
diff --git a/gcc/config/h8300/h8300.cc b/gcc/config/h8300/h8300.cc
index 7412c0535fce..cdf74c1acbd1 100644
--- a/gcc/config/h8300/h8300.cc
+++ b/gcc/config/h8300/h8300.cc
@@ -5625,9 +5625,6 @@ pre_incdec_with_reg (rtx op, unsigned int reg)
 #undef TARGET_MODES_TIEABLE_P
 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
 
-#undef TARGET_LRA_P
-#define TARGET_LRA_P hook_bool_void_false
-
 #undef TARGET_LEGITIMATE_ADDRESS_P
 #define TARGET_LEGITIMATE_ADDRESS_P	h8300_legitimate_address_p
 
diff --git a/gcc/config/h8300/logical.md b/gcc/config/h8300/logical.md
index f07c79e1eac2..5df0922ef4e0 100644
--- a/gcc/config/h8300/logical.md
+++ b/gcc/config/h8300/logical.md
@@ -31,28 +31,6 @@
 ;; AND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "bclr<mode>_msx"
-  [(set (match_operand:QHI 0 "bit_register_indirect_operand" "=WU")
-	(and:QHI (match_operand:QHI 1 "bit_register_indirect_operand" "%0")
-		 (match_operand:QHI 2 "single_zero_operand" "Y0")))]
-  "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
-  "bclr\\t%W2,%0"
-  [(set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:HI 0 "bit_register_indirect_operand")
-	(and:HI (match_operand:HI 1 "bit_register_indirect_operand")
-		(match_operand:HI 2 "single_zero_operand")))]
-  "TARGET_H8300SX && abs (INTVAL (operands[2])) > 0xff"
-  [(set (match_dup 0)
-	(and:QI (match_dup 1)
-		(match_dup 2)))]
-  {
-    operands[0] = adjust_address (operands[0], QImode, 0);
-    operands[1] = adjust_address (operands[1], QImode, 0);
-    operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
-  })
-
 (define_insn_and_split "*andqi3_2"
   [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
 	(and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
@@ -177,14 +155,6 @@
 ;; OR/XOR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "b<code><mode>_msx"
-  [(set (match_operand:QHI 0 "bit_register_indirect_operand" "=WU")
-	(ors:QHI (match_operand:QHI 1 "bit_register_indirect_operand" "%0")
-		 (match_operand:QHI 2 "single_one_operand" "Y2")))]
-  "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
-  { return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
-  [(set_attr "length" "8")])
-
 (define_insn_and_split "<code>qi3_1"
   [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
 	(ors:QI (match_operand:QI 1 "bit_operand" "%0,0")