From: Christophe Lyon Date: Tue, 28 Feb 2023 15:49:58 +0000 (+0000) Subject: arm: [MVE intrinsics] factorize vpselq X-Git-Tag: basepoints/gcc-15~9363 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f7196b72752cc4089570e75ebcce641b6d0165f2;p=thirdparty%2Fgcc.git arm: [MVE intrinsics] factorize vpselq Factorize vpselq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon gcc/ * config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of gen_mve_vpselq. * config/arm/iterators.md (MVE_VPSELQ_F): New. (mve_insn): Add vpsel. * config/arm/mve.md (@mve_vpselq_): Rename into ... (@mve_q_): ... this. (@mve_vpselq_f): Rename into ... (@mve_q_f): ... this. --- diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 06e0756e4e8e..da7e9c814653 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -31633,13 +31633,13 @@ arm_expand_vcond (rtx *operands, machine_mode cmp_result_mode) switch (GET_MODE_CLASS (cmp_mode)) { case MODE_VECTOR_INT: - emit_insn (gen_mve_vpselq (VPSELQ_S, cmp_mode, operands[0], - operands[1], operands[2], mask)); + emit_insn (gen_mve_q (VPSELQ_S, VPSELQ_S, cmp_mode, operands[0], + operands[1], operands[2], mask)); break; case MODE_VECTOR_FLOAT: if (TARGET_HAVE_MVE_FLOAT) - emit_insn (gen_mve_vpselq_f (cmp_mode, operands[0], - operands[1], operands[2], mask)); + emit_insn (gen_mve_q_f (VPSELQ_F, cmp_mode, operands[0], + operands[1], operands[2], mask)); else gcc_unreachable (); break; diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 022744f04d93..3d4a9cf9cc22 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -898,6 +898,10 @@ (VCMPNEQ_M_N_F "ne") ]) +(define_int_iterator MVE_VPSELQ_F [ + VPSELQ_F + ]) + (define_int_attr mve_insn [ (VABAVQ_P_S "vabav") (VABAVQ_P_U "vabav") (VABAVQ_S "vabav") (VABAVQ_U "vabav") @@ -1030,6 +1034,7 @@ (VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr") (VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr") (VORRQ_N_S "vorr") (VORRQ_N_U "vorr") + (VPSELQ_S "vpsel") (VPSELQ_U "vpsel") (VPSELQ_F "vpsel") (VQABSQ_M_S "vqabs") (VQABSQ_S "vqabs") (VQADDQ_M_N_S "vqadd") (VQADDQ_M_N_U "vqadd") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b87798730a25..c6f9c0b9afb8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1969,7 +1969,7 @@ ;; ;; [vpselq_u, vpselq_s]) ;; -(define_insn "@mve_vpselq_" +(define_insn "@mve_q_" [ (set (match_operand:MVE_1 0 "s_register_operand" "=w") (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w") @@ -1978,7 +1978,7 @@ VPSELQ)) ] "TARGET_HAVE_MVE" - "vpsel %q0, %q1, %q2" + "\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -2427,16 +2427,16 @@ ;; ;; [vpselq_f]) ;; -(define_insn "@mve_vpselq_f" +(define_insn "@mve_q_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand: 3 "vpr_register_operand" "Up")] - VPSELQ_F)) + MVE_VPSELQ_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpsel %q0, %q1, %q2" + "\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -6867,12 +6867,12 @@ switch (GET_MODE_CLASS (mode)) { case MODE_VECTOR_INT: - emit_insn (gen_mve_vpselq (VPSELQ_S, mode, operands[0], - operands[1], operands[2], operands[3])); + emit_insn (gen_mve_q (VPSELQ_S, VPSELQ_S, mode, operands[0], + operands[1], operands[2], operands[3])); break; case MODE_VECTOR_FLOAT: - emit_insn (gen_mve_vpselq_f (mode, operands[0], - operands[1], operands[2], operands[3])); + emit_insn (gen_mve_q_f (VPSELQ_F, mode, operands[0], + operands[1], operands[2], operands[3])); break; default: gcc_unreachable ();