From: Julian Seward Date: Sun, 5 Dec 2004 02:47:40 +0000 (+0000) Subject: Even more SSE insns. X-Git-Tag: svn/VALGRIND_3_0_1^2~716 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f76dbe65ed38e0bb76402d5f331b69e218c37961;p=thirdparty%2Fvalgrind.git Even more SSE insns. git-svn-id: svn://svn.valgrind.org/vex/trunk@618 --- diff --git a/VEX/priv/guest-x86/gdefs.h b/VEX/priv/guest-x86/gdefs.h index 6d787c7a3b..63141307c0 100644 --- a/VEX/priv/guest-x86/gdefs.h +++ b/VEX/priv/guest-x86/gdefs.h @@ -163,7 +163,10 @@ extern ULong x86g_calculate_max8Ux8 ( ULong, ULong ); extern ULong x86g_calculate_min16Sx4 ( ULong, ULong ); extern ULong x86g_calculate_min8Ux8 ( ULong, ULong ); -extern UInt x86g_calculate_pmovmskb ( ULong xx ); +extern UInt x86g_calculate_pmovmskb ( ULong xx ); +extern ULong x86g_calculate_psadbw ( ULong, ULong ); + +extern ULong x86g_calculate_mull16uHIx4 ( ULong, ULong ); /* --- DIRTY HELPERS --- */ diff --git a/VEX/priv/guest-x86/ghelpers.c b/VEX/priv/guest-x86/ghelpers.c index 2409d6afca..056b30564d 100644 --- a/VEX/priv/guest-x86/ghelpers.c +++ b/VEX/priv/guest-x86/ghelpers.c @@ -2008,6 +2008,19 @@ static inline UChar min8U ( UChar xx, UChar yy ) return (xx < yy) ? xx : yy; } +static inline UShort mull16uHI ( UShort xx, UShort yy ) +{ + UInt xxi = (UInt)xx; + UInt yyi = (UInt)yy; + UInt r = (xxi * yyi) >> 16; + return (UShort)r; +} + +static inline UChar abdU8 ( UChar xx, UChar yy ) +{ + return xx>yy ? xx-yy : yy-xx; +} + /* ------------ Normal addition ------------ */ ULong x86g_calculate_add32x2 ( ULong xx, ULong yy ) @@ -2568,8 +2581,32 @@ UInt x86g_calculate_pmovmskb ( ULong xx ) return r; } +ULong x86g_calculate_psadbw ( ULong xx, ULong yy ) +{ + UInt t = 0; + t += (UInt)abdU8( sel8x8_7(xx), sel8x8_7(yy) ); + t += (UInt)abdU8( sel8x8_6(xx), sel8x8_6(yy) ); + t += (UInt)abdU8( sel8x8_5(xx), sel8x8_5(yy) ); + t += (UInt)abdU8( sel8x8_4(xx), sel8x8_4(yy) ); + t += (UInt)abdU8( sel8x8_3(xx), sel8x8_3(yy) ); + t += (UInt)abdU8( sel8x8_2(xx), sel8x8_2(yy) ); + t += (UInt)abdU8( sel8x8_1(xx), sel8x8_1(yy) ); + t += (UInt)abdU8( sel8x8_0(xx), sel8x8_0(yy) ); + t &= 0xFFFF; + return (ULong)t; +} + /* ------------ MMX insns from SSE1: multiply ------------ */ +ULong x86g_calculate_mull16uHIx4 ( ULong xx, ULong yy ) +{ + return mk16x4( + mull16uHI( sel16x4_3(xx), sel16x4_3(yy) ), + mull16uHI( sel16x4_2(xx), sel16x4_2(yy) ), + mull16uHI( sel16x4_1(xx), sel16x4_1(yy) ), + mull16uHI( sel16x4_0(xx), sel16x4_0(yy) ) + ); +} /*-----------------------------------------------------------*/ diff --git a/VEX/priv/guest-x86/toIR.c b/VEX/priv/guest-x86/toIR.c index 5b3a5aa515..30c5de5d7c 100644 --- a/VEX/priv/guest-x86/toIR.c +++ b/VEX/priv/guest-x86/toIR.c @@ -5075,6 +5075,8 @@ UInt dis_MMXop_regmem_to_reg ( UChar sorb, case 0xDE: XXX(x86g_calculate_max8Ux8); break; case 0xEA: XXX(x86g_calculate_min16Sx4); break; case 0xDA: XXX(x86g_calculate_min8Ux8); break; + case 0xE4: XXX(x86g_calculate_mull16uHIx4); break; + case 0xF6: XXX(x86g_calculate_psadbw); break; default: vex_printf("\n0x%x\n", (Int)opc); @@ -6842,6 +6844,35 @@ UInt dis_SSE_E_to_G_invG ( UChar sorb, UInt delta, HChar* opname, IROp op ) return dis_SSE_E_to_G_wrk( sorb, delta, opname, op, True ); } +static UInt dis_SSE_E_to_G_unary ( + UChar sorb, UInt delta, + HChar* opname, IROp op + ) +{ + HChar dis_buf[50]; + Int alen; + IRTemp addr; + UChar rm = getIByte(delta); + if (epartIsReg(rm)) { + putXMMReg( gregOfRM(rm), + unop(op, getXMMReg(eregOfRM(rm))) ); + DIP("%s %s,%s\n", opname, + nameXMMReg(eregOfRM(rm)), + nameXMMReg(gregOfRM(rm)) ); + return delta+1; + } else { + addr = disAMode ( &alen, sorb, delta, dis_buf ); + putXMMReg( gregOfRM(rm), + unop(op, loadLE(Ity_V128, mkexpr(addr))) ); + DIP("%s %s,%s\n", opname, + dis_buf, + nameXMMReg(gregOfRM(rm)) ); + return delta+alen; + } +} + + + static void findSSECmpOp ( Bool* needNot, IROp* op, Int imm8, Bool all_lanes, Int sz ) { @@ -7061,85 +7092,6 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, insn = (UChar*)&guest_code[delta]; - /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */ - /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */ - if (insn[0] == 0x0F && insn[1] == 0x12) { - vassert(sz == 4); - modrm = getIByte(delta+2); - if (epartIsReg(modrm)) { - delta += 2+1; - putXMMRegLane64( gregOfRM(modrm), - 0/*lower lane*/, - getXMMRegLane64( eregOfRM(modrm), 1 )); - DIP("movhlps %s, %s\n", nameXMMReg(eregOfRM(modrm)), - nameXMMReg(gregOfRM(modrm))); - } else { - addr = disAMode ( &alen, sorb, delta+2, dis_buf ); - delta += 2+alen; - putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/, - loadLE(Ity_I64, mkexpr(addr)) ); - DIP("movlps %s, %s\n", - dis_buf, nameXMMReg( gregOfRM(modrm) )); - } - goto decode_success; - } - - /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */ - if (insn[0] == 0x0F && insn[1] == 0x13) { - if (!epartIsReg(insn[2])) { - vassert(sz == 4); - delta += 2; - addr = disAMode ( &alen, sorb, delta, dis_buf ); - delta += alen; - storeLE( mkexpr(addr), - getXMMRegLane64( gregOfRM(insn[2]), - 0/*lower lane*/ ) ); - DIP("movlps %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ), - dis_buf); - goto decode_success; - } - /* else fall through */ - } - - /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */ - /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */ - if (insn[0] == 0x0F && insn[1] == 0x16) { - vassert(sz == 4); - modrm = getIByte(delta+2); - if (epartIsReg(modrm)) { - delta += 2+1; - putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, - getXMMRegLane64( eregOfRM(modrm), 0 ) ); - DIP("movhps %s,%s\n", nameXMMReg(eregOfRM(modrm)), - nameXMMReg(gregOfRM(modrm))); - } else { - addr = disAMode ( &alen, sorb, delta+2, dis_buf ); - delta += 2+alen; - putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, - loadLE(Ity_I64, mkexpr(addr)) ); - DIP("movhps %s,%s\n", dis_buf, - nameXMMReg( gregOfRM(insn[2]) )); - } - goto decode_success; - } - - /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */ - if (insn[0] == 0x0F && insn[1] == 0x17) { - if (!epartIsReg(insn[2])) { - vassert(sz == 4); - delta += 2; - addr = disAMode ( &alen, sorb, delta, dis_buf ); - delta += alen; - storeLE( mkexpr(addr), - getXMMRegLane64( gregOfRM(insn[2]), - 1/*upper lane*/ ) ); - DIP("movhps %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ), - dis_buf); - goto decode_success; - } - /* else fall through */ - } - /* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */ if (insn[0] == 0x0F && insn[1] == 0x58) { vassert(sz == 4); @@ -7455,6 +7407,85 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, goto decode_success; } + /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */ + /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */ + if (insn[0] == 0x0F && insn[1] == 0x16) { + vassert(sz == 4); + modrm = getIByte(delta+2); + if (epartIsReg(modrm)) { + delta += 2+1; + putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, + getXMMRegLane64( eregOfRM(modrm), 0 ) ); + DIP("movhps %s,%s\n", nameXMMReg(eregOfRM(modrm)), + nameXMMReg(gregOfRM(modrm))); + } else { + addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + delta += 2+alen; + putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/, + loadLE(Ity_I64, mkexpr(addr)) ); + DIP("movhps %s,%s\n", dis_buf, + nameXMMReg( gregOfRM(insn[2]) )); + } + goto decode_success; + } + + /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */ + if (insn[0] == 0x0F && insn[1] == 0x17) { + if (!epartIsReg(insn[2])) { + vassert(sz == 4); + delta += 2; + addr = disAMode ( &alen, sorb, delta, dis_buf ); + delta += alen; + storeLE( mkexpr(addr), + getXMMRegLane64( gregOfRM(insn[2]), + 1/*upper lane*/ ) ); + DIP("movhps %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ), + dis_buf); + goto decode_success; + } + /* else fall through */ + } + + /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */ + /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */ + if (insn[0] == 0x0F && insn[1] == 0x12) { + vassert(sz == 4); + modrm = getIByte(delta+2); + if (epartIsReg(modrm)) { + delta += 2+1; + putXMMRegLane64( gregOfRM(modrm), + 0/*lower lane*/, + getXMMRegLane64( eregOfRM(modrm), 1 )); + DIP("movhlps %s, %s\n", nameXMMReg(eregOfRM(modrm)), + nameXMMReg(gregOfRM(modrm))); + } else { + addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + delta += 2+alen; + putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/, + loadLE(Ity_I64, mkexpr(addr)) ); + DIP("movlps %s, %s\n", + dis_buf, nameXMMReg( gregOfRM(modrm) )); + } + goto decode_success; + } + + /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */ + if (insn[0] == 0x0F && insn[1] == 0x13) { + if (!epartIsReg(insn[2])) { + vassert(sz == 4); + delta += 2; + addr = disAMode ( &alen, sorb, delta, dis_buf ); + delta += alen; + storeLE( mkexpr(addr), + getXMMRegLane64( gregOfRM(insn[2]), + 0/*lower lane*/ ) ); + DIP("movlps %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ), + dis_buf); + goto decode_success; + } + /* else fall through */ + } + /* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E) to 4 lowest bits of ireg(G) */ if (insn[0] == 0x0F && insn[1] == 0x50) { @@ -7782,6 +7813,90 @@ static DisResult disInstr ( /*IN*/ Bool resteerOK, /* else fall through */ } + /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ + /* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */ + if (insn[0] == 0x0F && insn[1] == 0xE4) { + vassert(sz == 4); + do_MMX_preamble(); + delta = dis_MMXop_regmem_to_reg ( + sorb, delta+2, insn[1], "pmuluh", False ); + goto decode_success; + } + + /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ + /* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */ + if (insn[0] == 0x0F && insn[1] == 0xF6) { + vassert(sz == 4); + do_MMX_preamble(); + delta = dis_MMXop_regmem_to_reg ( + sorb, delta+2, insn[1], "psadbw", False ); + goto decode_success; + } + + /* ***--- this is an MMX class insn introduced in SSE1 ---*** */ + /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */ + if (insn[0] == 0x0F && insn[1] == 0x70) { + Int order; + vassert(sz == 4); + t0 = newTemp(Ity_I64); + t1 = newTemp(Ity_I64); + do_MMX_preamble(); + modrm = insn[2]; + if (epartIsReg(modrm)) { + assign( t0, getMMXReg(eregOfRM(modrm)) ); + order = (Int)insn[3]; + delta += 2+2; + DIP("pshufw $%d,%s,%s\n", order, + nameMMXReg(eregOfRM(modrm)), + nameMMXReg(gregOfRM(modrm))); + } else { + addr = disAMode ( &alen, sorb, delta+2, dis_buf ); + assign( t0, loadLE(Ity_I64, mkexpr(addr)) ); + order = (Int)insn[2+alen]; + delta += 3+alen; + DIP("pshufw $%d,%s,%s\n", order, + dis_buf, + nameMMXReg(gregOfRM(modrm))); + } + +# define WORD0 unop(Iop_32to16,unop(Iop_64to32,mkexpr(t0))) +# define WORD1 unop(Iop_32HIto16,unop(Iop_64to32,mkexpr(t0))) +# define WORD2 unop(Iop_32to16,unop(Iop_64HIto32,mkexpr(t0))) +# define WORD3 unop(Iop_32HIto16,unop(Iop_64HIto32,mkexpr(t0))) +# define SEL(n) ((n)==0 ? WORD0 \ + : ((n)==1 ? WORD1 \ + : ((n)==2 ? WORD2 : WORD3))) + assign(t1, + binop(Iop_32HLto64, + binop(Iop_16HLto32,SEL((order>>6)&3),SEL((order>>4)&3)), + binop(Iop_16HLto32,SEL((order>>2)&3),SEL((order>>0)&3)) + ) + ); + putMMXReg(gregOfRM(modrm), mkexpr(t1)); + +# undef SEL +# undef WORD0 +# undef WORD1 +# undef WORD2 +# undef WORD3 + goto decode_success; + } + + /* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */ + if (insn[0] == 0x0F && insn[1] == 0x53) { + vassert(sz == 4); + delta = dis_SSE_E_to_G_unary( sorb, delta+2, + "rcpps", Iop_Recip32Fx4 ); + goto decode_success; + } + + /* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */ + if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x53) { + vassert(sz == 4); + delta = dis_SSE_E_to_G_unary( sorb, delta+3, + "rcpss", Iop_Recip32F0x4 ); + goto decode_success; + } //-- //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */ diff --git a/VEX/priv/host-x86/hdefs.c b/VEX/priv/host-x86/hdefs.c index 7ee3443974..78f2956f24 100644 --- a/VEX/priv/host-x86/hdefs.c +++ b/VEX/priv/host-x86/hdefs.c @@ -511,6 +511,7 @@ HChar* showX86SseOp ( X86SseOp op ) { case Xsse_DIVF: return "div"; case Xsse_MAXF: return "max"; case Xsse_MINF: return "min"; + case Xsse_RCPF: return "rcp"; case Xsse_CMPEQF: return "cmpFeq"; case Xsse_CMPLTF: return "cmpFlt"; case Xsse_CMPLEF: return "cmpFle"; @@ -998,6 +999,7 @@ void ppX86Instr ( X86Instr* i ) { void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i) { + Bool unary; initHRegUsage(u); switch (i->tag) { case Xin_Alu32R: @@ -1158,13 +1160,17 @@ void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i) return; case Xin_Sse32Fx4: vassert(i->Xin.Sse32Fx4.op != Xsse_MOV); - addHRegUse(u, HRmRead, i->Xin.Sse32Fx4.src); - addHRegUse(u, HRmModify, i->Xin.Sse32Fx4.dst); + unary = i->Xin.Sse32Fx4.op == Xsse_RCPF; + addHRegUse(u, HRmRead, i->Xin.Sse32Fx4.src); + addHRegUse(u, unary ? HRmWrite : HRmModify, + i->Xin.Sse32Fx4.dst); return; case Xin_Sse32FLo: vassert(i->Xin.Sse32FLo.op != Xsse_MOV); - addHRegUse(u, HRmRead, i->Xin.Sse32FLo.src); - addHRegUse(u, HRmModify, i->Xin.Sse32FLo.dst); + unary = i->Xin.Sse32Fx4.op == Xsse_RCPF; + addHRegUse(u, HRmRead, i->Xin.Sse32FLo.src); + addHRegUse(u, unary ? HRmWrite : HRmModify, + i->Xin.Sse32FLo.dst); return; default: ppX86Instr(i); @@ -2410,6 +2416,7 @@ Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i ) case Xsse_MAXF: *p++ = 0x5F; break; case Xsse_MINF: *p++ = 0x5D; break; case Xsse_MULF: *p++ = 0x59; break; + case Xsse_RCPF: *p++ = 0x53; break; case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; @@ -2431,6 +2438,7 @@ Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i ) case Xsse_MAXF: *p++ = 0x5F; break; case Xsse_MINF: *p++ = 0x5D; break; case Xsse_MULF: *p++ = 0x59; break; + case Xsse_RCPF: *p++ = 0x53; break; case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; diff --git a/VEX/priv/host-x86/hdefs.h b/VEX/priv/host-x86/hdefs.h index 3e143cc6e2..7e47899714 100644 --- a/VEX/priv/host-x86/hdefs.h +++ b/VEX/priv/host-x86/hdefs.h @@ -310,6 +310,7 @@ typedef Xsse_MOV, Xsse_AND, Xsse_OR, Xsse_XOR, Xsse_ANDN, Xsse_ADDF, Xsse_SUBF, Xsse_MULF, Xsse_DIVF, Xsse_MAXF, Xsse_MINF, + Xsse_RCPF, Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF } X86SseOp; diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c index 9f04acea28..3b33caf0e0 100644 --- a/VEX/priv/host-x86/isel.c +++ b/VEX/priv/host-x86/isel.c @@ -2426,6 +2426,32 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) return dst; } + if (e->tag == Iex_Unop) { + switch (e->Iex.Unop.op) { + + case Iop_Recip32Fx4: op = Xsse_RCPF; goto do_32Fx4_unary; + do_32Fx4_unary: + { + HReg arg = iselVecExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegV(env); + addInstr(env, X86Instr_Sse32Fx4(op, arg, dst)); + return dst; + } + + case Iop_Recip32F0x4: op = Xsse_RCPF; goto do_32F0x4_unary; + do_32F0x4_unary: + { + HReg arg = iselVecExpr(env, e->Iex.Unop.arg); + HReg dst = newVRegV(env); + addInstr(env, X86Instr_Sse32FLo(op, arg, dst)); + return dst; + } + + default: + break; + } /* switch (e->Iex.Unop.op) */ + } /* if (e->tag == Iex_Unop) */ + if (e->tag == Iex_Binop) { switch (e->Iex.Binop.op) { case Iop_64HLto128: { diff --git a/VEX/priv/ir/irdefs.c b/VEX/priv/ir/irdefs.c index 3d3c622881..8e7f5fbc39 100644 --- a/VEX/priv/ir/irdefs.c +++ b/VEX/priv/ir/irdefs.c @@ -240,6 +240,9 @@ void ppIROp ( IROp op ) case Iop_Mul32Fx4: vex_printf("Mul32Fx4"); return; case Iop_Mul32F0x4: vex_printf("Mul32F0x4"); return; + case Iop_Recip32Fx4: vex_printf("Recip32Fx4"); return; + case Iop_Recip32F0x4: vex_printf("Recip32F0x4"); return; + case Iop_CmpEQ32Fx4: vex_printf("CmpEQ32Fx4"); return; case Iop_CmpLT32Fx4: vex_printf("CmpLT32Fx4"); return; case Iop_CmpLE32Fx4: vex_printf("CmpLE32Fx4"); return; @@ -1122,6 +1125,9 @@ void typeOfPrimop ( IROp op, IRType* t_dst, IRType* t_arg1, IRType* t_arg2 ) case Iop_And128: case Iop_Or128: case Iop_Xor128: BINARY(Ity_V128, Ity_V128,Ity_V128); + case Iop_Recip32Fx4: case Iop_Recip32F0x4: + UNARY(Ity_V128, Ity_V128); + default: ppIROp(op); vpanic("typeOfPrimop"); diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index d2fd489607..0ff7bb286c 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -341,8 +341,8 @@ typedef /* unary */ Iop_Recip32Fx4, Iop_Sqrt32Fx4, Iop_RSqrt32Fx4, - Iop_ItoF32x4, /* first arg is IRRoundingMode (Ity_I32) */ - Iop_FtoI32x4, /* first arg is IRRoundingMode (Ity_I32) */ + //Iop_ItoF32x4, /* first arg is IRRoundingMode (Ity_I32) */ + //Iop_FtoI32x4, /* first arg is IRRoundingMode (Ity_I32) */ /* --- 32x4 lowest-lane-only scalar FP --- */ @@ -355,8 +355,8 @@ typedef /* unary */ Iop_Recip32F0x4, Iop_Sqrt32F0x4, Iop_RSqrt32F0x4, - Iop_ItoF320x4, /* first arg is IRRoundingMode (Ity_I32) */ - Iop_FtoI320x4, /* first arg is IRRoundingMode (Ity_I32) */ + //Iop_ItoF320x4, /* first arg is IRRoundingMode (Ity_I32) */ + //Iop_FtoI320x4, /* first arg is IRRoundingMode (Ity_I32) */ /* --- pack / unpack --- */