From: Stephen Boyd <sboyd@kernel.org>
Date: Tue, 29 Jul 2025 22:18:13 +0000 (-0700)
Subject: Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx... 
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f7887ee4ee2b1fa2a538db4dbf3cec26538f317a;p=thirdparty%2Flinux.git

Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next

 - Support atomic PWMs in the PWM clk driver
 - clk_hw_get_dev() and clk_hw_get_of_node() helpers

* clk-bindings: (30 commits)
  dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
  dt-bindings: clock: Convert qca,ath79-pll to DT schema
  dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
  dt-bindings: clock: Convert moxa,moxart-clock to DT schema
  dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
  dt-bindings: clock: Convert maxim,max9485 to DT schema
  dt-bindings: clock: Convert qcom,krait-cc to DT schema
  dt-bindings: clock: qcom: Remove double colon from description
  dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
  dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
  dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
  dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
  dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
  dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
  dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
  dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
  dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
  dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
  dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
  dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
  ...

* clk-cleanup: (29 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: bcm: bcm2835: convert from round_rate() to determine_rate()
  MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry
  clk: ti: Simplify ti_find_clock_provider()
  ...

* clk-pwm:
  clk: pwm: Make use of non-sleeping PWMs
  clk: pwm: Don't reconfigure running PWM at probe time
  clk: pwm: Convert to use pwm_apply_might_sleep()
  clk: pwm: Let .get_duty_cycle() return the real duty cycle

* clk-hw-device:
  clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests
  clk: tests: Make clk_register_clk_parent_data_device_driver() common
  clk: add a clk_hw helpers to get the clock device or device_node

* clk-xilinx:
  clk: xilinx: vcu: Update vcu init/reset sequence
  clk: xilinx: vcu: unregister pll_post only if registered correctly

* clk-adi:
  clk: clk-axi-clkgen: fix coding style issues
  clk: clk-axi-clkgen move to min/max()
  clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime
  include: adi-axi-common: add new helper macros
  include: linux: move adi-axi-common.h out of fpga
  clk: clk-axi-clkgen: make sure to include mod_devicetable.h
  clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
---

f7887ee4ee2b1fa2a538db4dbf3cec26538f317a