From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Thu, 5 Apr 2007 23:14:23 +0000 (+0000)
Subject: 64bit MIPS FPUs have 32 registers.
X-Git-Tag: release_0_9_1~1287
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f7cfb2a176208d3b5139a2e792b40edf1adb43b4;p=thirdparty%2Fqemu.git

64bit MIPS FPUs have 32 registers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3849e503cde..4b179297061 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -62,9 +62,8 @@ struct CPUMIPSState {
     target_ulong t2;
 #endif
     target_ulong HI, LO;
-    uint32_t DCR; /* ? */
     /* Floating point registers */
-    fpr_t fpr[16];
+    fpr_t fpr[32];
 #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
 #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
 #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])