From: liuhongt Date: Tue, 10 Sep 2024 07:04:58 +0000 (+0800) Subject: Enable tune fuse_move_and_alu for GNR. X-Git-Tag: basepoints/gcc-16~5974 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f80e4ba94e41410219bdcdb1a0f204ea3f148666;p=thirdparty%2Fgcc.git Enable tune fuse_move_and_alu for GNR. According to Intel Software Optimization Manual[1], the Redwood cove microarchitecture supports LD+OP and MOV+OP macro fusions. The patch enables MOV+OP tune for GNR. [1] https://www.intel.com/content/www/us/en/content-details/814198/intel-64-and-ia-32-architectures-optimization-reference-manual-volume-1.html gcc/ChangeLog: * config/i386/x86-tune.def (X86_TUNE_FUSE_MOV_AND_ALU): Enable for GNR and GNR-D. --- diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index d7e2ad7fd25..3d123da95f0 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -153,7 +153,8 @@ DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch", /* X86_TUNE_FUSE_MOV_AND_ALU: mov and alu in case mov is reg-reg mov and the destination is used by alu. alu must be one of ADD, ADC, AND, XOR, OR, SUB, SBB, INC, DEC, NOT, SAL, SHL, SHR, SAR. */ -DEF_TUNE (X86_TUNE_FUSE_MOV_AND_ALU, "fuse_mov_and_alu", m_ZNVER5) +DEF_TUNE (X86_TUNE_FUSE_MOV_AND_ALU, "fuse_mov_and_alu", + m_ZNVER5 | m_GRANITERAPIDS | m_GRANITERAPIDS_D) /*****************************************************************************/ /* Function prologue, epilogue and function calling sequences. */