From: Wilco Dijkstra <wilco.dijkstra@arm.com>
Date: Fri, 10 Nov 2023 14:06:50 +0000 (+0000)
Subject: libatomic: Improve ifunc selection on AArch64
X-Git-Tag: basepoints/gcc-15~4814
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f880bdc2716d59530949c9c03e4b759c6398c4e4;p=thirdparty%2Fgcc.git

libatomic: Improve ifunc selection on AArch64

Add support for ifunc selection based on CPUID register.  Neoverse N1 supports
atomic 128-bit load/store, so use the FEAT_USCAT ifunc like newer Neoverse
cores.

Reviewed-by: Kyrylo.Tkachov@arm.com

libatomic:
	* config/linux/aarch64/host-config.h (ifunc1): Use CPUID in ifunc
	selection.
---

diff --git a/libatomic/config/linux/aarch64/host-config.h b/libatomic/config/linux/aarch64/host-config.h
index bea26825b4f7..9747accd88f5 100644
--- a/libatomic/config/linux/aarch64/host-config.h
+++ b/libatomic/config/linux/aarch64/host-config.h
@@ -26,7 +26,7 @@
 
 #ifdef HWCAP_USCAT
 # if N == 16
-#  define IFUNC_COND_1	(hwcap & HWCAP_USCAT)
+#  define IFUNC_COND_1	ifunc1 (hwcap)
 # else
 #  define IFUNC_COND_1	(hwcap & HWCAP_ATOMICS)
 # endif
@@ -41,4 +41,28 @@
 
 #endif /* HAVE_IFUNC */
 
+#ifdef HWCAP_USCAT
+
+#define MIDR_IMPLEMENTOR(midr)	(((midr) >> 24) & 255)
+#define MIDR_PARTNUM(midr)	(((midr) >> 4) & 0xfff)
+
+static inline bool
+ifunc1 (unsigned long hwcap)
+{
+  if (hwcap & HWCAP_USCAT)
+    return true;
+  if (!(hwcap & HWCAP_CPUID))
+    return false;
+
+  unsigned long midr;
+  asm volatile ("mrs %0, midr_el1" : "=r" (midr));
+
+  /* Neoverse N1 supports atomic 128-bit load/store.  */
+  if (MIDR_IMPLEMENTOR (midr) == 'A' && MIDR_PARTNUM (midr) == 0xd0c)
+    return true;
+
+  return false;
+}
+#endif
+
 #include_next <host-config.h>