From: Tommaso Merciai Date: Wed, 3 Sep 2025 08:27:51 +0000 (+0200) Subject: clk: renesas: rzg2l: Re-assert reset on deassert timeout X-Git-Tag: v6.18-rc1~50^2~7^3^2~10 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f8c5f0dc77d86da36bcbf0684c6747a2937cc3cd;p=thirdparty%2Fkernel%2Flinux.git clk: renesas: rzg2l: Re-assert reset on deassert timeout Prevent issues during reset deassertion by re-asserting the reset if a timeout occurs when trying to deassert. This ensures the reset line is in a known state and improves reliability for hardware that may not immediately clear the reset monitor bit. Reviewed-by: Geert Uytterhoeven Signed-off-by: Tommaso Merciai Link: https://lore.kernel.org/20250903082757.115778-3-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index e0e1bebd98950..07909e80bae24 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1667,8 +1667,14 @@ static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev, return 0; } - return readl_poll_timeout_atomic(priv->base + reg, value, - assert == !!(value & mask), 10, 200); + ret = readl_poll_timeout_atomic(priv->base + reg, value, + assert == !!(value & mask), 10, 200); + if (ret && !assert) { + value = mask << 16; + writel(value, priv->base + CLK_RST_R(info->resets[id].off)); + } + + return ret; } static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,