From: Matt Atwood Date: Fri, 6 Oct 2023 16:47:59 +0000 (-0700) Subject: drm/xe: add gt tuning for indirect state X-Git-Tag: v6.8-rc1~111^2~7^2~316 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f8ebadd0df248d7f0b5060fd8a0d956e773d9d78;p=thirdparty%2Flinux.git drm/xe: add gt tuning for indirect state Force indirect state sampler data to only be in the dynamic state pool, which is more convienent for the UMD. Behavior change mirrors similar change for i915 in commit 16fc9c08f0ec ("drm/i915: disable sampler indirect state in bindless heap") v2: split out per engine tuning into separate patch, commit message (Lucas) v3: rebase v4: Change to match render only, g.ver 1200 to 1271 (MattR) Acked-by: Lionel Landwerlin Reviewed-by: Matt Roper Signed-off-by: Matt Atwood Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 83519a424aab1..cd1821d96a5d8 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -303,6 +303,7 @@ #define ENABLE_SMALLPL REG_BIT(15) #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) +#define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c index 3ad11c2593003..d705198165220 100644 --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -28,6 +28,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = { }; static const struct xe_rtp_entry_sr engine_tunings[] = { + { XE_RTP_NAME("Tuning: Set Indirect State Override"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1271), + ENGINE_CLASS(RENDER)), + XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE)) + }, {} };