From: Philippe Waroquiers Date: Mon, 11 Aug 2014 22:45:47 +0000 (+0000) Subject: Small cleanups in VEX: X-Git-Tag: svn/VALGRIND_3_10_1^2~52 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f92e06c688b7c8e8e80a7a390c95742b3101b7f8;p=thirdparty%2Fvalgrind.git Small cleanups in VEX: * rm unused arm64 function * ijk_nodecode: always set the 4 components of the result (avoid a compiler warning that a part is not initialised) git-svn-id: svn://svn.valgrind.org/vex/trunk@2919 --- diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index 5430bed507..8d5d4603e1 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -6213,22 +6213,6 @@ IRTemp math_NARROW_LANES ( IRTemp argHi, IRTemp argLo, UInt sizeNarrow ) } -/* Generate IR that takes an I64 and sign- or zero- widens each - lane, giving a V128 value. */ -static -IRTemp math_WIDEN_LANES ( Bool zWiden, UInt sizeNarrow, IRExpr* srcE ) -{ - IRTemp src = newTemp(Ity_I64); - assign(src, srcE); - return math_WIDEN_LO_OR_HI_LANES( - zWiden, - False/*!fromUpperHalf*/, - sizeNarrow, - binop(Iop_64HLtoV128, mkexpr(src), mkexpr(src)) - ); -} - - /* Return a temp which holds the vector dup of the lane of width (1 << size) obtained from src[laneNo]. */ static @@ -10836,10 +10820,10 @@ DisResult disInstr_ARM64 ( IRSB* irsb_IN, start of each insn, but nevertheless be paranoid and update it again right now. */ putPC( mkU64(guest_PC_curr_instr) ); - dres.whatNext = Dis_StopHere; dres.len = 0; - dres.continueAt = 0; + dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; + dres.continueAt = 0; } return dres; } diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index a7ab76b900..64e5d6e386 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -17277,9 +17277,10 @@ DisResult disInstr_ARM_WRK ( now. */ vassert(0 == (guest_R15_curr_instr_notENC & 3)); llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) ); + dres.len = 0; dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; - dres.len = 0; + dres.continueAt = 0; return dres; decode_success: @@ -21846,9 +21847,10 @@ DisResult disInstr_THUMB_WRK ( now. */ vassert(0 == (guest_R15_curr_instr_notENC & 1)); llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) ); + dres.len = 0; dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; - dres.len = 0; + dres.continueAt = 0; return dres; decode_success: diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index d810feba4d..b561de28ef 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -20086,11 +20086,11 @@ DisResult disInstr_PPC_WRK ( insn, but nevertheless be paranoid and update it again right now. */ putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) ); + dres.len = 0; dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; - dres.len = 0; + dres.continueAt = 0; return dres; - } /* switch (opc) for the main (primary) opcode switch. */ decode_success: @@ -20154,9 +20154,9 @@ DisResult disInstr_PPC ( IRSB* irsb_IN, ty = mode64 ? Ity_I64 : Ity_I32; if (!mode64 && (host_endness_IN == VexEndnessLE)) { vex_printf("disInstr(ppc): Little Endian 32-bit mode is not supported\n"); + dres.len = 0; dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; - dres.len = 0; dres.continueAt = 0; return dres; } diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 4a5013b341..1f6bc6b238 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -16515,10 +16515,10 @@ disInstr_S390_WRK(UChar *insn) incorrect address. */ put_IA(mkaddr_expr(guest_IA_curr_instr)); + dres.len = 0; dres.whatNext = Dis_StopHere; dres.jk_StopHere = Ijk_NoDecode; dres.continueAt = 0; - dres.len = 0; } else { /* Decode success */ switch (dres.whatNext) {