From: Thomas Zimmermann <tzimmermann@suse.de>
Date: Mon, 16 Sep 2024 08:25:14 +0000 (+0200)
Subject: drm/ast: Use TX-chip register constants
X-Git-Tag: v6.13-rc1~122^2~23^2~10
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f93d66635fb3d4e3995dcc20acfa0498a2fa609d;p=thirdparty%2Fkernel%2Fstable.git

drm/ast: Use TX-chip register constants

Replace magic values with named constants when reading the TX chip
from VGACRD1.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240916082920.56234-3-tzimmermann@suse.de
---

diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c
index e5553334bfde7..9e19d8c177308 100644
--- a/drivers/gpu/drm/ast/ast_dp501.c
+++ b/drivers/gpu/drm/ast/ast_dp501.c
@@ -444,18 +444,19 @@ static void ast_init_analog(struct ast_device *ast)
 
 void ast_init_3rdtx(struct ast_device *ast)
 {
-	u8 jreg;
+	u8 vgacrd1;
 
 	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast)) {
-		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
-		switch (jreg & 0x0e) {
-		case 0x04:
+		vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
+						 AST_IO_VGACRD1_TX_TYPE_MASK);
+		switch (vgacrd1) {
+		case AST_IO_VGACRD1_TX_SIL164_VBIOS:
 			ast_init_dvo(ast);
 			break;
-		case 0x08:
+		case AST_IO_VGACRD1_TX_DP501_VBIOS:
 			ast_launch_m68k(ast);
 			break;
-		case 0x0c:
+		case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW:
 			ast_init_dvo(ast);
 			break;
 		default:
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index d0e4f0dc92347..7289bdc6066ef 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -101,12 +101,13 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 		 * the SOC scratch register #1 bits 11:8 (interestingly marked
 		 * as "reserved" in the spec)
 		 */
-		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
+		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
+					      AST_IO_VGACRD1_TX_TYPE_MASK);
 		switch (jreg) {
-		case 0x04:
+		case AST_IO_VGACRD1_TX_SIL164_VBIOS:
 			ast->tx_chip = AST_TX_SIL164;
 			break;
-		case 0x08:
+		case AST_IO_VGACRD1_TX_DP501_VBIOS:
 			ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
 			if (ast->dp501_fw_addr) {
 				/* backup firmware */
@@ -116,7 +117,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 				}
 			}
 			fallthrough;
-		case 0x0c:
+		case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW:
 			ast->tx_chip = AST_TX_DP501;
 		}
 	} else if (IS_AST_GEN7(ast)) {
diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
index daa5d3a9e6a12..2aadf07d135af 100644
--- a/drivers/gpu/drm/ast/ast_reg.h
+++ b/drivers/gpu/drm/ast/ast_reg.h
@@ -46,7 +46,7 @@
 #define AST_IO_VGACRD1_TX_CH7003_VBIOS		0x06
 #define AST_IO_VGACRD1_TX_DP501_VBIOS		0x08
 #define AST_IO_VGACRD1_TX_ANX9807_VBIOS		0x0a
-#define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW	0x0c
+#define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW	0x0c /* special case of DP501 */
 #define AST_IO_VGACRD1_TX_ASTDP			0x0e
 
 #define AST_IO_VGACRD7_EDID_VALID_FLAG	BIT(0)