From: Pan Li Date: Tue, 13 Jan 2026 02:03:47 +0000 (+0800) Subject: RISC-V: Add test for vec_duplicate + vmsle.vv combine with GR2VR cost 0, 1 and 15 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f941d0491edf6704b2fdd9eb9ff37516b5bd74ed;p=thirdparty%2Fgcc.git RISC-V: Add test for vec_duplicate + vmsle.vv combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vmsle.vv combine to vmsle.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check for vmsle.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i8.c: New test. Signed-off-by: Pan Li --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 1b7a0d8061b..683e7cebb28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 8e2c6315b08..07dcc2ec7e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index a16623ee294..b30fe640d21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -33,3 +33,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index be50b83c726..01b426afbfb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsle.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index fb50baecf59..532e1884aea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index d79e0e04c85..5ed2711c032 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index 6cdaf5d6538..b494695098e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index 9e3879aadb7..8fdee21f931 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index e3ef3e35deb..841b88e4c2c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index 20039c7e3b3..e80fdcc7357 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index c973ea7c430..548a3218e7f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index e781c627b8d..eb10722f2d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmslt.vx} } } */ +/* { dg-final { scan-assembler-not {vmsle.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index b1a678c130b..149787ae476 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -405,6 +405,7 @@ DEF_AVG_CEIL(int32_t, int64_t) DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq) \ DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \ DEF_VX_BINARY_CASE_0_WRAP(T, <, lt) \ + DEF_VX_BINARY_CASE_0_WRAP(T, <=, le) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 0cfb0fa5a2a..8e66c22a235 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -6838,4 +6838,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, leu)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, le)[][3][N] = +{ + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 127, 127, 127, 127, + -128, -128, -128, -128, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -128, -128, -128, -128, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, le)[][3][N] = +{ + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -32768, -32768, -32768, -32768, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, le)[][3][N] = +{ + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, le)[][3][N] = +{ + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i16.c new file mode 100644 index 00000000000..f197ccc07ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME le + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i32.c new file mode 100644 index 00000000000..9ca23ba0da0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME le + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i64.c new file mode 100644 index 00000000000..2fbb08ea7c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME le + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i8.c new file mode 100644 index 00000000000..41062b2f617 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsle-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME le + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h"