From: Julius Bairaktaris Date: Sun, 26 Jul 2026 08:46:41 +0000 (+0200) Subject: qualcommax: 6.18: drop upstreamed patches X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=f9cfce5ee791d2bd69b0659ff1a51a20126b89fb;p=thirdparty%2Fopenwrt.git qualcommax: 6.18: drop upstreamed patches Drop the 34 patches carrying a v6.13..v6.18 version prefix - all part of kernel 6.18 - and three more whose content reached 6.18 through a different route: - 0111 (PCIe msi-parent): superseded, the ipq8074 PCIe nodes use split msi0..msi7 interrupts upstream now. - 0760 (Aquantia USXGMII MAC autoneg): generic/715 enables the same autoneg bit unconditionally at config_init on 6.18. - 0843 (stmmac get_interfaces): merged upstream. The patches for later kernel versions are not in 6.18 and stay. Signed-off-by: Julius Bairaktaris Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek --- diff --git a/target/linux/qualcommax/patches-6.18/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch b/target/linux/qualcommax/patches-6.18/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch deleted file mode 100644 index 9dadee21548..00000000000 --- a/target/linux/qualcommax/patches-6.18/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch +++ /dev/null @@ -1,381 +0,0 @@ -From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Tue, 22 Oct 2024 17:47:26 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case - -DTS coding style expects labels to be lowercase. No functional impact. -Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++--- - arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++----- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++------- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++----- - arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++-------------- - 5 files changed, 61 insertions(+), 61 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -31,27 +31,27 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; ---- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi -@@ -31,47 +31,47 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -34,12 +34,12 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -47,12 +47,12 @@ - #cooling-cells = <2>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -60,12 +60,12 @@ - #cooling-cells = <2>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -73,12 +73,12 @@ - #cooling-cells = <2>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -86,7 +86,7 @@ - #cooling-cells = <2>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; -@@ -1015,10 +1015,10 @@ - cooling-maps { - map0 { - trip = <&cpu_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -32,39 +32,39 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - enable-method = "psci"; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; ---- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -34,12 +34,12 @@ - #address-cells = <1>; - #size-cells = <0>; - -- CPU0: cpu@0 { -+ cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -47,12 +47,12 @@ - #cooling-cells = <2>; - }; - -- CPU1: cpu@1 { -+ cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x1>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -60,12 +60,12 @@ - #cooling-cells = <2>; - }; - -- CPU2: cpu@2 { -+ cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x2>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -73,12 +73,12 @@ - #cooling-cells = <2>; - }; - -- CPU3: cpu@3 { -+ cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x3>; - enable-method = "psci"; -- next-level-cache = <&L2_0>; -+ next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -@@ -86,7 +86,7 @@ - #cooling-cells = <2>; - }; - -- L2_0: l2-cache { -+ l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; -@@ -865,10 +865,10 @@ - cooling-maps { - map0 { - trip = <&cpu0_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -@@ -893,10 +893,10 @@ - cooling-maps { - map0 { - trip = <&cpu1_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -@@ -921,10 +921,10 @@ - cooling-maps { - map0 { - trip = <&cpu2_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -@@ -949,10 +949,10 @@ - cooling-maps { - map0 { - trip = <&cpu3_alert>; -- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; diff --git a/target/linux/qualcommax/patches-6.18/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch b/target/linux/qualcommax/patches-6.18/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch deleted file mode 100644 index 5a5a7019abe..00000000000 --- a/target/linux/qualcommax/patches-6.18/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 144230e5840c09984ad743c3df9de5fb443159a9 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:18 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency - -The final version of IPQ6000 (SoC id: IPQ6000, SBL version: -BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency -of 1.2GHz, so add this CPU frequency. - -Signed-off-by: Chukun Pan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -119,6 +119,13 @@ - clock-latency-ns = <200000>; - }; - -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <850000>; -+ opp-supported-hw = <0x4>; -+ clock-latency-ns = <200000>; -+ }; -+ - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; diff --git a/target/linux/qualcommax/patches-6.18/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch b/target/linux/qualcommax/patches-6.18/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch deleted file mode 100644 index f87356c35b8..00000000000 --- a/target/linux/qualcommax/patches-6.18/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a96e765a7b3f64429f7eec3471a2093355ab041e Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:19 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency - -The early version of IPQ6000 (SoC id: IPQ6018, SBL version: -BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach -a max frequency of 1.5GHz, so add this CPU frequency. - -Signed-off-by: Chukun Pan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -140,6 +140,13 @@ - clock-latency-ns = <200000>; - }; - -+ opp-1512000000 { -+ opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <937500>; -+ opp-supported-hw = <0x2>; -+ clock-latency-ns = <200000>; -+ }; -+ - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; diff --git a/target/linux/qualcommax/patches-6.18/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch b/target/linux/qualcommax/patches-6.18/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch deleted file mode 100644 index da39ae54c12..00000000000 --- a/target/linux/qualcommax/patches-6.18/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 0c4c0f14b7d704bcb728d018a74788771dc9286b Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:20 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi - -Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 -pmic was never part of the IPQ60xx SoC, it's optional, so we moved -it out of the soc dtsi. - -Signed-off-by: Chukun Pan -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- - arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++++++++++ - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 ----------- - 3 files changed, 36 insertions(+), 15 deletions(-) - create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi - ---- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts -+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts -@@ -7,7 +7,7 @@ - - /dts-v1/; - --#include "ipq6018.dtsi" -+#include "ipq6018-mp5496.dtsi" - - / { - model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; ---- /dev/null -+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -@@ -0,0 +1,35 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that -+ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC. -+ */ -+ -+#include "ipq6018.dtsi" -+ -+&cpu0 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&ipq6018_s2>; -+}; -+ -+&rpm_requests { -+ regulators { -+ compatible = "qcom,rpm-mp5496-regulators"; -+ -+ ipq6018_s2: s2 { -+ regulator-min-microvolt = <725000>; -+ regulator-max-microvolt = <1062500>; -+ regulator-always-on; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -43,7 +43,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -56,7 +55,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -69,7 +67,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -82,7 +79,6 @@ - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; -- cpu-supply = <&ipq6018_s2>; - #cooling-cells = <2>; - }; - -@@ -184,16 +180,6 @@ - rpm_requests: rpm-requests { - compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; - qcom,glink-channels = "rpm_requests"; -- -- regulators { -- compatible = "qcom,rpm-mp5496-regulators"; -- -- ipq6018_s2: s2 { -- regulator-min-microvolt = <725000>; -- regulator-max-microvolt = <1062500>; -- regulator-always-on; -- }; -- }; - }; - }; - }; diff --git a/target/linux/qualcommax/patches-6.18/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch b/target/linux/qualcommax/patches-6.18/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch deleted file mode 100644 index 120ce53f8c1..00000000000 --- a/target/linux/qualcommax/patches-6.18/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch +++ /dev/null @@ -1,50 +0,0 @@ -From e60f872c2dc4c1d9227977c8714373fe6328699c Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:21 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator - -Change the labels of mp5496 regulator from ipq6018 to mp5496. - -Suggested-by: Konrad Dybcio -Suggested-by: Dmitry Baryshkov -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -@@ -7,26 +7,26 @@ - #include "ipq6018.dtsi" - - &cpu0 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &cpu1 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &cpu2 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &cpu3 { -- cpu-supply = <&ipq6018_s2>; -+ cpu-supply = <&mp5496_s2>; - }; - - &rpm_requests { - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - -- ipq6018_s2: s2 { -+ mp5496_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; diff --git a/target/linux/qualcommax/patches-6.18/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch b/target/linux/qualcommax/patches-6.18/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch deleted file mode 100644 index ce98c62f831..00000000000 --- a/target/linux/qualcommax/patches-6.18/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a566fb9ba8ffecb56c50729390a9ea076f5c9532 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 10 Feb 2025 15:01:22 +0800 -Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator - -Add LDOA2 regulator from MP5496 to support SDCC voltage scaling. - -Suggested-by: Robert Marko -Signed-off-by: Chukun Pan -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi -@@ -31,5 +31,14 @@ - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; -+ -+ mp5496_l2: l2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; - }; - }; -+ -+&sdhc { -+ vqmmc-supply = <&mp5496_l2>; -+}; diff --git a/target/linux/qualcommax/patches-6.18/0045-v6.16-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch b/target/linux/qualcommax/patches-6.18/0045-v6.16-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch deleted file mode 100644 index 622b3888bb0..00000000000 --- a/target/linux/qualcommax/patches-6.18/0045-v6.16-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch +++ /dev/null @@ -1,340 +0,0 @@ -From 74badb8b0b146668cc6c03eb58e2a814f9463d02 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Thu, 20 Feb 2025 15:12:46 +0530 -Subject: [PATCH] phy: qcom: Introduce PCIe UNIPHY 28LP driver - -Add Qualcomm PCIe UNIPHY 28LP driver support present in Qualcomm IPQ5332 -SoC and the phy init sequence. - -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Nitheesh Sekar -Signed-off-by: Varadarajan Narayanan -Link: https://lore.kernel.org/r/20250220094251.230936-3-quic_varada@quicinc.com -Signed-off-by: Vinod Koul ---- - drivers/phy/qualcomm/Kconfig | 12 + - drivers/phy/qualcomm/Makefile | 1 + - .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++ - 3 files changed, 299 insertions(+) - create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c - ---- a/drivers/phy/qualcomm/Kconfig -+++ b/drivers/phy/qualcomm/Kconfig -@@ -154,6 +154,18 @@ config PHY_QCOM_M31_USB - management. This driver is required even for peripheral only or - host only mode configurations. - -+config PHY_QCOM_UNIPHY_PCIE_28LP -+ bool "PCIE UNIPHY 28LP PHY driver" -+ depends on ARCH_QCOM -+ depends on HAS_IOMEM -+ depends on OF -+ select GENERIC_PHY -+ help -+ Enable this to support the PCIe UNIPHY 28LP phy transceiver that -+ is used with PCIe controllers on Qualcomm IPQ5332 chips. It -+ handles PHY initialization, clock management required after -+ resetting the hardware and power management. -+ - config PHY_QCOM_USB_HS - tristate "Qualcomm USB HS PHY module" - depends on USB_ULPI_BUS ---- a/drivers/phy/qualcomm/Makefile -+++ b/drivers/phy/qualcomm/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY) += - obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o - obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o - obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o -+obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o - obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o - obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o - obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o ---- /dev/null -+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c -@@ -0,0 +1,286 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2025, The Linux Foundation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define RST_ASSERT_DELAY_MIN_US 100 -+#define RST_ASSERT_DELAY_MAX_US 150 -+#define PIPE_CLK_DELAY_MIN_US 5000 -+#define PIPE_CLK_DELAY_MAX_US 5100 -+#define CLK_EN_DELAY_MIN_US 30 -+#define CLK_EN_DELAY_MAX_US 50 -+#define CDR_CTRL_REG_1 0x80 -+#define CDR_CTRL_REG_2 0x84 -+#define CDR_CTRL_REG_3 0x88 -+#define CDR_CTRL_REG_4 0x8c -+#define CDR_CTRL_REG_5 0x90 -+#define CDR_CTRL_REG_6 0x94 -+#define CDR_CTRL_REG_7 0x98 -+#define SSCG_CTRL_REG_1 0x9c -+#define SSCG_CTRL_REG_2 0xa0 -+#define SSCG_CTRL_REG_3 0xa4 -+#define SSCG_CTRL_REG_4 0xa8 -+#define SSCG_CTRL_REG_5 0xac -+#define SSCG_CTRL_REG_6 0xb0 -+#define PCS_INTERNAL_CONTROL_2 0x2d8 -+ -+#define PHY_CFG_PLLCFG 0x220 -+#define PHY_CFG_EIOS_DTCT_REG 0x3e4 -+#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 -+ -+enum qcom_uniphy_pcie_type { -+ PHY_TYPE_PCIE = 1, -+ PHY_TYPE_PCIE_GEN2, -+ PHY_TYPE_PCIE_GEN3, -+}; -+ -+struct qcom_uniphy_pcie_regs { -+ u32 offset; -+ u32 val; -+}; -+ -+struct qcom_uniphy_pcie_data { -+ int lane_offset; /* offset between the lane register bases */ -+ u32 phy_type; -+ const struct qcom_uniphy_pcie_regs *init_seq; -+ u32 init_seq_num; -+ u32 pipe_clk_rate; -+}; -+ -+struct qcom_uniphy_pcie { -+ struct phy phy; -+ struct device *dev; -+ const struct qcom_uniphy_pcie_data *data; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct reset_control *resets; -+ void __iomem *base; -+ int lanes; -+}; -+ -+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) -+ -+static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { -+ { -+ .offset = PHY_CFG_PLLCFG, -+ .val = 0x30, -+ }, { -+ .offset = PHY_CFG_EIOS_DTCT_REG, -+ .val = 0x53ef, -+ }, { -+ .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, -+ .val = 0xcf, -+ }, -+}; -+ -+static const struct qcom_uniphy_pcie_data ipq5332_data = { -+ .lane_offset = 0x800, -+ .phy_type = PHY_TYPE_PCIE_GEN3, -+ .init_seq = ipq5332_regs, -+ .init_seq_num = ARRAY_SIZE(ipq5332_regs), -+ .pipe_clk_rate = 250 * MEGA, -+}; -+ -+static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) -+{ -+ const struct qcom_uniphy_pcie_data *data = phy->data; -+ const struct qcom_uniphy_pcie_regs *init_seq; -+ void __iomem *base = phy->base; -+ int lane, i; -+ -+ for (lane = 0; lane < phy->lanes; lane++) { -+ init_seq = data->init_seq; -+ -+ for (i = 0; i < data->init_seq_num; i++) -+ writel(init_seq[i].val, base + init_seq[i].offset); -+ -+ base += data->lane_offset; -+ } -+} -+ -+static int qcom_uniphy_pcie_power_off(struct phy *x) -+{ -+ struct qcom_uniphy_pcie *phy = phy_get_drvdata(x); -+ -+ clk_bulk_disable_unprepare(phy->num_clks, phy->clks); -+ -+ return reset_control_assert(phy->resets); -+} -+ -+static int qcom_uniphy_pcie_power_on(struct phy *x) -+{ -+ struct qcom_uniphy_pcie *phy = phy_get_drvdata(x); -+ int ret; -+ -+ ret = reset_control_assert(phy->resets); -+ if (ret) { -+ dev_err(phy->dev, "reset assert failed (%d)\n", ret); -+ return ret; -+ } -+ -+ usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US); -+ -+ ret = reset_control_deassert(phy->resets); -+ if (ret) { -+ dev_err(phy->dev, "reset deassert failed (%d)\n", ret); -+ return ret; -+ } -+ -+ usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US); -+ -+ ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks); -+ if (ret) { -+ dev_err(phy->dev, "clk prepare and enable failed %d\n", ret); -+ return ret; -+ } -+ -+ usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US); -+ -+ qcom_uniphy_pcie_init(phy); -+ -+ return 0; -+} -+ -+static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev, -+ struct qcom_uniphy_pcie *phy) -+{ -+ struct resource *res; -+ -+ phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); -+ if (IS_ERR(phy->base)) -+ return PTR_ERR(phy->base); -+ -+ phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks); -+ if (phy->num_clks < 0) -+ return phy->num_clks; -+ -+ phy->resets = devm_reset_control_array_get_exclusive(phy->dev); -+ if (IS_ERR(phy->resets)) -+ return PTR_ERR(phy->resets); -+ -+ return 0; -+} -+ -+/* -+ * Register a fixed rate pipe clock. -+ * -+ * The _pipe_clksrc generated by PHY goes to the GCC that gate -+ * controls it. The _pipe_clk coming out of the GCC is requested -+ * by the PHY driver for its operations. -+ * We register the _pipe_clksrc here. The gcc driver takes care -+ * of assigning this _pipe_clksrc as parent to _pipe_clk. -+ * Below picture shows this relationship. -+ * -+ * +---------------+ -+ * | PHY block |<<---------------------------------------+ -+ * | | | -+ * | +-------+ | +-----+ | -+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ -+ * clk | +-------+ | +-----+ -+ * +---------------+ -+ */ -+static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id) -+{ -+ const struct qcom_uniphy_pcie_data *data = phy->data; -+ struct clk_hw *hw; -+ char name[64]; -+ -+ snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id); -+ hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0, -+ data->pipe_clk_rate); -+ if (IS_ERR(hw)) -+ return dev_err_probe(phy->dev, PTR_ERR(hw), -+ "Unable to register %s\n", name); -+ -+ return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw); -+} -+ -+static const struct of_device_id qcom_uniphy_pcie_id_table[] = { -+ { -+ .compatible = "qcom,ipq5332-uniphy-pcie-phy", -+ .data = &ipq5332_data, -+ }, { -+ /* Sentinel */ -+ }, -+}; -+MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); -+ -+static const struct phy_ops pcie_ops = { -+ .power_on = qcom_uniphy_pcie_power_on, -+ .power_off = qcom_uniphy_pcie_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int qcom_uniphy_pcie_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct qcom_uniphy_pcie *phy; -+ struct phy *generic_phy; -+ int ret; -+ -+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, phy); -+ phy->dev = &pdev->dev; -+ -+ phy->data = of_device_get_match_data(dev); -+ if (!phy->data) -+ return -EINVAL; -+ -+ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes); -+ if (ret) -+ return dev_err_probe(dev, ret, "Couldn't read num-lanes\n"); -+ -+ ret = qcom_uniphy_pcie_get_resources(pdev, phy); -+ if (ret < 0) -+ return dev_err_probe(&pdev->dev, ret, -+ "failed to get resources: %d\n", ret); -+ -+ generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops); -+ if (IS_ERR(generic_phy)) -+ return PTR_ERR(generic_phy); -+ -+ phy_set_drvdata(generic_phy, phy); -+ -+ ret = phy_pipe_clk_register(phy, generic_phy->id); -+ if (ret) -+ dev_err(&pdev->dev, "failed to register phy pipe clk\n"); -+ -+ phy_provider = devm_of_phy_provider_register(phy->dev, -+ of_phy_simple_xlate); -+ if (IS_ERR(phy_provider)) -+ return PTR_ERR(phy_provider); -+ -+ return 0; -+} -+ -+static struct platform_driver qcom_uniphy_pcie_driver = { -+ .probe = qcom_uniphy_pcie_probe, -+ .driver = { -+ .name = "qcom-uniphy-pcie", -+ .of_match_table = qcom_uniphy_pcie_id_table, -+ }, -+}; -+ -+module_platform_driver(qcom_uniphy_pcie_driver); -+ -+MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommax/patches-6.18/0046-v6.16-phy-qualcomm-qcom-uniphy-pcie-28LP-add-support-for-I.patch b/target/linux/qualcommax/patches-6.18/0046-v6.16-phy-qualcomm-qcom-uniphy-pcie-28LP-add-support-for-I.patch deleted file mode 100644 index 4c727fcc611..00000000000 --- a/target/linux/qualcommax/patches-6.18/0046-v6.16-phy-qualcomm-qcom-uniphy-pcie-28LP-add-support-for-I.patch +++ /dev/null @@ -1,86 +0,0 @@ -From dfc820d2f8a8ea90bbc02269b5362e3678e58cac Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Wed, 26 Mar 2025 12:10:56 +0400 -Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018 - -The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018. -Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018. - -Signed-off-by: Nitheesh Sekar -Signed-off-by: Sricharan Ramabadhran -Reviewed-by: Dmitry Baryshkov -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-2-e1828fef06c9@outlook.com -Signed-off-by: Vinod Koul ---- - .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 45 +++++++++++++++++++ - 1 file changed, 45 insertions(+) - ---- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c -+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c -@@ -75,6 +75,40 @@ struct qcom_uniphy_pcie { - - #define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy) - -+static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = { -+ { -+ .offset = SSCG_CTRL_REG_4, -+ .val = 0x1cb9, -+ }, { -+ .offset = SSCG_CTRL_REG_5, -+ .val = 0x023a, -+ }, { -+ .offset = SSCG_CTRL_REG_3, -+ .val = 0xd360, -+ }, { -+ .offset = SSCG_CTRL_REG_1, -+ .val = 0x1, -+ }, { -+ .offset = SSCG_CTRL_REG_2, -+ .val = 0xeb, -+ }, { -+ .offset = CDR_CTRL_REG_4, -+ .val = 0x3f9, -+ }, { -+ .offset = CDR_CTRL_REG_5, -+ .val = 0x1c9, -+ }, { -+ .offset = CDR_CTRL_REG_2, -+ .val = 0x419, -+ }, { -+ .offset = CDR_CTRL_REG_1, -+ .val = 0x200, -+ }, { -+ .offset = PCS_INTERNAL_CONTROL_2, -+ .val = 0xf101, -+ }, -+}; -+ - static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = { - { - .offset = PHY_CFG_PLLCFG, -@@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_reg - }, - }; - -+static const struct qcom_uniphy_pcie_data ipq5018_data = { -+ .lane_offset = 0x800, -+ .phy_type = PHY_TYPE_PCIE_GEN2, -+ .init_seq = ipq5018_regs, -+ .init_seq_num = ARRAY_SIZE(ipq5018_regs), -+ .pipe_clk_rate = 125 * MEGA, -+}; -+ - static const struct qcom_uniphy_pcie_data ipq5332_data = { - .lane_offset = 0x800, - .phy_type = PHY_TYPE_PCIE_GEN3, -@@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register( - - static const struct of_device_id qcom_uniphy_pcie_id_table[] = { - { -+ .compatible = "qcom,ipq5018-uniphy-pcie-phy", -+ .data = &ipq5018_data, -+ }, { - .compatible = "qcom,ipq5332-uniphy-pcie-phy", - .data = &ipq5332_data, - }, { diff --git a/target/linux/qualcommax/patches-6.18/0047-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch b/target/linux/qualcommax/patches-6.18/0047-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch deleted file mode 100644 index 753a53711b9..00000000000 --- a/target/linux/qualcommax/patches-6.18/0047-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 3e5127469a8d41153fb30031a271788f52dd17ec Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Wed, 26 Mar 2025 12:10:58 +0400 -Subject: [PATCH] PCI: qcom: Add support for IPQ5018 - -Add IPQ5018 platform with is based on Qcom IP rev. 2.9.0 and Synopsys IP -rev. 5.00a. - -The platform itself has two PCIe Gen2 controllers: one single-lane and -one dual-lane. So add the IPQ5018 compatible and re-use 2_9_0 ops. - -Signed-off-by: Nitheesh Sekar -Signed-off-by: Sricharan R -Signed-off-by: George Moussalem -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20250326-ipq5018-pcie-v7-4-e1828fef06c9@outlook.com ---- - drivers/pci/controller/dwc/pcie-qcom.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -1832,6 +1832,7 @@ static const struct of_device_id qcom_pc - { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, - { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, - { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, -+ { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 }, - { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, - { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, - { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, diff --git a/target/linux/qualcommax/patches-6.18/0048-v6.16-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch b/target/linux/qualcommax/patches-6.18/0048-v6.16-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch deleted file mode 100644 index a7fceeba653..00000000000 --- a/target/linux/qualcommax/patches-6.18/0048-v6.16-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch +++ /dev/null @@ -1,286 +0,0 @@ -From 18a5bf00a02ca54d51266b861518f2844c4f08d7 Mon Sep 17 00:00:00 2001 -From: Nitheesh Sekar -Date: Wed, 14 May 2025 09:52:13 +0400 -Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes - -Add phy and controller nodes for a 2-lane Gen2 and -a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and -one global interrupt. - -NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2. - -Signed-off-by: Nitheesh Sekar -Signed-off-by: Sricharan R -Reviewed-by: Manivannan Sadhasivam -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250514-ipq5018-pcie-v10-1-5b42a8eff7ea@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 240 +++++++++++++++++++++++++- - 1 file changed, 238 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -147,6 +147,40 @@ - status = "disabled"; - }; - -+ pcie1_phy: phy@7e000 { -+ compatible = "qcom,ipq5018-uniphy-pcie-phy"; -+ reg = <0x0007e000 0x800>; -+ -+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; -+ -+ resets = <&gcc GCC_PCIE1_PHY_BCR>, -+ <&gcc GCC_PCIE1PHY_PHY_BCR>; -+ -+ #clock-cells = <0>; -+ #phy-cells = <0>; -+ -+ num-lanes = <1>; -+ -+ status = "disabled"; -+ }; -+ -+ pcie0_phy: phy@86000 { -+ compatible = "qcom,ipq5018-uniphy-pcie-phy"; -+ reg = <0x00086000 0x1000>; -+ -+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ -+ resets = <&gcc GCC_PCIE0_PHY_BCR>, -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ -+ #clock-cells = <0>; -+ #phy-cells = <0>; -+ -+ num-lanes = <2>; -+ -+ status = "disabled"; -+ }; -+ - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-tlmm"; - reg = <0x01000000 0x300000>; -@@ -170,8 +204,8 @@ - reg = <0x01800000 0x80000>; - clocks = <&xo_board_clk>, - <&sleep_clk>, -- <0>, -- <0>, -+ <&pcie0_phy>, -+ <&pcie1_phy>, - <0>, - <0>, - <0>, -@@ -387,6 +421,208 @@ - status = "disabled"; - }; - }; -+ -+ pcie1: pcie@80000000 { -+ compatible = "qcom,pcie-ipq5018"; -+ reg = <0x80000000 0xf1d>, -+ <0x80000f20 0xa8>, -+ <0x80001000 0x1000>, -+ <0x00078000 0x3000>, -+ <0x80100000 0x1000>, -+ <0x0007b000 0x1000>; -+ reg-names = "dbi", -+ "elbi", -+ "atu", -+ "parf", -+ "config", -+ "mhi"; -+ device_type = "pci"; -+ linux,pci-domain = <1>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* The controller supports Gen3, but the connected PHY is Gen2-capable */ -+ max-link-speed = <2>; -+ -+ phys = <&pcie1_phy>; -+ phy-names ="pciephy"; -+ -+ ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, -+ <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; -+ -+ msi-map = <0x0 &v2m0 0x0 0xff8>; -+ -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "msi0", -+ "msi1", -+ "msi2", -+ "msi3", -+ "msi4", -+ "msi5", -+ "msi6", -+ "msi7", -+ "global"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; -+ -+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, -+ <&gcc GCC_PCIE1_AXI_M_CLK>, -+ <&gcc GCC_PCIE1_AXI_S_CLK>, -+ <&gcc GCC_PCIE1_AHB_CLK>, -+ <&gcc GCC_PCIE1_AUX_CLK>, -+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; -+ clock-names = "iface", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "aux", -+ "axi_bridge"; -+ -+ resets = <&gcc GCC_PCIE1_PIPE_ARES>, -+ <&gcc GCC_PCIE1_SLEEP_ARES>, -+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, -+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>, -+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, -+ <&gcc GCC_PCIE1_AHB_ARES>, -+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, -+ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; -+ reset-names = "pipe", -+ "sleep", -+ "sticky", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "axi_m_sticky", -+ "axi_s_sticky"; -+ -+ status = "disabled"; -+ -+ pcie@0 { -+ device_type = "pci"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; -+ -+ pcie0: pcie@a0000000 { -+ compatible = "qcom,pcie-ipq5018"; -+ reg = <0xa0000000 0xf1d>, -+ <0xa0000f20 0xa8>, -+ <0xa0001000 0x1000>, -+ <0x00080000 0x3000>, -+ <0xa0100000 0x1000>, -+ <0x00083000 0x1000>; -+ reg-names = "dbi", -+ "elbi", -+ "atu", -+ "parf", -+ "config", -+ "mhi"; -+ device_type = "pci"; -+ linux,pci-domain = <0>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <2>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ /* The controller supports Gen3, but the connected PHY is Gen2-capable */ -+ max-link-speed = <2>; -+ -+ phys = <&pcie0_phy>; -+ phy-names ="pciephy"; -+ -+ ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, -+ <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; -+ -+ msi-map = <0x0 &v2m0 0x0 0xff8>; -+ -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "msi0", -+ "msi1", -+ "msi2", -+ "msi3", -+ "msi4", -+ "msi5", -+ "msi6", -+ "msi7", -+ "global"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; -+ -+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, -+ <&gcc GCC_PCIE0_AXI_M_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_CLK>, -+ <&gcc GCC_PCIE0_AHB_CLK>, -+ <&gcc GCC_PCIE0_AUX_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; -+ clock-names = "iface", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "aux", -+ "axi_bridge"; -+ -+ resets = <&gcc GCC_PCIE0_PIPE_ARES>, -+ <&gcc GCC_PCIE0_SLEEP_ARES>, -+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, -+ <&gcc GCC_PCIE0_AHB_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; -+ reset-names = "pipe", -+ "sleep", -+ "sticky", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "axi_m_sticky", -+ "axi_s_sticky"; -+ -+ status = "disabled"; -+ -+ pcie@0 { -+ device_type = "pci"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; - }; - - timer { diff --git a/target/linux/qualcommax/patches-6.18/0049-v6.16-arm64-dts-qcom-ipq5018-enable-the-download-mode-supp.patch b/target/linux/qualcommax/patches-6.18/0049-v6.16-arm64-dts-qcom-ipq5018-enable-the-download-mode-supp.patch deleted file mode 100644 index 08200516a3f..00000000000 --- a/target/linux/qualcommax/patches-6.18/0049-v6.16-arm64-dts-qcom-ipq5018-enable-the-download-mode-supp.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 43fefd6c71291b5793e7c4052b6e3e54d1d87715 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 12 May 2025 18:36:47 +0400 -Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the download mode support - -Enable support for download mode to collect RAM dumps in case of a -system crash, allowing post mortem analysis. - -Signed-off-by: George Moussalem -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250512-ipq5018-syscon-v1-2-eb1ad2414c3c@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -79,6 +79,7 @@ - firmware { - scm { - compatible = "qcom,scm-ipq5018", "qcom,scm"; -+ qcom,dload-mode = <&tcsr 0x6100>; - qcom,sdi-enabled; - }; - }; -@@ -221,6 +222,11 @@ - #hwlock-cells = <1>; - }; - -+ tcsr: syscon@1937000 { -+ compatible = "qcom,tcsr-ipq5018", "syscon"; -+ reg = <0x01937000 0x21000>; -+ }; -+ - sdhc_1: mmc@7804000 { - compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.18/0050-v6.15-thermal-drivers-tsens-Add-TSENS-enable-and-calibrati.patch b/target/linux/qualcommax/patches-6.18/0050-v6.15-thermal-drivers-tsens-Add-TSENS-enable-and-calibrati.patch deleted file mode 100644 index bf675556ad0..00000000000 --- a/target/linux/qualcommax/patches-6.18/0050-v6.15-thermal-drivers-tsens-Add-TSENS-enable-and-calibrati.patch +++ /dev/null @@ -1,297 +0,0 @@ -From ff0cf0ab9073727a67f9902dba77a758654ae895 Mon Sep 17 00:00:00 2001 -From: Praveenkumar I -Date: Mon, 10 Feb 2025 17:34:32 +0530 -Subject: [PATCH] thermal/drivers/tsens: Add TSENS enable and calibration - support for V2 - -SoCs without RPM need to enable sensors and calibrate them from the kernel. -The IPQ5332 and IPQ5424 use the tsens v2.3.3 IP and do not have RPM. -Therefore, add a new calibration function for V2, as the tsens.c calib -function only supports V1. Also add new feature_config, ops and data for -IPQ5332, IPQ5424. - -Although the TSENS IP supports 16 sensors, not all are used. The hw_id -is used to enable the relevant sensors. - -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Praveenkumar I -Signed-off-by: Manikanta Mylavarapu -Link: https://lore.kernel.org/r/20250210120436.821684-3-quic_mmanikan@quicinc.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/qcom/tsens-v2.c | 178 ++++++++++++++++++++++++++++++++ - drivers/thermal/qcom/tsens.c | 8 +- - drivers/thermal/qcom/tsens.h | 3 + - 3 files changed, 188 insertions(+), 1 deletion(-) - ---- a/drivers/thermal/qcom/tsens-v2.c -+++ b/drivers/thermal/qcom/tsens-v2.c -@@ -4,13 +4,32 @@ - * Copyright (c) 2018, Linaro Limited - */ - -+#include - #include -+#include - #include - #include "tsens.h" - - /* ----- SROT ------ */ - #define SROT_HW_VER_OFF 0x0000 - #define SROT_CTRL_OFF 0x0004 -+#define SROT_MEASURE_PERIOD 0x0008 -+#define SROT_Sn_CONVERSION 0x0060 -+#define V2_SHIFT_DEFAULT 0x0003 -+#define V2_SLOPE_DEFAULT 0x0cd0 -+#define V2_CZERO_DEFAULT 0x016a -+#define ONE_PT_SLOPE 0x0cd0 -+#define TWO_PT_SHIFTED_GAIN 921600 -+#define ONE_PT_CZERO_CONST 94 -+#define SW_RST_DEASSERT 0x0 -+#define SW_RST_ASSERT 0x1 -+#define MEASURE_PERIOD_2mSEC 0x1 -+#define RESULT_FORMAT_TEMP 0x1 -+#define TSENS_ENABLE 0x1 -+#define SENSOR_CONVERSION(n) (((n) * 4) + SROT_Sn_CONVERSION) -+#define CONVERSION_SHIFT_MASK GENMASK(24, 23) -+#define CONVERSION_SLOPE_MASK GENMASK(22, 10) -+#define CONVERSION_CZERO_MASK GENMASK(9, 0) - - /* ----- TM ------ */ - #define TM_INT_EN_OFF 0x0004 -@@ -50,6 +69,17 @@ static struct tsens_features ipq8074_fea - .trip_max_temp = 204000, - }; - -+static struct tsens_features ipq5332_feat = { -+ .ver_major = VER_2_X_NO_RPM, -+ .crit_int = 1, -+ .combo_int = 1, -+ .adc = 0, -+ .srot_split = 1, -+ .max_sensors = 16, -+ .trip_min_temp = 0, -+ .trip_max_temp = 204000, -+}; -+ - static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { - /* ----- SROT ------ */ - /* VERSION */ -@@ -59,6 +89,10 @@ static const struct reg_field tsens_v2_r - /* CTRL_OFF */ - [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), - [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), -+ [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 18), -+ [CODE_OR_TEMP] = REG_FIELD(SROT_CTRL_OFF, 21, 21), -+ -+ [MAIN_MEASURE_PERIOD] = REG_FIELD(SROT_MEASURE_PERIOD, 0, 7), - - /* ----- TM ------ */ - /* INTERRUPT ENABLE */ -@@ -104,6 +138,128 @@ static const struct reg_field tsens_v2_r - [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), - }; - -+static int tsens_v2_calibrate_sensor(struct device *dev, struct tsens_sensor *sensor, -+ struct regmap *map, u32 mode, u32 base0, u32 base1) -+{ -+ u32 shift = V2_SHIFT_DEFAULT; -+ u32 slope = V2_SLOPE_DEFAULT; -+ u32 czero = V2_CZERO_DEFAULT; -+ char name[20]; -+ u32 val; -+ int ret; -+ -+ /* Read offset value */ -+ ret = snprintf(name, sizeof(name), "tsens_sens%d_off", sensor->hw_id); -+ if (ret < 0) -+ return ret; -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, name, &sensor->offset); -+ if (ret) -+ return ret; -+ -+ /* Based on calib mode, program SHIFT, SLOPE and CZERO */ -+ switch (mode) { -+ case TWO_PT_CALIB: -+ slope = (TWO_PT_SHIFTED_GAIN / (base1 - base0)); -+ -+ czero = (base0 + sensor->offset - ((base1 - base0) / 3)); -+ -+ break; -+ case ONE_PT_CALIB2: -+ czero = base0 + sensor->offset - ONE_PT_CZERO_CONST; -+ -+ slope = ONE_PT_SLOPE; -+ -+ break; -+ default: -+ dev_dbg(dev, "calibrationless mode\n"); -+ } -+ -+ val = FIELD_PREP(CONVERSION_SHIFT_MASK, shift) | -+ FIELD_PREP(CONVERSION_SLOPE_MASK, slope) | -+ FIELD_PREP(CONVERSION_CZERO_MASK, czero); -+ -+ regmap_write(map, SENSOR_CONVERSION(sensor->hw_id), val); -+ -+ return 0; -+} -+ -+static int tsens_v2_calibration(struct tsens_priv *priv) -+{ -+ struct device *dev = priv->dev; -+ u32 mode, base0, base1; -+ int i, ret; -+ -+ if (priv->num_sensors > MAX_SENSORS) -+ return -EINVAL; -+ -+ ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); -+ if (ret == -ENOENT) -+ dev_warn(priv->dev, "Calibration data not present in DT\n"); -+ if (ret < 0) -+ return ret; -+ -+ dev_dbg(priv->dev, "calibration mode is %d\n", mode); -+ -+ ret = nvmem_cell_read_variable_le_u32(priv->dev, "base0", &base0); -+ if (ret < 0) -+ return ret; -+ -+ ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); -+ if (ret < 0) -+ return ret; -+ -+ /* Calibrate each sensor */ -+ for (i = 0; i < priv->num_sensors; i++) { -+ ret = tsens_v2_calibrate_sensor(dev, &priv->sensor[i], priv->srot_map, -+ mode, base0, base1); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int __init init_tsens_v2_no_rpm(struct tsens_priv *priv) -+{ -+ struct device *dev = priv->dev; -+ int i, ret; -+ u32 val = 0; -+ -+ ret = init_common(priv); -+ if (ret < 0) -+ return ret; -+ -+ priv->rf[CODE_OR_TEMP] = devm_regmap_field_alloc(dev, priv->srot_map, -+ priv->fields[CODE_OR_TEMP]); -+ if (IS_ERR(priv->rf[CODE_OR_TEMP])) -+ return PTR_ERR(priv->rf[CODE_OR_TEMP]); -+ -+ priv->rf[MAIN_MEASURE_PERIOD] = devm_regmap_field_alloc(dev, priv->srot_map, -+ priv->fields[MAIN_MEASURE_PERIOD]); -+ if (IS_ERR(priv->rf[MAIN_MEASURE_PERIOD])) -+ return PTR_ERR(priv->rf[MAIN_MEASURE_PERIOD]); -+ -+ regmap_field_write(priv->rf[TSENS_SW_RST], SW_RST_ASSERT); -+ -+ regmap_field_write(priv->rf[MAIN_MEASURE_PERIOD], MEASURE_PERIOD_2mSEC); -+ -+ /* Enable available sensors */ -+ for (i = 0; i < priv->num_sensors; i++) -+ val |= 1 << priv->sensor[i].hw_id; -+ -+ regmap_field_write(priv->rf[SENSOR_EN], val); -+ -+ /* Select temperature format, unit is deci-Celsius */ -+ regmap_field_write(priv->rf[CODE_OR_TEMP], RESULT_FORMAT_TEMP); -+ -+ regmap_field_write(priv->rf[TSENS_SW_RST], SW_RST_DEASSERT); -+ -+ regmap_field_write(priv->rf[TSENS_EN], TSENS_ENABLE); -+ -+ return 0; -+} -+ - static const struct tsens_ops ops_generic_v2 = { - .init = init_common, - .get_temp = get_temp_tsens_valid, -@@ -122,6 +278,28 @@ struct tsens_plat_data data_ipq8074 = { - .fields = tsens_v2_regfields, - }; - -+static const struct tsens_ops ops_ipq5332 = { -+ .init = init_tsens_v2_no_rpm, -+ .get_temp = get_temp_tsens_valid, -+ .calibrate = tsens_v2_calibration, -+}; -+ -+const struct tsens_plat_data data_ipq5332 = { -+ .num_sensors = 5, -+ .ops = &ops_ipq5332, -+ .hw_ids = (unsigned int []){11, 12, 13, 14, 15}, -+ .feat = &ipq5332_feat, -+ .fields = tsens_v2_regfields, -+}; -+ -+const struct tsens_plat_data data_ipq5424 = { -+ .num_sensors = 7, -+ .ops = &ops_ipq5332, -+ .hw_ids = (unsigned int []){9, 10, 11, 12, 13, 14, 15}, -+ .feat = &ipq5332_feat, -+ .fields = tsens_v2_regfields, -+}; -+ - /* Kept around for backward compatibility with old msm8996.dtsi */ - struct tsens_plat_data data_8996 = { - .num_sensors = 13, ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -975,7 +975,7 @@ int __init init_common(struct tsens_priv - ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); - if (ret) - goto err_put_device; -- if (!enabled) { -+ if (!enabled && (tsens_version(priv) != VER_2_X_NO_RPM)) { - dev_err(dev, "%s: device not enabled\n", __func__); - ret = -ENODEV; - goto err_put_device; -@@ -1102,6 +1102,12 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t - - static const struct of_device_id tsens_table[] = { - { -+ .compatible = "qcom,ipq5332-tsens", -+ .data = &data_ipq5332, -+ }, { -+ .compatible = "qcom,ipq5424-tsens", -+ .data = &data_ipq5424, -+ }, { - .compatible = "qcom,ipq8064-tsens", - .data = &data_8960, - }, { ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -35,6 +35,7 @@ enum tsens_ver { - VER_0_1, - VER_1_X, - VER_2_X, -+ VER_2_X_NO_RPM, - }; - - enum tsens_irq_type { -@@ -168,6 +169,7 @@ enum regfield_ids { - TSENS_SW_RST, - SENSOR_EN, - CODE_OR_TEMP, -+ MAIN_MEASURE_PERIOD, - - /* ----- TM ------ */ - /* TRDY */ -@@ -651,5 +653,6 @@ extern struct tsens_plat_data data_tsens - - /* TSENS v2 targets */ - extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; -+extern const struct tsens_plat_data data_ipq5332, data_ipq5424; - - #endif /* __QCOM_TSENS_H__ */ diff --git a/target/linux/qualcommax/patches-6.18/0051-v6.16-thermal-drivers-qcom-tsens-Update-conditions-to-stri.patch b/target/linux/qualcommax/patches-6.18/0051-v6.16-thermal-drivers-qcom-tsens-Update-conditions-to-stri.patch deleted file mode 100644 index 7de3472a65e..00000000000 --- a/target/linux/qualcommax/patches-6.18/0051-v6.16-thermal-drivers-qcom-tsens-Update-conditions-to-stri.patch +++ /dev/null @@ -1,69 +0,0 @@ -From e3f90f167a49902cda2408f7e91cca0dcfd5040a Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Fri, 28 Feb 2025 09:11:36 +0400 -Subject: [PATCH] thermal/drivers/qcom/tsens: Update conditions to strictly - evaluate for IP v2+ - -TSENS v2.0+ leverage features not available to prior versions such as -updated interrupts init routine, masked interrupts, and watchdog. -Currently, the checks in place evaluate whether the IP version is greater -than v1 which invalidates when updates to v1 or v1 minor versions are -implemented. As such, update the conditional statements to strictly -evaluate whether the version is greater than or equal to v2 (inclusive). - -Signed-off-by: George Moussalem -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Amit Kucheria -Link: https://lore.kernel.org/r/DS7PR19MB8883434CAA053648E22AA8AC9DCC2@DS7PR19MB8883.namprd19.prod.outlook.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/qcom/tsens.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -447,7 +447,7 @@ static void tsens_set_interrupt(struct t - dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__, - irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW", - enable ? "en" : "dis"); -- if (tsens_version(priv) > VER_1_X) -+ if (tsens_version(priv) >= VER_2_X) - tsens_set_interrupt_v2(priv, hw_id, irq_type, enable); - else - tsens_set_interrupt_v1(priv, hw_id, irq_type, enable); -@@ -499,7 +499,7 @@ static int tsens_read_irq_state(struct t - ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear); - if (ret) - return ret; -- if (tsens_version(priv) > VER_1_X) { -+ if (tsens_version(priv) >= VER_2_X) { - ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask); - if (ret) - return ret; -@@ -543,7 +543,7 @@ static int tsens_read_irq_state(struct t - - static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver) - { -- if (ver > VER_1_X) -+ if (ver >= VER_2_X) - return mask & (1 << hw_id); - - /* v1, v0.1 don't have a irq mask register */ -@@ -733,7 +733,7 @@ static int tsens_set_trips(struct therma - static int tsens_enable_irq(struct tsens_priv *priv) - { - int ret; -- int val = tsens_version(priv) > VER_1_X ? 7 : 1; -+ int val = tsens_version(priv) >= VER_2_X ? 7 : 1; - - ret = regmap_field_write(priv->rf[INT_EN], val); - if (ret < 0) -@@ -1040,7 +1040,7 @@ int __init init_common(struct tsens_priv - } - } - -- if (tsens_version(priv) > VER_1_X && ver_minor > 2) { -+ if (tsens_version(priv) >= VER_2_X && ver_minor > 2) { - /* Watchdog is present only on v2.3+ */ - priv->feat->has_watchdog = 1; - for (i = WDOG_BARK_STATUS; i <= CC_MON_MASK; i++) { diff --git a/target/linux/qualcommax/patches-6.18/0052-v6.16-thermal-drivers-qcom-tsens-Add-support-for-tsens-v1-.patch b/target/linux/qualcommax/patches-6.18/0052-v6.16-thermal-drivers-qcom-tsens-Add-support-for-tsens-v1-.patch deleted file mode 100644 index 0ed4f17501b..00000000000 --- a/target/linux/qualcommax/patches-6.18/0052-v6.16-thermal-drivers-qcom-tsens-Add-support-for-tsens-v1-.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 19f9b02ebc8fe3babefbe76a37c74c5f4c174de1 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Fri, 28 Feb 2025 09:11:37 +0400 -Subject: [PATCH] thermal/drivers/qcom/tsens: Add support for tsens v1 without - RPM - -Adding generic support for SoCs with tsens v1.0 IP with no RPM. -Due to lack of RPM, tsens has to be reset and enabled in the driver -init. SoCs can have support for more sensors than those which will -actually be enabled. As such, init will only enable those explicitly -added to the hw_ids array. - -Co-developed-by: Sricharan Ramabadhran -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: George Moussalem -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/DS7PR19MB8883C5D7974C7735E23923769DCC2@DS7PR19MB8883.namprd19.prod.outlook.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/qcom/tsens-v1.c | 48 +++++++++++++++++++++++++++++++++ - drivers/thermal/qcom/tsens.c | 14 +++++++--- - drivers/thermal/qcom/tsens.h | 1 + - 3 files changed, 59 insertions(+), 4 deletions(-) - ---- a/drivers/thermal/qcom/tsens-v1.c -+++ b/drivers/thermal/qcom/tsens-v1.c -@@ -79,6 +79,17 @@ static struct tsens_features tsens_v1_fe - .trip_max_temp = 120000, - }; - -+static struct tsens_features tsens_v1_no_rpm_feat = { -+ .ver_major = VER_1_X_NO_RPM, -+ .crit_int = 0, -+ .combo_int = 0, -+ .adc = 1, -+ .srot_split = 1, -+ .max_sensors = 11, -+ .trip_min_temp = -40000, -+ .trip_max_temp = 120000, -+}; -+ - static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { - /* ----- SROT ------ */ - /* VERSION */ -@@ -150,6 +161,43 @@ static int __init init_8956(struct tsens - return init_common(priv); - } - -+static int __init init_tsens_v1_no_rpm(struct tsens_priv *priv) -+{ -+ int i, ret; -+ u32 mask = 0; -+ -+ ret = init_common(priv); -+ if (ret < 0) { -+ dev_err(priv->dev, "Init common failed %d\n", ret); -+ return ret; -+ } -+ -+ ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1); -+ if (ret) { -+ dev_err(priv->dev, "Reset failed\n"); -+ return ret; -+ } -+ -+ for (i = 0; i < priv->num_sensors; i++) -+ mask |= BIT(priv->sensor[i].hw_id); -+ -+ ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask); -+ if (ret) { -+ dev_err(priv->dev, "Sensor Enable failed\n"); -+ return ret; -+ } -+ -+ ret = regmap_field_write(priv->rf[TSENS_EN], 1); -+ if (ret) { -+ dev_err(priv->dev, "Enable failed\n"); -+ return ret; -+ } -+ -+ ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0); -+ -+ return ret; -+} -+ - static const struct tsens_ops ops_generic_v1 = { - .init = init_common, - .calibrate = calibrate_v1, ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -975,10 +975,16 @@ int __init init_common(struct tsens_priv - ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); - if (ret) - goto err_put_device; -- if (!enabled && (tsens_version(priv) != VER_2_X_NO_RPM)) { -- dev_err(dev, "%s: device not enabled\n", __func__); -- ret = -ENODEV; -- goto err_put_device; -+ if (!enabled) { -+ switch (tsens_version(priv)) { -+ case VER_1_X_NO_RPM: -+ case VER_2_X_NO_RPM: -+ break; -+ default: -+ dev_err(dev, "%s: device not enabled\n", __func__); -+ ret = -ENODEV; -+ goto err_put_device; -+ } - } - - priv->rf[SENSOR_EN] = devm_regmap_field_alloc(dev, priv->srot_map, ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -34,6 +34,7 @@ enum tsens_ver { - VER_0 = 0, - VER_0_1, - VER_1_X, -+ VER_1_X_NO_RPM, - VER_2_X, - VER_2_X_NO_RPM, - }; diff --git a/target/linux/qualcommax/patches-6.18/0053-v6.16-thermal-drivers-qcom-tsens-Add-support-for-IPQ5018-t.patch b/target/linux/qualcommax/patches-6.18/0053-v6.16-thermal-drivers-qcom-tsens-Add-support-for-IPQ5018-t.patch deleted file mode 100644 index 1c09ffc70ed..00000000000 --- a/target/linux/qualcommax/patches-6.18/0053-v6.16-thermal-drivers-qcom-tsens-Add-support-for-IPQ5018-t.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 04b31cc53fe0df0e87a37d18a3c0363d7dee218f Mon Sep 17 00:00:00 2001 -From: Sricharan Ramabadhran -Date: Fri, 28 Feb 2025 09:11:38 +0400 -Subject: [PATCH] thermal/drivers/qcom/tsens: Add support for IPQ5018 tsens - -IPQ5018 has tsens IP V1.0, 5 sensors of which 4 are in use and 1 -interrupt. The IP does not have a RPM, hence use init routine for -tsens v1.0 without RPM which does not early enable. - -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/DS7PR19MB8883BD0E36C08DD1D03CE1CB9DCC2@DS7PR19MB8883.namprd19.prod.outlook.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/qcom/tsens-v1.c | 14 ++++++++++++++ - drivers/thermal/qcom/tsens.c | 3 +++ - drivers/thermal/qcom/tsens.h | 3 +++ - 3 files changed, 20 insertions(+) - ---- a/drivers/thermal/qcom/tsens-v1.c -+++ b/drivers/thermal/qcom/tsens-v1.c -@@ -242,3 +242,17 @@ struct tsens_plat_data data_8976 = { - .feat = &tsens_v1_feat, - .fields = tsens_v1_regfields, - }; -+ -+const struct tsens_ops ops_ipq5018 = { -+ .init = init_tsens_v1_no_rpm, -+ .calibrate = tsens_calibrate_common, -+ .get_temp = get_temp_tsens_valid, -+}; -+ -+const struct tsens_plat_data data_ipq5018 = { -+ .num_sensors = 5, -+ .ops = &ops_ipq5018, -+ .hw_ids = (unsigned int []){0, 1, 2, 3, 4}, -+ .feat = &tsens_v1_no_rpm_feat, -+ .fields = tsens_v1_regfields, -+}; ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -1108,6 +1108,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t - - static const struct of_device_id tsens_table[] = { - { -+ .compatible = "qcom,ipq5018-tsens", -+ .data = &data_ipq5018, -+ }, { - .compatible = "qcom,ipq5332-tsens", - .data = &data_ipq5332, - }, { ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -652,6 +652,9 @@ extern struct tsens_plat_data data_8226, - /* TSENS v1 targets */ - extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956; - -+/* TSENS v1 with no RPM targets */ -+extern const struct tsens_plat_data data_ipq5018; -+ - /* TSENS v2 targets */ - extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; - extern const struct tsens_plat_data data_ipq5332, data_ipq5424; diff --git a/target/linux/qualcommax/patches-6.18/0054-v6.18-arm64-dts-qcom-ipq5018-Add-tsens-node.patch b/target/linux/qualcommax/patches-6.18/0054-v6.18-arm64-dts-qcom-ipq5018-Add-tsens-node.patch deleted file mode 100644 index 81e9302bd87..00000000000 --- a/target/linux/qualcommax/patches-6.18/0054-v6.18-arm64-dts-qcom-ipq5018-Add-tsens-node.patch +++ /dev/null @@ -1,240 +0,0 @@ -From 450a80623e3b8bb5dae59e0d56046fc3d0a88f3b Mon Sep 17 00:00:00 2001 -From: Sricharan Ramabadhran -Date: Thu, 12 Jun 2025 10:46:14 +0400 -Subject: arm64: dts: qcom: ipq5018: Add tsens node - -IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use. -There is no RPM, so tsens has to be manually enabled. Adding the tsens -and nvmem nodes and adding 4 thermal sensors (zones). The critical trip -temperature is set to 120'C with an action to reboot. - -In addition, adding a cooling device to the CPU thermal zone which uses -CPU frequency scaling. - -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Sricharan Ramabadhran -Signed-off-by: George Moussalem -Reviewed-by: Konrad Dybcio -[bjorn: Added tsens-v1 fallback compatible, per binding] -Link: https://lore.kernel.org/r/20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++++++++++ - 1 file changed, 178 insertions(+) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - / { - interrupt-parent = <&intc>; -@@ -39,6 +40,7 @@ - next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; -+ #cooling-cells = <2>; - }; - - cpu1: cpu@1 { -@@ -49,6 +51,7 @@ - next-level-cache = <&l2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - operating-points-v2 = <&cpu_opp_table>; -+ #cooling-cells = <2>; - }; - - l2_0: l2-cache { -@@ -182,6 +185,117 @@ - status = "disabled"; - }; - -+ qfprom: qfprom@a0000 { -+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; -+ reg = <0x000a0000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ tsens_mode: mode@249 { -+ reg = <0x249 0x1>; -+ bits = <0 3>; -+ }; -+ -+ tsens_base1: base1@249 { -+ reg = <0x249 0x2>; -+ bits = <3 8>; -+ }; -+ -+ tsens_base2: base2@24a { -+ reg = <0x24a 0x2>; -+ bits = <3 8>; -+ }; -+ -+ tsens_s0_p1: s0-p1@24b { -+ reg = <0x24b 0x2>; -+ bits = <2 6>; -+ }; -+ -+ tsens_s0_p2: s0-p2@24c { -+ reg = <0x24c 0x1>; -+ bits = <1 6>; -+ }; -+ -+ tsens_s1_p1: s1-p1@24c { -+ reg = <0x24c 0x2>; -+ bits = <7 6>; -+ }; -+ -+ tsens_s1_p2: s1-p2@24d { -+ reg = <0x24d 0x2>; -+ bits = <5 6>; -+ }; -+ -+ tsens_s2_p1: s2-p1@24e { -+ reg = <0x24e 0x2>; -+ bits = <3 6>; -+ }; -+ -+ tsens_s2_p2: s2-p2@24f { -+ reg = <0x24f 0x1>; -+ bits = <1 6>; -+ }; -+ -+ tsens_s3_p1: s3-p1@24f { -+ reg = <0x24f 0x2>; -+ bits = <7 6>; -+ }; -+ -+ tsens_s3_p2: s3-p2@250 { -+ reg = <0x250 0x2>; -+ bits = <5 6>; -+ }; -+ -+ tsens_s4_p1: s4-p1@251 { -+ reg = <0x251 0x2>; -+ bits = <3 6>; -+ }; -+ -+ tsens_s4_p2: s4-p2@254 { -+ reg = <0x254 0x1>; -+ bits = <0 6>; -+ }; -+ }; -+ -+ tsens: thermal-sensor@4a9000 { -+ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; -+ reg = <0x004a9000 0x1000>, -+ <0x004a8000 0x1000>; -+ -+ nvmem-cells = <&tsens_mode>, -+ <&tsens_base1>, -+ <&tsens_base2>, -+ <&tsens_s0_p1>, -+ <&tsens_s0_p2>, -+ <&tsens_s1_p1>, -+ <&tsens_s1_p2>, -+ <&tsens_s2_p1>, -+ <&tsens_s2_p2>, -+ <&tsens_s3_p1>, -+ <&tsens_s3_p2>, -+ <&tsens_s4_p1>, -+ <&tsens_s4_p2>; -+ -+ nvmem-cell-names = "mode", -+ "base1", -+ "base2", -+ "s0_p1", -+ "s0_p2", -+ "s1_p1", -+ "s1_p2", -+ "s2_p1", -+ "s2_p2", -+ "s3_p1", -+ "s3_p2", -+ "s4_p1", -+ "s4_p2"; -+ -+ interrupts = ; -+ interrupt-names = "uplow"; -+ #qcom,sensors = <5>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-tlmm"; - reg = <0x01000000 0x300000>; -@@ -630,6 +744,70 @@ - }; - }; - }; -+ -+ thermal-zones { -+ cpu-thermal { -+ thermal-sensors = <&tsens 2>; -+ -+ trips { -+ cpu-critical { -+ temperature = <120000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ -+ cpu_alert: cpu-passive { -+ temperature = <100000>; -+ hysteresis = <1000>; -+ type = "passive"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gephy-thermal { -+ thermal-sensors = <&tsens 4>; -+ -+ trips { -+ gephy-critical { -+ temperature = <120000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ top-glue-thermal { -+ thermal-sensors = <&tsens 3>; -+ -+ trips { -+ top-glue-critical { -+ temperature = <120000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ ubi32-thermal { -+ thermal-sensors = <&tsens 1>; -+ -+ trips { -+ ubi32-critical { -+ temperature = <120000>; -+ hysteresis = <1000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; - - timer { - compatible = "arm,armv8-timer"; diff --git a/target/linux/qualcommax/patches-6.18/0056-v6.17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch b/target/linux/qualcommax/patches-6.18/0056-v6.17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch deleted file mode 100644 index 41399e419d3..00000000000 --- a/target/linux/qualcommax/patches-6.18/0056-v6.17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch +++ /dev/null @@ -1,33 +0,0 @@ -From f6a4a55ae5d99f865e106916a9295548e381de47 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 30 Jun 2025 16:35:00 +0400 -Subject: clk: qcom: gcc-ipq5018: fix GE PHY reset - -The MISC reset is supposed to trigger a resets across the MDC, DSP, and -RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask -of the reset definition accordingly in the GCC as per the downstream -driver. - -Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932 - -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/gcc-ipq5018.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -(limited to 'drivers/clk/qcom/gcc-ipq5018.c') - ---- a/drivers/clk/qcom/gcc-ipq5018.c -+++ b/drivers/clk/qcom/gcc-ipq5018.c -@@ -3661,7 +3661,7 @@ static const struct qcom_reset_map gcc_i - [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, - [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, - [GCC_WCSSAON_RESET] = { 0x59010, 0}, -- [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, -+ [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) }, - }; - - static const struct of_device_id gcc_ipq5018_match_table[] = { diff --git a/target/linux/qualcommax/patches-6.18/0057-v6.17-net-phy-qcom-at803x-Add-Qualcomm-IPQ5018-Internal-PHY-support.patch b/target/linux/qualcommax/patches-6.18/0057-v6.17-net-phy-qcom-at803x-Add-Qualcomm-IPQ5018-Internal-PHY-support.patch deleted file mode 100644 index 006f0b35f5e..00000000000 --- a/target/linux/qualcommax/patches-6.18/0057-v6.17-net-phy-qcom-at803x-Add-Qualcomm-IPQ5018-Internal-PHY-support.patch +++ /dev/null @@ -1,243 +0,0 @@ -From d46502279a11b48ede1d8bf65a229c8231bf0602 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Fri, 13 Jun 2025 05:55:08 +0400 -Subject: net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support - -The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which -provides an MDI interface directly to an RJ45 connector or an external -switch over a PHY to PHY link. - -The PHY supports 10BASE-T/100BASE-TX/1000BASE-T link modes in SGMII -interface mode, CDT, auto-negotiation and 802.3az EEE. - -Let's add support for this PHY in the at803x driver as it falls within -the Qualcomm Atheros OUI. - -Reviewed-by: Andrew Lunn -Signed-off-by: George Moussalem -Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-2-9af06e34ea6b@outlook.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/phy/qcom/at803x.c | 167 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 167 insertions(+) - -(limited to 'drivers/net/phy/qcom/at803x.c') - ---- a/drivers/net/phy/qcom/at803x.c -+++ b/drivers/net/phy/qcom/at803x.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -93,6 +94,8 @@ - #define ATH8035_PHY_ID 0x004dd072 - #define AT8030_PHY_ID_MASK 0xffffffef - -+#define IPQ5018_PHY_ID 0x004dd0c0 -+ - #define QCA9561_PHY_ID 0x004dd042 - - #define AT803X_PAGE_FIBER 0 -@@ -105,6 +108,48 @@ - /* disable hibernation mode */ - #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) - -+#define IPQ5018_PHY_FIFO_CONTROL 0x19 -+#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) -+ -+#define IPQ5018_PHY_DEBUG_EDAC 0x4380 -+#define IPQ5018_PHY_MMD1_MDAC 0x8100 -+#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8) -+ -+/* MDAC and EDAC values for short cable length */ -+#define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10 -+#define IPQ5018_PHY_MMD1_MDAC_VAL 0x10 -+ -+#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 -+#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 -+#define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008 -+#define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f -+ -+#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 -+#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 -+#define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880 -+#define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060 -+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060 -+#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0 -+ -+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 -+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4) -+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 -+#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 -+ - MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); - MODULE_AUTHOR("Matus Ujhelyi"); - MODULE_LICENSE("GPL"); -@@ -130,6 +175,11 @@ struct at803x_context { - u16 led_control; - }; - -+struct ipq5018_priv { -+ struct reset_control *rst; -+ bool set_short_cable_dac; -+}; -+ - static int at803x_write_page(struct phy_device *phydev, int page) - { - int mask; -@@ -960,6 +1010,109 @@ static int at8035_probe(struct phy_devic - return at8035_parse_dt(phydev); - } - -+static int ipq5018_cable_test_start(struct phy_device *phydev) -+{ -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13, -+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, -+ IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL); -+ -+ /* we do all the (time consuming) work later */ -+ return 0; -+} -+ -+static int ipq5018_config_init(struct phy_device *phydev) -+{ -+ struct ipq5018_priv *priv = phydev->priv; -+ u16 val; -+ -+ /* -+ * set LDO efuse: first temporarily store ANA_DAC_FILTER value from -+ * debug register as it will be reset once the ANA_LDO_EFUSE register -+ * is written to -+ */ -+ val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); -+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, -+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, -+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); -+ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); -+ -+ /* set 8023AZ EEE TX and RX timer values */ -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER, -+ IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER, -+ IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL); -+ -+ /* set MSE threshold values */ -+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, -+ IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); -+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, -+ IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); -+ -+ /* PHY DAC values are optional and only set in a PHY to PHY link architecture */ -+ if (priv->set_short_cable_dac) { -+ /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */ -+ phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, -+ IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL); -+ -+ /* setting EDAC (Error-detection and Correction) in debug register */ -+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, -+ IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL); -+ } -+ -+ return 0; -+} -+ -+static void ipq5018_link_change_notify(struct phy_device *phydev) -+{ -+ /* -+ * Reset the FIFO buffer upon link disconnects to clear any residual data -+ * which may cause issues with the FIFO which it cannot recover from. -+ */ -+ mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, -+ IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET, -+ phydev->link ? IPQ5018_PHY_FIFO_RESET : 0); -+} -+ -+static int ipq5018_probe(struct phy_device *phydev) -+{ -+ struct device *dev = &phydev->mdio.dev; -+ struct ipq5018_priv *priv; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->set_short_cable_dac = of_property_read_bool(dev->of_node, -+ "qcom,dac-preset-short-cable"); -+ -+ priv->rst = devm_reset_control_array_get_exclusive(dev); -+ if (IS_ERR(priv->rst)) -+ return dev_err_probe(dev, PTR_ERR(priv->rst), -+ "failed to acquire reset\n"); -+ -+ ret = reset_control_reset(priv->rst); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to reset\n"); -+ -+ phydev->priv = priv; -+ -+ return 0; -+} -+ - static struct phy_driver at803x_driver[] = { - { - /* Qualcomm Atheros AR8035 */ -@@ -1052,6 +1205,19 @@ static struct phy_driver at803x_driver[] - .soft_reset = genphy_soft_reset, - .config_aneg = at803x_config_aneg, - }, { -+ PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), -+ .name = "Qualcomm Atheros IPQ5018 internal PHY", -+ .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, -+ .probe = ipq5018_probe, -+ .config_init = ipq5018_config_init, -+ .link_change_notify = ipq5018_link_change_notify, -+ .read_status = at803x_read_status, -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .cable_test_start = ipq5018_cable_test_start, -+ .cable_test_get_status = qca808x_cable_test_get_status, -+ .soft_reset = genphy_soft_reset, -+}, { - /* Qualcomm Atheros QCA9561 */ - PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), - .name = "Qualcomm Atheros QCA9561 built-in PHY", -@@ -1077,6 +1243,7 @@ static const struct mdio_device_id __may - { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, - { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, - { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, - { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, - { } - }; diff --git a/target/linux/qualcommax/patches-6.18/0058-v6.18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch b/target/linux/qualcommax/patches-6.18/0058-v6.18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch deleted file mode 100644 index 59f6bc2cc47..00000000000 --- a/target/linux/qualcommax/patches-6.18/0058-v6.18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 1e2261a669a9596ba435c6fe524e026bac0f0e2f Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 30 Jun 2025 16:35:01 +0400 -Subject: arm64: dts: qcom: ipq5018: Add MDIO buses - -IPQ5018 contains two mdio buses of which one bus is used to control the -SoC's internal GE PHY, while the other bus is connected to external PHYs -or switches. - -There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's -simply add the mdio nodes for them. - -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -185,6 +185,30 @@ - status = "disabled"; - }; - -+ mdio0: mdio@88000 { -+ compatible = "qcom,ipq5018-mdio"; -+ reg = <0x00088000 0x64>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clocks = <&gcc GCC_MDIO0_AHB_CLK>; -+ clock-names = "gcc_mdio_ahb_clk"; -+ -+ status = "disabled"; -+ }; -+ -+ mdio1: mdio@90000 { -+ compatible = "qcom,ipq5018-mdio"; -+ reg = <0x00090000 0x64>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clocks = <&gcc GCC_MDIO1_AHB_CLK>; -+ clock-names = "gcc_mdio_ahb_clk"; -+ -+ status = "disabled"; -+ }; -+ - qfprom: qfprom@a0000 { - compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; - reg = <0x000a0000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.18/0059-v6.18-arm64-dts-qcom-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch b/target/linux/qualcommax/patches-6.18/0059-v6.18-arm64-dts-qcom-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch deleted file mode 100644 index e8d96b8e0a9..00000000000 --- a/target/linux/qualcommax/patches-6.18/0059-v6.18-arm64-dts-qcom-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch +++ /dev/null @@ -1,82 +0,0 @@ -From f5f2b835e316df29b89e28ed7e467df473932e8d Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 30 Jun 2025 16:35:02 +0400 -Subject: arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus - -The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. -As such, let's add the GE PHY node to the SoC dtsi. - -The LDO controller found in the SoC must be enabled to provide constant -low voltages to the PHY. The mdio-ipq4019 driver already has support -for this, so adding the appropriate TCSR register offset. - -In addition, the GE PHY outputs both the RX and TX clocks to the GCC -which gate controls them and routes them back to the PHY itself. -So let's create two DT fixed clocks and register them in the GCC node. - -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++--- - 1 file changed, 23 insertions(+), 3 deletions(-) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -17,6 +17,18 @@ - #size-cells = <2>; - - clocks { -+ gephy_rx_clk: gephy-rx-clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ #clock-cells = <0>; -+ }; -+ -+ gephy_tx_clk: gephy-tx-clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ #clock-cells = <0>; -+ }; -+ - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -187,7 +199,8 @@ - - mdio0: mdio@88000 { - compatible = "qcom,ipq5018-mdio"; -- reg = <0x00088000 0x64>; -+ reg = <0x00088000 0x64>, -+ <0x019475c4 0x4>; - #address-cells = <1>; - #size-cells = <0>; - -@@ -195,6 +208,13 @@ - clock-names = "gcc_mdio_ahb_clk"; - - status = "disabled"; -+ -+ ge_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-id004d.d0c0"; -+ reg = <7>; -+ -+ resets = <&gcc GCC_GEPHY_MISC_ARES>; -+ }; - }; - - mdio1: mdio@90000 { -@@ -346,8 +366,8 @@ - <&pcie0_phy>, - <&pcie1_phy>, - <0>, -- <0>, -- <0>, -+ <&gephy_rx_clk>, -+ <&gephy_tx_clk>, - <0>, - <0>; - #clock-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.18/0060-v6.18-arm64-dts-qcom-ipq5018-Add-SPI-nand-support.patch b/target/linux/qualcommax/patches-6.18/0060-v6.18-arm64-dts-qcom-ipq5018-Add-SPI-nand-support.patch deleted file mode 100644 index f9b47cdbddd..00000000000 --- a/target/linux/qualcommax/patches-6.18/0060-v6.18-arm64-dts-qcom-ipq5018-Add-SPI-nand-support.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 8d2a8e8dc448f218b36b3b9f3790c9c0dfaa2b74 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Thu, 1 May 2025 13:20:52 +0400 -Subject: arm64: dts: qcom: ipq5018: Add SPI nand support - -Add QPIC SPI NAND support for IPQ5018 SoC. - -Signed-off-by: George Moussalem -Reviewed-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250501-ipq5018-spi-qpic-snand-v1-2-31e01fbb606f@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 38 +++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -436,6 +436,44 @@ - status = "disabled"; - }; - -+ qpic_bam: dma-controller@7984000 { -+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; -+ reg = <0x07984000 0x1c000>; -+ -+ interrupts = ; -+ -+ clocks = <&gcc GCC_QPIC_AHB_CLK>; -+ clock-names = "bam_clk"; -+ -+ #dma-cells = <1>; -+ qcom,ee = <0>; -+ -+ status = "disabled"; -+ }; -+ -+ qpic_nand: spi@79b0000 { -+ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; -+ reg = <0x079b0000 0x10000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clocks = <&gcc GCC_QPIC_CLK>, -+ <&gcc GCC_QPIC_AHB_CLK>, -+ <&gcc GCC_QPIC_IO_MACRO_CLK>; -+ clock-names = "core", -+ "aon", -+ "iom"; -+ -+ dmas = <&qpic_bam 0>, -+ <&qpic_bam 1>, -+ <&qpic_bam 2>; -+ dma-names = "tx", -+ "rx", -+ "cmd"; -+ -+ status = "disabled"; -+ }; -+ - usb: usb@8af8800 { - compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; - reg = <0x08af8800 0x400>; diff --git a/target/linux/qualcommax/patches-6.18/0061-v6.18-arm64-dts-qcom-ipq5018-add-PRNG-node.patch b/target/linux/qualcommax/patches-6.18/0061-v6.18-arm64-dts-qcom-ipq5018-add-PRNG-node.patch deleted file mode 100644 index bdb15ff9384..00000000000 --- a/target/linux/qualcommax/patches-6.18/0061-v6.18-arm64-dts-qcom-ipq5018-add-PRNG-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From bf258fdaa2bcbafa04bf1ad646e8ed42e13033cb Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 21 Jul 2025 10:30:46 +0400 -Subject: arm64: dts: qcom: ipq5018: add PRNG node - -PRNG inside of IPQ5018 is already supported, so let's add the node for it. - -Signed-off-by: George Moussalem -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20250721-ipq5018-prng-v1-1-474310e0575d@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -301,6 +301,14 @@ - }; - }; - -+ prng: rng@e3000 { -+ compatible = "qcom,prng-ee"; -+ reg = <0x000e3000 0x1000>; -+ clocks = <&gcc GCC_PRNG_AHB_CLK>; -+ clock-names = "core"; -+ status = "disabled"; -+ }; -+ - tsens: thermal-sensor@4a9000 { - compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, diff --git a/target/linux/qualcommax/patches-6.18/0062-v6.18-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch b/target/linux/qualcommax/patches-6.18/0062-v6.18-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch deleted file mode 100644 index 808f8ea570f..00000000000 --- a/target/linux/qualcommax/patches-6.18/0062-v6.18-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch +++ /dev/null @@ -1,58 +0,0 @@ -From ed5789ba7c2ce548f01ebbdbd7488dd9cccc4513 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 21 Jul 2025 10:23:15 +0400 -Subject: arm64: dts: qcom: ipq5018: Add crypto nodes - -IPQ5018 uses Qualcomm QCE crypto engine v5.1 which is already supported. -So let's add the dts nodes for its DMA v1.7.4 and QCE itself. - -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20250721-ipq5018-crypto-v3-1-b9cd9b0ef147@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -348,6 +348,36 @@ - #thermal-sensor-cells = <1>; - }; - -+ cryptobam: dma-controller@704000 { -+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; -+ reg = <0x00704000 0x20000>; -+ interrupts = ; -+ -+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>; -+ clock-names = "bam_clk"; -+ -+ #dma-cells = <1>; -+ qcom,ee = <1>; -+ qcom,controlled-remotely; -+ }; -+ -+ crypto: crypto@73a000 { -+ compatible = "qcom,crypto-v5.1"; -+ reg = <0x0073a000 0x6000>; -+ -+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>, -+ <&gcc GCC_CRYPTO_AXI_CLK>, -+ <&gcc GCC_CRYPTO_CLK>; -+ clock-names = "iface", -+ "bus", -+ "core"; -+ -+ dmas = <&cryptobam 2>, -+ <&cryptobam 3>; -+ dma-names = "rx", -+ "tx"; -+ }; -+ - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-tlmm"; - reg = <0x01000000 0x300000>; diff --git a/target/linux/qualcommax/patches-6.18/0063-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller.patch b/target/linux/qualcommax/patches-6.18/0063-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller.patch deleted file mode 100644 index 01312eb5d11..00000000000 --- a/target/linux/qualcommax/patches-6.18/0063-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller.patch +++ /dev/null @@ -1,132 +0,0 @@ -From c0f1cbf795095c21b92a46fa1dc47a7b787ce538 Mon Sep 17 00:00:00 2001 -From: Luo Jie -Date: Fri, 3 Jan 2025 15:31:34 +0800 -Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL clock controller for - IPQ SoC - -The CMN PLL controller provides clocks to networking hardware blocks -and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the -on-chip Wi-Fi, and produces output clocks at fixed rates. These output -rates are predetermined, and are unrelated to the input clock rate. -The primary purpose of CMN PLL is to supply clocks to the networking -hardware such as PPE (packet process engine), PCS and the externally -connected switch or PHY device. The CMN PLL block also outputs fixed -rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep -clock supplied to GCC. - -Signed-off-by: Luo Jie -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com -Signed-off-by: Bjorn Andersson ---- - .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 77 +++++++++++++++++++ - include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++++++ - 2 files changed, 99 insertions(+) - create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml - create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml -@@ -0,0 +1,77 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Qualcomm CMN PLL Clock Controller on IPQ SoC -+ -+maintainers: -+ - Bjorn Andersson -+ - Luo Jie -+ -+description: -+ The CMN (or common) PLL clock controller expects a reference -+ input clock. This reference clock is from the on-board Wi-Fi. -+ The CMN PLL supplies a number of fixed rate output clocks to -+ the devices providing networking functions and to GCC. These -+ networking hardware include PPE (packet process engine), PCS -+ and the externally connected switch or PHY devices. The CMN -+ PLL block also outputs fixed rate clocks to GCC. The PLL's -+ primary function is to enable fixed rate output clocks for -+ networking hardware functions used with the IPQ SoC. -+ -+properties: -+ compatible: -+ enum: -+ - qcom,ipq9574-cmn-pll -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: The reference clock. The supported clock rates include -+ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. -+ - description: The AHB clock -+ - description: The SYS clock -+ description: -+ The reference clock is the source clock of CMN PLL, which is from the -+ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL -+ clock registers. -+ -+ clock-names: -+ items: -+ - const: ref -+ - const: ahb -+ - const: sys -+ -+ "#clock-cells": -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - "#clock-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ cmn_pll: clock-controller@9b000 { -+ compatible = "qcom,ipq9574-cmn-pll"; -+ reg = <0x0009b000 0x800>; -+ clocks = <&cmn_pll_ref_clk>, -+ <&gcc GCC_CMN_12GPLL_AHB_CLK>, -+ <&gcc GCC_CMN_12GPLL_SYS_CLK>; -+ clock-names = "ref", "ahb", "sys"; -+ #clock-cells = <1>; -+ assigned-clocks = <&cmn_pll CMN_PLL_CLK>; -+ assigned-clock-rates-u64 = /bits/ 64 <12000000000>; -+ }; -+... ---- /dev/null -+++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H -+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H -+ -+/* CMN PLL core clock. */ -+#define CMN_PLL_CLK 0 -+ -+/* The output clocks from CMN PLL of IPQ9574. */ -+#define XO_24MHZ_CLK 1 -+#define SLEEP_32KHZ_CLK 2 -+#define PCS_31P25MHZ_CLK 3 -+#define NSS_1200MHZ_CLK 4 -+#define PPE_353MHZ_CLK 5 -+#define ETH0_50MHZ_CLK 6 -+#define ETH1_50MHZ_CLK 7 -+#define ETH2_50MHZ_CLK 8 -+#define ETH_25MHZ_CLK 9 -+#endif diff --git a/target/linux/qualcommax/patches-6.18/0064-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch b/target/linux/qualcommax/patches-6.18/0064-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch deleted file mode 100644 index 350e8eeabbd..00000000000 --- a/target/linux/qualcommax/patches-6.18/0064-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch +++ /dev/null @@ -1,500 +0,0 @@ -From f81715a4c87c3b75ca2640bb61b6c66506061a64 Mon Sep 17 00:00:00 2001 -From: Luo Jie -Date: Fri, 3 Jan 2025 15:31:35 +0800 -Subject: [PATCH] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC - -The CMN PLL clock controller supplies clocks to the hardware -blocks that together make up the Ethernet function on Qualcomm -IPQ SoCs and to GCC. The driver is initially supported for -IPQ9574 SoC. - -The CMN PLL clock controller expects a reference input clock -from the on-board Wi-Fi block acting as clock source. The input -reference clock needs to be configured to one of the supported -clock rates. - -The controller supplies a number of fixed-rate output clocks. -For the IPQ9574, there is one output clock of 353 MHZ to PPE -(Packet Process Engine) hardware block, three 50 MHZ output -clocks and an additional 25 MHZ output clock supplied to the -connected Ethernet devices. The PLL also supplies a 24 MHZ -clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 -MHZ clock to PCS. - -Signed-off-by: Luo Jie -Acked-by: Konrad Dybcio -Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/Kconfig | 9 + - drivers/clk/qcom/Makefile | 1 + - drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++++++++++++++ - 3 files changed, 445 insertions(+) - create mode 100644 drivers/clk/qcom/ipq-cmn-pll.c - ---- a/drivers/clk/qcom/Kconfig -+++ b/drivers/clk/qcom/Kconfig -@@ -190,6 +190,15 @@ config IPQ_APSS_6018 - Say Y if you want to support CPU frequency scaling on - ipq based devices. - -+config IPQ_CMN_PLL -+ tristate "IPQ CMN PLL Clock Controller" -+ help -+ Support for CMN PLL clock controller on IPQ platform. The -+ CMN PLL consumes the AHB/SYS clocks from GCC and supplies -+ the output clocks to the networking hardware and GCC blocks. -+ Say Y or M if you want to support CMN PLL clock on the IPQ -+ based devices. -+ - config IPQ_GCC_4019 - tristate "IPQ4019 Global Clock Controller" - help ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcs - obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o - obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o - obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o -+obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o - obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o - obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o - obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o ---- /dev/null -+++ b/drivers/clk/qcom/ipq-cmn-pll.c -@@ -0,0 +1,435 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ -+ -+/* -+ * CMN PLL block expects the reference clock from on-board Wi-Fi block, -+ * and supplies fixed rate clocks as output to the networking hardware -+ * blocks and to GCC. The networking related blocks include PPE (packet -+ * process engine), the externally connected PHY or switch devices, and -+ * the PCS. -+ * -+ * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock -+ * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), -+ * and one clock with 353 MHZ to PPE. The other fixed rate output clocks -+ * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS -+ * with 31.25 MHZ. -+ * -+ * +---------+ -+ * | GCC | -+ * +--+---+--+ -+ * AHB CLK| |SYS CLK -+ * V V -+ * +-------+---+------+ -+ * | +-------------> eth0-50mhz -+ * REF CLK | IPQ9574 | -+ * -------->+ +-------------> eth1-50mhz -+ * | CMN PLL block | -+ * | +-------------> eth2-50mhz -+ * | | -+ * +----+----+----+---+-------------> eth-25mhz -+ * | | | -+ * V V V -+ * GCC PCS NSS/PPE -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define CMN_PLL_REFCLK_SRC_SELECTION 0x28 -+#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) -+ -+#define CMN_PLL_LOCKED 0x64 -+#define CMN_PLL_CLKS_LOCKED BIT(8) -+ -+#define CMN_PLL_POWER_ON_AND_RESET 0x780 -+#define CMN_ANA_EN_SW_RSTN BIT(6) -+ -+#define CMN_PLL_REFCLK_CONFIG 0x784 -+#define CMN_PLL_REFCLK_EXTERNAL BIT(9) -+#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) -+#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) -+ -+#define CMN_PLL_CTRL 0x78c -+#define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) -+ -+#define CMN_PLL_DIVIDER_CTRL 0x794 -+#define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) -+ -+/** -+ * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information -+ * @id: Clock specifier to be supplied -+ * @name: Clock name to be registered -+ * @rate: Clock rate -+ */ -+struct cmn_pll_fixed_output_clk { -+ unsigned int id; -+ const char *name; -+ unsigned long rate; -+}; -+ -+/** -+ * struct clk_cmn_pll - CMN PLL hardware specific data -+ * @regmap: hardware regmap. -+ * @hw: handle between common and hardware-specific interfaces -+ */ -+struct clk_cmn_pll { -+ struct regmap *regmap; -+ struct clk_hw hw; -+}; -+ -+#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .rate = _rate, \ -+} -+ -+#define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) -+ -+static const struct regmap_config ipq_cmn_pll_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = 0x7fc, -+ .fast_io = true, -+}; -+ -+static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { -+ CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), -+ CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), -+ CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), -+ CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), -+ CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), -+ CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), -+}; -+ -+/* -+ * CMN PLL has the single parent clock, which supports the several -+ * possible parent clock rates, each parent clock rate is reflected -+ * by the specific reference index value in the hardware. -+ */ -+static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) -+{ -+ int index = -EINVAL; -+ -+ switch (parent_rate) { -+ case 25000000: -+ index = 3; -+ break; -+ case 31250000: -+ index = 4; -+ break; -+ case 40000000: -+ index = 6; -+ break; -+ case 48000000: -+ case 96000000: -+ /* -+ * Parent clock rate 48 MHZ and 96 MHZ take the same value -+ * of reference clock index. 96 MHZ needs the source clock -+ * divider to be programmed as 2. -+ */ -+ index = 7; -+ break; -+ case 50000000: -+ index = 8; -+ break; -+ default: -+ break; -+ } -+ -+ return index; -+} -+ -+static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); -+ u32 val, factor; -+ -+ /* -+ * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted -+ * by HW according to the parent clock rate. -+ */ -+ regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); -+ factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); -+ -+ return parent_rate * 2 * factor; -+} -+ -+static int clk_cmn_pll_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ int ret; -+ -+ /* Validate the rate of the single parent clock. */ -+ ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); -+ -+ return ret < 0 ? ret : 0; -+} -+ -+/* -+ * This function is used to initialize the CMN PLL to enable the fixed -+ * rate output clocks. It is expected to be configured once. -+ */ -+static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); -+ int ret, index; -+ u32 val; -+ -+ /* -+ * Configure the reference input clock selection as per the given -+ * parent clock. The output clock rates are always of fixed value. -+ */ -+ index = ipq_cmn_pll_find_freq_index(parent_rate); -+ if (index < 0) -+ return index; -+ -+ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, -+ CMN_PLL_REFCLK_INDEX, -+ FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); -+ if (ret) -+ return ret; -+ -+ /* -+ * Update the source clock rate selection and source clock -+ * divider as 2 when the parent clock rate is 96 MHZ. -+ */ -+ if (parent_rate == 96000000) { -+ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, -+ CMN_PLL_REFCLK_DIV, -+ FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); -+ if (ret) -+ return ret; -+ -+ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, -+ CMN_PLL_REFCLK_SRC_DIV, -+ FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); -+ if (ret) -+ return ret; -+ } -+ -+ /* Enable PLL locked detect. */ -+ ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, -+ CMN_PLL_CTRL_LOCK_DETECT_EN); -+ if (ret) -+ return ret; -+ -+ /* -+ * Reset the CMN PLL block to ensure the updated configurations -+ * take effect. -+ */ -+ ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, -+ CMN_ANA_EN_SW_RSTN); -+ if (ret) -+ return ret; -+ -+ usleep_range(1000, 1200); -+ ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, -+ CMN_ANA_EN_SW_RSTN); -+ if (ret) -+ return ret; -+ -+ /* Stability check of CMN PLL output clocks. */ -+ return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, -+ (val & CMN_PLL_CLKS_LOCKED), -+ 100, 100 * USEC_PER_MSEC); -+} -+ -+static const struct clk_ops clk_cmn_pll_ops = { -+ .recalc_rate = clk_cmn_pll_recalc_rate, -+ .determine_rate = clk_cmn_pll_determine_rate, -+ .set_rate = clk_cmn_pll_set_rate, -+}; -+ -+static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) -+{ -+ struct clk_parent_data pdata = { .index = 0 }; -+ struct device *dev = &pdev->dev; -+ struct clk_init_data init = {}; -+ struct clk_cmn_pll *cmn_pll; -+ struct regmap *regmap; -+ void __iomem *base; -+ int ret; -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return ERR_CAST(base); -+ -+ regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); -+ if (IS_ERR(regmap)) -+ return ERR_CAST(regmap); -+ -+ cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); -+ if (!cmn_pll) -+ return ERR_PTR(-ENOMEM); -+ -+ init.name = "cmn_pll"; -+ init.parent_data = &pdata; -+ init.num_parents = 1; -+ init.ops = &clk_cmn_pll_ops; -+ -+ cmn_pll->hw.init = &init; -+ cmn_pll->regmap = regmap; -+ -+ ret = devm_clk_hw_register(dev, &cmn_pll->hw); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ return &cmn_pll->hw; -+} -+ -+static int ipq_cmn_pll_register_clks(struct platform_device *pdev) -+{ -+ const struct cmn_pll_fixed_output_clk *fixed_clk; -+ struct clk_hw_onecell_data *hw_data; -+ struct device *dev = &pdev->dev; -+ struct clk_hw *cmn_pll_hw; -+ unsigned int num_clks; -+ struct clk_hw *hw; -+ int ret, i; -+ -+ fixed_clk = ipq9574_output_clks; -+ num_clks = ARRAY_SIZE(ipq9574_output_clks); -+ -+ hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), -+ GFP_KERNEL); -+ if (!hw_data) -+ return -ENOMEM; -+ -+ /* -+ * Register the CMN PLL clock, which is the parent clock of -+ * the fixed rate output clocks. -+ */ -+ cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); -+ if (IS_ERR(cmn_pll_hw)) -+ return PTR_ERR(cmn_pll_hw); -+ -+ /* Register the fixed rate output clocks. */ -+ for (i = 0; i < num_clks; i++) { -+ hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, -+ cmn_pll_hw, 0, -+ fixed_clk[i].rate); -+ if (IS_ERR(hw)) { -+ ret = PTR_ERR(hw); -+ goto unregister_fixed_clk; -+ } -+ -+ hw_data->hws[fixed_clk[i].id] = hw; -+ } -+ -+ /* -+ * Provide the CMN PLL clock. The clock rate of CMN PLL -+ * is configured to 12 GHZ by DT property assigned-clock-rates-u64. -+ */ -+ hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; -+ hw_data->num = num_clks + 1; -+ -+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); -+ if (ret) -+ goto unregister_fixed_clk; -+ -+ platform_set_drvdata(pdev, hw_data); -+ -+ return 0; -+ -+unregister_fixed_clk: -+ while (i > 0) -+ clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); -+ -+ return ret; -+} -+ -+static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ int ret; -+ -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ return ret; -+ -+ ret = devm_pm_clk_create(dev); -+ if (ret) -+ return ret; -+ -+ /* -+ * To access the CMN PLL registers, the GCC AHB & SYS clocks -+ * of CMN PLL block need to be enabled. -+ */ -+ ret = pm_clk_add(dev, "ahb"); -+ if (ret) -+ return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); -+ -+ ret = pm_clk_add(dev, "sys"); -+ if (ret) -+ return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); -+ -+ ret = pm_runtime_resume_and_get(dev); -+ if (ret) -+ return ret; -+ -+ /* Register CMN PLL clock and fixed rate output clocks. */ -+ ret = ipq_cmn_pll_register_clks(pdev); -+ pm_runtime_put(dev); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "Fail to register CMN PLL clocks\n"); -+ -+ return 0; -+} -+ -+static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev); -+ int i; -+ -+ /* -+ * The clock with index CMN_PLL_CLK is unregistered by -+ * device management. -+ */ -+ for (i = 0; i < hw_data->num; i++) { -+ if (i != CMN_PLL_CLK) -+ clk_hw_unregister(hw_data->hws[i]); -+ } -+} -+ -+static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { -+ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) -+}; -+ -+static const struct of_device_id ipq_cmn_pll_clk_ids[] = { -+ { .compatible = "qcom,ipq9574-cmn-pll", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); -+ -+static struct platform_driver ipq_cmn_pll_clk_driver = { -+ .probe = ipq_cmn_pll_clk_probe, -+ .remove = ipq_cmn_pll_clk_remove, -+ .driver = { -+ .name = "ipq_cmn_pll", -+ .of_match_table = ipq_cmn_pll_clk_ids, -+ .pm = &ipq_cmn_pll_pm_ops, -+ }, -+}; -+module_platform_driver(ipq_cmn_pll_clk_driver); -+ -+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommax/patches-6.18/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch b/target/linux/qualcommax/patches-6.18/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch deleted file mode 100644 index b3209630368..00000000000 --- a/target/linux/qualcommax/patches-6.18/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 0c25ae62f5dc6a438b563536b5fe7fb6da3612b8 Mon Sep 17 00:00:00 2001 -From: Luo Jie -Date: Tue, 10 Jun 2025 18:35:18 +0800 -Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC - -The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference -input clock. The output clocks are the same as IPQ9574 SoC, except -for the clock rate of output clocks to PPE and NSS. - -Also, add the new header file to export the CMN PLL output clock -specifiers for IPQ5424 SoC. - -Acked-by: Rob Herring (Arm) -Signed-off-by: Luo Jie -Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com -Signed-off-by: Bjorn Andersson ---- - .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + - .../dt-bindings/clock/qcom,ipq5424-cmn-pll.h | 22 +++++++++++++++++++ - 2 files changed, 23 insertions(+) - create mode 100644 include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h - ---- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml -@@ -24,6 +24,7 @@ description: - properties: - compatible: - enum: -+ - qcom,ipq5424-cmn-pll - - qcom,ipq9574-cmn-pll - - reg: ---- /dev/null -+++ b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H -+#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H -+ -+/* CMN PLL core clock. */ -+#define IPQ5424_CMN_PLL_CLK 0 -+ -+/* The output clocks from CMN PLL of IPQ5424. */ -+#define IPQ5424_XO_24MHZ_CLK 1 -+#define IPQ5424_SLEEP_32KHZ_CLK 2 -+#define IPQ5424_PCS_31P25MHZ_CLK 3 -+#define IPQ5424_NSS_300MHZ_CLK 4 -+#define IPQ5424_PPE_375MHZ_CLK 5 -+#define IPQ5424_ETH0_50MHZ_CLK 6 -+#define IPQ5424_ETH1_50MHZ_CLK 7 -+#define IPQ5424_ETH2_50MHZ_CLK 8 -+#define IPQ5424_ETH_25MHZ_CLK 9 -+#endif diff --git a/target/linux/qualcommax/patches-6.18/0066-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch b/target/linux/qualcommax/patches-6.18/0066-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch deleted file mode 100644 index d13e0b1fd55..00000000000 --- a/target/linux/qualcommax/patches-6.18/0066-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch +++ /dev/null @@ -1,104 +0,0 @@ -From a2afa4c33f0a7f7f70d54a1bc5110e326753f982 Mon Sep 17 00:00:00 2001 -From: Luo Jie -Date: Tue, 10 Jun 2025 18:35:19 +0800 -Subject: clk: qcom: cmnpll: Add IPQ5424 SoC support - -The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ -and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC, -and their rates are same as IPQ9574. - -Acked-by: Stephen Boyd -Signed-off-by: Luo Jie -Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-2-ceada8165645@quicinc.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/ipq-cmn-pll.c | 35 ++++++++++++++++++++++++++++++----- - 1 file changed, 30 insertions(+), 5 deletions(-) - -(limited to 'drivers/clk/qcom/ipq-cmn-pll.c') - ---- a/drivers/clk/qcom/ipq-cmn-pll.c -+++ b/drivers/clk/qcom/ipq-cmn-pll.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* -- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. -+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. - */ - - /* -@@ -16,6 +16,10 @@ - * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS - * with 31.25 MHZ. - * -+ * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, -+ * and an output clock to NSS (network subsystem) at 300 MHZ. The other output -+ * clocks from CMN PLL on IPQ5424 are the same as IPQ9574. -+ * - * +---------+ - * | GCC | - * +--+---+--+ -@@ -46,6 +50,7 @@ - #include - - #include -+#include - - #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 - #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) -@@ -115,6 +120,20 @@ static const struct cmn_pll_fixed_output - CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), -+ { /* Sentinel */ } -+}; -+ -+static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { -+ CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), -+ CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), -+ CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), -+ CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), -+ CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), -+ CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), -+ { /* Sentinel */ } - }; - - /* -@@ -297,7 +316,7 @@ static struct clk_hw *ipq_cmn_pll_clk_hw - - static int ipq_cmn_pll_register_clks(struct platform_device *pdev) - { -- const struct cmn_pll_fixed_output_clk *fixed_clk; -+ const struct cmn_pll_fixed_output_clk *p, *fixed_clk; - struct clk_hw_onecell_data *hw_data; - struct device *dev = &pdev->dev; - struct clk_hw *cmn_pll_hw; -@@ -305,8 +324,13 @@ static int ipq_cmn_pll_register_clks(str - struct clk_hw *hw; - int ret, i; - -- fixed_clk = ipq9574_output_clks; -- num_clks = ARRAY_SIZE(ipq9574_output_clks); -+ fixed_clk = device_get_match_data(dev); -+ if (!fixed_clk) -+ return -EINVAL; -+ -+ num_clks = 0; -+ for (p = fixed_clk; p->name; p++) -+ num_clks++; - - hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), - GFP_KERNEL); -@@ -415,7 +439,8 @@ static const struct dev_pm_ops ipq_cmn_p - }; - - static const struct of_device_id ipq_cmn_pll_clk_ids[] = { -- { .compatible = "qcom,ipq9574-cmn-pll", }, -+ { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, -+ { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, - { } - }; - MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); diff --git a/target/linux/qualcommax/patches-6.18/0067-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch b/target/linux/qualcommax/patches-6.18/0067-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch deleted file mode 100644 index e2e3f74fd46..00000000000 --- a/target/linux/qualcommax/patches-6.18/0067-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 314b903c30040632db7edd187cd33003b2aee512 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Fri, 16 May 2025 16:36:09 +0400 -Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC - -The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference -input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and -ethernet (50Mhz) clocks. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com -Signed-off-by: Bjorn Andersson ---- - .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + - include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++++++ - 2 files changed, 17 insertions(+) - create mode 100644 include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h - ---- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml -@@ -24,6 +24,7 @@ description: - properties: - compatible: - enum: -+ - qcom,ipq5018-cmn-pll - - qcom,ipq5424-cmn-pll - - qcom,ipq9574-cmn-pll - ---- /dev/null -+++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H -+#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H -+ -+/* CMN PLL core clock. */ -+#define IPQ5018_CMN_PLL_CLK 0 -+ -+/* The output clocks from CMN PLL of IPQ5018. */ -+#define IPQ5018_XO_24MHZ_CLK 1 -+#define IPQ5018_SLEEP_32KHZ_CLK 2 -+#define IPQ5018_ETH_50MHZ_CLK 3 -+#endif diff --git a/target/linux/qualcommax/patches-6.18/0068-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch b/target/linux/qualcommax/patches-6.18/0068-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch deleted file mode 100644 index d113c2d6c05..00000000000 --- a/target/linux/qualcommax/patches-6.18/0068-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 25d12630561d8d0906f1f5eceb055da3af67c8c9 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Fri, 16 May 2025 16:36:10 +0400 -Subject: clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support - -The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the -ethernet block. - -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-3-389a6b30e504@outlook.com -Signed-off-by: Bjorn Andersson ---- - drivers/clk/qcom/ipq-cmn-pll.c | 37 +++++++++++++++++++++++-------------- - 1 file changed, 23 insertions(+), 14 deletions(-) - -(limited to 'drivers/clk/qcom/ipq-cmn-pll.c') - ---- a/drivers/clk/qcom/ipq-cmn-pll.c -+++ b/drivers/clk/qcom/ipq-cmn-pll.c -@@ -50,6 +50,7 @@ - #include - - #include -+#include - #include - - #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 -@@ -110,16 +111,10 @@ static const struct regmap_config ipq_cm - .fast_io = true, - }; - --static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { -- CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), -- CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), -- CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), -- CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), -- CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), -- CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), -- CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), -- CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), -- CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), -+static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { -+ CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), -+ CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), -+ CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), - { /* Sentinel */ } - }; - -@@ -136,6 +131,19 @@ static const struct cmn_pll_fixed_output - { /* Sentinel */ } - }; - -+static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { -+ CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), -+ CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), -+ CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), -+ CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), -+ CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), -+ CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), -+ CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), -+ { /* Sentinel */ } -+}; -+ - /* - * CMN PLL has the single parent clock, which supports the several - * possible parent clock rates, each parent clock rate is reflected -@@ -399,11 +407,11 @@ static int ipq_cmn_pll_clk_probe(struct - */ - ret = pm_clk_add(dev, "ahb"); - if (ret) -- return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); -+ return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); - - ret = pm_clk_add(dev, "sys"); - if (ret) -- return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); -+ return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); - - ret = pm_runtime_resume_and_get(dev); - if (ret) -@@ -414,7 +422,7 @@ static int ipq_cmn_pll_clk_probe(struct - pm_runtime_put(dev); - if (ret) - return dev_err_probe(dev, ret, -- "Fail to register CMN PLL clocks\n"); -+ "Failed to register CMN PLL clocks\n"); - - return 0; - } -@@ -439,8 +447,9 @@ static const struct dev_pm_ops ipq_cmn_p - }; - - static const struct of_device_id ipq_cmn_pll_clk_ids[] = { -- { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, -+ { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, - { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, -+ { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, - { } - }; - MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); diff --git a/target/linux/qualcommax/patches-6.18/0069-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch b/target/linux/qualcommax/patches-6.18/0069-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch deleted file mode 100644 index 83d6714153d..00000000000 --- a/target/linux/qualcommax/patches-6.18/0069-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch +++ /dev/null @@ -1,89 +0,0 @@ -From c006b249c54441dd8a3a493c7c87158f441f8178 Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 21 Jul 2025 10:04:35 +0400 -Subject: arm64: dts: ipq5018: Add CMN PLL node - -Add CMN PLL node for enabling output clocks to the networking -hardware blocks on IPQ5018 devices. - -The reference clock of CMN PLL is routed from XO to the CMN PLL -through the internal WiFi block. -.XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. - -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++++++++-- - 1 file changed, 31 insertions(+), 2 deletions(-) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -2,12 +2,13 @@ - /* - * IPQ5018 SoC device tree source - * -- * Copyright (c) 2023 The Linux Foundation. All rights reserved. -+ * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. - */ - - #include --#include - #include -+#include -+#include - #include - #include - -@@ -29,6 +30,14 @@ - #clock-cells = <0>; - }; - -+ ref_96mhz_clk: ref-96mhz-clk { -+ compatible = "fixed-factor-clock"; -+ clocks = <&xo_clk>; -+ #clock-cells = <0>; -+ clock-div = <1>; -+ clock-mult = <2>; -+ }; -+ - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -38,6 +47,12 @@ - compatible = "fixed-clock"; - #clock-cells = <0>; - }; -+ -+ xo_clk: xo-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <48000000>; -+ }; - }; - - cpus { -@@ -229,6 +244,20 @@ - status = "disabled"; - }; - -+ cmn_pll: clock-controller@9b000 { -+ compatible = "qcom,ipq5018-cmn-pll"; -+ reg = <0x0009b000 0x800>; -+ clocks = <&ref_96mhz_clk>, -+ <&gcc GCC_CMN_BLK_AHB_CLK>, -+ <&gcc GCC_CMN_BLK_SYS_CLK>; -+ clock-names = "ref", -+ "ahb", -+ "sys"; -+ #clock-cells = <1>; -+ assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; -+ assigned-clock-rates-u64 = /bits/ 64 <9600000000>; -+ }; -+ - qfprom: qfprom@a0000 { - compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; - reg = <0x000a0000 0x1000>; diff --git a/target/linux/qualcommax/patches-6.18/0070-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch b/target/linux/qualcommax/patches-6.18/0070-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch deleted file mode 100644 index 20c184d2626..00000000000 --- a/target/linux/qualcommax/patches-6.18/0070-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 5ca3d42384a66bcb66f91d75da16ec9e9f053aab Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Mon, 21 Jul 2025 10:04:36 +0400 -Subject: arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor - clock - -The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output -clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 -to the analog block routing channel. Update the xo_board_clk nodes in -the board DTS files to use clock-div/clock-mult accordingly. - -Reviewed-by: Konrad Dybcio -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -44,7 +44,8 @@ - }; - - xo_board_clk: xo-board-clk { -- compatible = "fixed-clock"; -+ compatible = "fixed-factor-clock"; -+ clocks = <&ref_96mhz_clk>; - #clock-cells = <0>; - }; - diff --git a/target/linux/qualcommax/patches-6.18/0071-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch b/target/linux/qualcommax/patches-6.18/0071-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch deleted file mode 100644 index abf0cab5b55..00000000000 --- a/target/linux/qualcommax/patches-6.18/0071-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch +++ /dev/null @@ -1,120 +0,0 @@ -From patchwork Mon Sep 15 09:24:18 2025 -Content-Type: text/plain; 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- Mon, 15 Sep 2025 09:24:36 +0000 (UTC) -Date: Mon, 15 Sep 2025 13:24:18 +0400 -Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP3 I2C node -Precedence: bulk -X-Mailing-List: linux-arm-msm@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -Message-Id: <20250915-ipq5018-i2c-v1-1-46bbf27396d6@outlook.com> -X-B4-Tracking: v=1; b=H4sIAEHbx2gC/x3MQQqAIBBA0avIrBNmBMu6SrSQGms2ZQoRiHdPW - r7F/wUyJ+EMkyqQ+JEs19lAnYL18OfOWrZmMGgsjkRa4m2RnBazavQYPA29ceSgFTFxkPe/zUu - tH1sLzpNdAAAA -X-Change-ID: 20250911-ipq5018-i2c-0a0fa1762818 -To: Bjorn Andersson , - Konrad Dybcio , Rob Herring , - Krzysztof Kozlowski , - Conor Dooley -Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, - Vandhiadevan Karunamoorthy , - George Moussalem -X-Mailer: b4 0.14.2 -X-Developer-Signature: v=1; a=ed25519-sha256; t=1757928274; l=1420; - i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; - bh=5AMg7/oGtHNBWL+11z9Q/HGGQ9F6ll9nuoBPaZhI9aM=; - b=YRzjCtxRPYCTIZbfjE7Ch/iQgVk2FPQ2D3Z9XheAftOihKy/1/tmjGVVJNjCCP6dXt51fm4rq - wtSUjXqnECrAN3FPi6I7N+IBTc6A+E6Q/wpYazdNwaMdyxGBj0tyK4f -X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; - pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= -X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 - with auth_id=364 -X-Original-From: George Moussalem -Reply-To: george.moussalem@outlook.com -From: George Moussalem - -From: Vandhiadevan Karunamoorthy - -Add node to support I2C bus inside of IPQ5018. - -Signed-off-by: Vandhiadevan Karunamoorthy -Signed-off-by: George Moussalem ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - - ---- -base-commit: b0971d2008c644b9064d968d440fb9f44606d90c -change-id: 20250911-ipq5018-i2c-0a0fa1762818 - -Best regards, - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -504,6 +504,21 @@ - status = "disabled"; - }; - -+ blsp1_i2c3: i2c@78b7000 { -+ compatible = "qcom,i2c-qup-v2.2.1"; -+ reg = <0x078b7000 0x600>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ clock-frequency = <400000>; -+ dmas = <&blsp_dma 9>, <&blsp_dma 8>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ - qpic_bam: dma-controller@7984000 { - compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; - reg = <0x07984000 0x1c000>; diff --git a/target/linux/qualcommax/patches-6.18/0072-v6.18-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch b/target/linux/qualcommax/patches-6.18/0072-v6.18-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch deleted file mode 100644 index e27807583e9..00000000000 --- a/target/linux/qualcommax/patches-6.18/0072-v6.18-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch +++ /dev/null @@ -1,36 +0,0 @@ -From b410d25fb349bc32132749bd2cb17aa17054287d Mon Sep 17 00:00:00 2001 -From: Manikanta Mylavarapu -Date: Wed, 17 Sep 2025 15:49:00 +0400 -Subject: arm64: dts: qcom: ipq5018: add QUP1 UART2 node - -Add node to support the second UART node controller in IPQ5018. - -Signed-off-by: Manikanta Mylavarapu -Signed-off-by: George Moussalem -Link: https://lore.kernel.org/r/20250917-ipq5018-uart2-v1-1-f8680bbf947f@outlook.com -Signed-off-by: Bjorn Andersson ---- - arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi') - ---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi -@@ -490,6 +490,16 @@ - status = "disabled"; - }; - -+ blsp1_uart2: serial@78b0000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x078b0000 0x200>; -+ interrupts = ; -+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, -+ <&gcc GCC_BLSP1_AHB_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ - blsp1_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.18/0086-v6.17-dt-bindings-net-qca-ar803x-Add-IPQ5018-Internal-GE-PHY-support.patch b/target/linux/qualcommax/patches-6.18/0086-v6.17-dt-bindings-net-qca-ar803x-Add-IPQ5018-Internal-GE-PHY-support.patch deleted file mode 100644 index 52ff962cf4d..00000000000 --- a/target/linux/qualcommax/patches-6.18/0086-v6.17-dt-bindings-net-qca-ar803x-Add-IPQ5018-Internal-GE-PHY-support.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 82eaf94d69fce20f8859a2b8dae8e7064d9343da Mon Sep 17 00:00:00 2001 -From: George Moussalem -Date: Fri, 13 Jun 2025 05:55:07 +0400 -Subject: [PATCH] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY - support - -Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 -SoC. Its output pins provide an MDI interface to either an external -switch in a PHY to PHY link scenario or is directly attached to an RJ45 -connector. - -The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and -802.3az EEE. - -For operation, the LDO controller found in the IPQ5018 SoC for which -there is provision in the mdio-4019 driver. - -Two common archictures across IPQ5018 boards are: -1. IPQ5018 PHY --> MDI --> RJ45 connector -2. IPQ5018 PHY --> MDI --> External PHY -In a phy to phy architecture, the DAC needs to be configured to -accommodate for the short cable length. As such, add an optional boolean -property so the driver sets preset DAC register values accordingly. - -Signed-off-by: George Moussalem -Reviewed-by: Krzysztof Kozlowski -Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-1-9af06e34ea6b@outlook.com -Signed-off-by: Jakub Kicinski ---- - .../devicetree/bindings/net/qca,ar803x.yaml | 43 +++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml -+++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml -@@ -16,8 +16,37 @@ description: | - - allOf: - - $ref: ethernet-phy.yaml# -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - ethernet-phy-id004d.d0c0 -+ -+ then: -+ properties: -+ reg: -+ const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC -+ -+ resets: -+ items: -+ - description: -+ GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines. -+ -+ qcom,dac-preset-short-cable: -+ description: -+ Set if this phy is connected to another phy to adjust the values for -+ MDAC and EDAC to adjust amplitude, bias current settings, and error -+ detection and correction algorithm to accommodate for short cable length. -+ If not set, DAC values are not modified and it is assumed the MDI output pins -+ of this PHY are directly connected to an RJ45 connector. -+ type: boolean - - properties: -+ compatible: -+ enum: -+ - ethernet-phy-id004d.d0c0 -+ - qca,clk-out-frequency: - description: Clock output frequency in Hertz. - $ref: /schemas/types.yaml#/definitions/uint32 -@@ -132,3 +161,17 @@ examples: - }; - }; - }; -+ - | -+ #include -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ge_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-id004d.d0c0"; -+ reg = <7>; -+ -+ resets = <&gcc GCC_GEPHY_MISC_ARES>; -+ }; -+ }; diff --git a/target/linux/qualcommax/patches-6.18/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch b/target/linux/qualcommax/patches-6.18/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch deleted file mode 100644 index a12dc442061..00000000000 --- a/target/linux/qualcommax/patches-6.18/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch +++ /dev/null @@ -1,43 +0,0 @@ -From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 16 Nov 2022 22:26:25 +0100 -Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe - -Instead of hardcoding the IRQ, simply use msi-parent instead. - -Signed-off-by: Robert Marko ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++----- - 1 file changed, 3 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -759,7 +759,7 @@ - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; - ranges = <0 0xb00a000 0xffd>; - -- v2m@0 { -+ gic_v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xffd>; -@@ -872,8 +872,7 @@ - ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ - <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ - -- interrupts = ; -- interrupt-names = "msi"; -+ msi-parent = <&gic_v2m0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 142 -@@ -944,8 +943,7 @@ - ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ - <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ - -- interrupts = ; -- interrupt-names = "msi"; -+ msi-parent = <&gic_v2m0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 diff --git a/target/linux/qualcommax/patches-6.18/0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch b/target/linux/qualcommax/patches-6.18/0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch deleted file mode 100644 index 6ff9b323381..00000000000 --- a/target/linux/qualcommax/patches-6.18/0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 54280bff5b17407e8b23cdeafdc63f4d43ad1ee5 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 27 Nov 2025 13:49:06 +0100 -Subject: [PATCH] net: phy: aquantia: enable USXGMII MAC autoneg - -USXGMII MAC autoneg control bit is always set disabled by default, in order -for USXGMII to work properly we must enable it. - -Signed-off-by: Robert Marko ---- - drivers/net/phy/aquantia/aquantia_main.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/net/phy/aquantia/aquantia_main.c -+++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -46,6 +46,9 @@ - #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 - #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 - -+#define MDIO_PHYXS_VEND_PROV2 0xc441 -+#define MDIO_PHYXS_VEND_PROV2_USX_AUTONEG_MAC BIT(3) -+ - #define MDIO_AN_VEND_PROV 0xc400 - #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) - #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) -@@ -440,6 +443,10 @@ static int aqr107_read_status(struct phy - break; - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: - phydev->interface = PHY_INTERFACE_MODE_USXGMII; -+ phy_modify_mmd(phydev, MDIO_MMD_PHYXS, -+ MDIO_PHYXS_VEND_PROV2, -+ MDIO_PHYXS_VEND_PROV2_USX_AUTONEG_MAC, -+ MDIO_PHYXS_VEND_PROV2_USX_AUTONEG_MAC); - break; - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: - phydev->interface = PHY_INTERFACE_MODE_XAUI; diff --git a/target/linux/qualcommax/patches-6.18/0843-net-stmmac-add-get_interfaces-platform-method.patch b/target/linux/qualcommax/patches-6.18/0843-net-stmmac-add-get_interfaces-platform-method.patch deleted file mode 100644 index 3e415d24fbd..00000000000 --- a/target/linux/qualcommax/patches-6.18/0843-net-stmmac-add-get_interfaces-platform-method.patch +++ /dev/null @@ -1,56 +0,0 @@ -From ca732e990fc8222a2d6782ae750304719e212fe8 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Thu, 1 May 2025 12:45:11 +0100 -Subject: [PATCH] net: stmmac: add get_interfaces() platform method - -Add a get_interfaces() platform method to allow platforms to indicate -to phylink which interface modes they support - which then allows -phylink to validate on initialisation that the configured PHY interface -mode is actually supported. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1uASLn-0021Qd-Mi@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski ---- - .../net/ethernet/stmicro/stmmac/stmmac_main.c | 16 +++++++++++++--- - include/linux/stmmac.h | 2 ++ - 2 files changed, 15 insertions(+), 3 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -1250,10 +1250,21 @@ static int stmmac_phy_setup(struct stmma - priv->phylink_config.default_an_inband = - mdio_bus_data->default_an_inband; - -- /* Set the platform/firmware specified interface mode. Note, phylink -- * deals with the PHY interface mode, not the MAC interface mode. -+ /* Get the PHY interface modes (at the PHY end of the link) that -+ * are supported by the platform. - */ -- __set_bit(mode, priv->phylink_config.supported_interfaces); -+ if (priv->plat->get_interfaces) -+ priv->plat->get_interfaces(priv, priv->plat->bsp_priv, -+ priv->phylink_config.supported_interfaces); -+ -+ /* Set the platform/firmware specified interface mode if the -+ * supported interfaces have not already been provided using -+ * phy_interface as a last resort. -+ */ -+ if (phy_interface_empty(priv->phylink_config.supported_interfaces)) -+ __set_bit(priv->plat->phy_interface, -+ priv->phylink_config.supported_interfaces); -+ - - /* If we have an xpcs, it defines which PHY interfaces are supported. */ - if (priv->hw->xpcs) ---- a/include/linux/stmmac.h -+++ b/include/linux/stmmac.h -@@ -229,6 +229,8 @@ struct plat_stmmacenet_data { - u8 tx_sched_algorithm; - struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; - struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; -+ void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv, -+ unsigned long *interfaces); - void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode); - int (*fix_soc_reset)(void *priv, void __iomem *ioaddr); - int (*serdes_powerup)(struct net_device *ndev, void *priv);