From: Thomas Preud'homme <thomas.preudhomme@arm.com>
Date: Wed, 18 Apr 2018 13:17:30 +0000 (+0000)
Subject: [ARM] Fix PR85261: ICE with FPSCR setter builtin
X-Git-Tag: releases/gcc-6.5.0~366
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fac908cfe0e145bf85fa396125c7c382ba3a9fcd;p=thirdparty%2Fgcc.git

[ARM] Fix PR85261: ICE with FPSCR setter builtin

Instruction pattern for setting the FPSCR expects the input value to be
in a register. However, __builtin_arm_set_fpscr expander does not ensure
that this is the case and as a result GCC ICEs when the builtin is
called with a constant literal.

This commit fixes the builtin to force the input value into a register.
It also remove the unneeded volatile in the existing fpscr test and
fixes the function prototype.

2018-04-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    Backport from mainline
    2018-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR target/85261
    * config/arm/arm-builtins.c (arm_expand_builtin): Force input operand
    into register.

    gcc/testsuite/
    PR target/85261
    * gcc.target/arm/fpscr.c: Add call to __builtin_arm_set_fpscr with
    literal value.  Expect 2 MCR instruction.  Fix function prototype.
    Remove volatile keyword.

From-SVN: r259469
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2dbf8f1eb140..2631728fc5f6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2018-04-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	Backport from mainline
+	2018-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR target/85261
+	* config/arm/arm-builtins.c (arm_expand_builtin): Force input operand
+	into register.
+
 2018-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from mainline
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 809c43e7d8d0..cba582fa6684 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -2368,7 +2368,7 @@ arm_expand_builtin (tree exp,
 	  icode = CODE_FOR_set_fpscr;
 	  arg0 = CALL_EXPR_ARG (exp, 0);
 	  op0 = expand_normal (arg0);
-	  pat = GEN_FCN (icode) (op0);
+	  pat = GEN_FCN (icode) (force_reg (SImode, op0));
 	}
       emit_insn (pat);
       return target;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e663523b3177..a03fe2e98102 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2018-04-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	Backport from mainline
+	2018-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	PR target/85261
+	* gcc.target/arm/fpscr.c: Add call to __builtin_arm_set_fpscr with
+	literal value.  Expect 2 MCR instruction.  Fix function prototype.
+	Remove volatile keyword.
+
 2018-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/gcc.target/arm/fpscr.c b/gcc/testsuite/gcc.target/arm/fpscr.c
index 7b4d71d72d89..4c3eaf7fcf75 100644
--- a/gcc/testsuite/gcc.target/arm/fpscr.c
+++ b/gcc/testsuite/gcc.target/arm/fpscr.c
@@ -6,11 +6,14 @@
 /* { dg-add-options arm_fp } */
 
 void
-test_fpscr ()
+test_fpscr (void)
 {
-  volatile unsigned int status = __builtin_arm_get_fpscr ();
+  unsigned status;
+
+  __builtin_arm_set_fpscr (0);
+  status = __builtin_arm_get_fpscr ();
   __builtin_arm_set_fpscr (status);
 }
 
 /* { dg-final { scan-assembler "mrc\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */
-/* { dg-final { scan-assembler "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */
+/* { dg-final { scan-assembler-times "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" 2 } } */