From: Greg Kroah-Hartman Date: Tue, 5 Mar 2024 07:44:43 +0000 (+0000) Subject: 6.7-stable patches X-Git-Tag: v4.19.309~4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fb22d5f2f746cd590f8d245743a7cc97794c4b9c;p=thirdparty%2Fkernel%2Fstable-queue.git 6.7-stable patches added patches: riscv-add-a-custom-isa-extension-for-the-envcfg-csr.patch --- diff --git a/queue-6.7/riscv-add-a-custom-isa-extension-for-the-envcfg-csr.patch b/queue-6.7/riscv-add-a-custom-isa-extension-for-the-envcfg-csr.patch new file mode 100644 index 00000000000..06a4ca9ef17 --- /dev/null +++ b/queue-6.7/riscv-add-a-custom-isa-extension-for-the-envcfg-csr.patch @@ -0,0 +1,86 @@ +From 4774848fef6041716a4883217eb75f6b10eb183b Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Tue, 27 Feb 2024 22:55:34 -0800 +Subject: riscv: Add a custom ISA extension for the [ms]envcfg CSR + +From: Samuel Holland + +commit 4774848fef6041716a4883217eb75f6b10eb183b upstream. + +The [ms]envcfg CSR was added in version 1.12 of the RISC-V privileged +ISA (aka S[ms]1p12). However, bits in this CSR are defined by several +other extensions which may be implemented separately from any particular +version of the privileged ISA (for example, some unrelated errata may +prevent an implementation from claiming conformance with Ss1p12). As a +result, Linux cannot simply use the privileged ISA version to determine +if the CSR is present. It must also check if any of these other +extensions are implemented. It also cannot probe the existence of the +CSR at runtime, because Linux does not require Sstrict, so (in the +absence of additional information) it cannot know if a CSR at that +address is [ms]envcfg or part of some non-conforming vendor extension. + +Since there are several standard extensions that imply the existence of +the [ms]envcfg CSR, it becomes unwieldy to check for all of them +wherever the CSR is accessed. Instead, define a custom Xlinuxenvcfg ISA +extension bit that is implied by the other extensions and denotes that +the CSR exists as defined in the privileged ISA, containing at least one +of the fields common between menvcfg and senvcfg. + +This extension does not need to be parsed from the devicetree or ISA +string because it can only be implemented as a subset of some other +standard extension. + +Cc: # v6.7+ +Signed-off-by: Samuel Holland +Reviewed-by: Conor Dooley +Reviewed-by: Andrew Jones +Link: https://lore.kernel.org/r/20240228065559.3434837-3-samuel.holland@sifive.com +Signed-off-by: Palmer Dabbelt +Cc: Ron Economos +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/include/asm/hwcap.h | 2 ++ + arch/riscv/kernel/cpufeature.c | 14 ++++++++++++-- + 2 files changed, 14 insertions(+), 2 deletions(-) + +--- a/arch/riscv/include/asm/hwcap.h ++++ b/arch/riscv/include/asm/hwcap.h +@@ -58,6 +58,8 @@ + #define RISCV_ISA_EXT_SMSTATEEN 43 + #define RISCV_ISA_EXT_ZICOND 44 + ++#define RISCV_ISA_EXT_XLINUXENVCFG 127 ++ + #define RISCV_ISA_EXT_MAX 64 + + #ifdef CONFIG_RISCV_M_MODE +--- a/arch/riscv/kernel/cpufeature.c ++++ b/arch/riscv/kernel/cpufeature.c +@@ -115,6 +115,16 @@ static bool riscv_isa_extension_check(in + } + + /* ++ * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V ++ * privileged ISA, the existence of the CSRs is implied by any extension which ++ * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the ++ * existence of the CSR, and treat it as a subset of those other extensions. ++ */ ++static const unsigned int riscv_xlinuxenvcfg_exts[] = { ++ RISCV_ISA_EXT_XLINUXENVCFG ++}; ++ ++/* + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * +@@ -167,8 +177,8 @@ const struct riscv_isa_ext_data riscv_is + __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p), + __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), +- __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), +- __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), ++ __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), ++ __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), diff --git a/queue-6.7/series b/queue-6.7/series index 1b5a25ca8f1..78bcde552e1 100644 --- a/queue-6.7/series +++ b/queue-6.7/series @@ -105,6 +105,7 @@ ceph-switch-to-corrected-encoding-of-max_xattr_size-in-mdsmap.patch risc-v-drop-invalid-test-from-config_as_has_option_arch.patch riscv-add-caller_addrx-support.patch riscv-fix-enabling-cbo.zero-when-running-in-m-mode.patch +riscv-add-a-custom-isa-extension-for-the-envcfg-csr.patch riscv-save-restore-envcfg-csr-during-cpu-suspend.patch power-supply-mm8013-select-regmap_i2c.patch kbuild-add-wa-fatal-warnings-to-as-instr-invocation.patch