From: Srinivasan Shanmugam Date: Mon, 23 Mar 2026 04:54:15 +0000 (+0530) Subject: drm/amd/display: Add NULL check for integrated_info in clk_mgr_construct X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fbe3a5743a4f34f57f25ab68d701d38d3b24ac3a;p=thirdparty%2Flinux.git drm/amd/display: Add NULL check for integrated_info in clk_mgr_construct clk_mgr_construct() initializes display clock and memory bandwidth settings during driver bring-up. As part of this, the driver selects a watermark table based on the memory type (DDR4, LPDDR4, LPDDR5) from ctx->dc_bios->integrated_info. The display pipeline continuously reads pixel data from memory, processes it (such as scaling, color conversion, and blending), and sends it to the screen. To keep this pipeline running smoothly, the driver must ensure there is enough memory bandwidth and that clocks are increased when needed. Watermark tables define when the GPU should increase clocks to ensure there is enough bandwidth to feed pixel data without underflow. However, ctx->dc_bios->integrated_info is dereferenced without checking for NULL in multiple clk_mgr_construct() implementations. On some platforms, BIOS may not provide this information, and accessing it directly can cause a NULL pointer dereference during initialization. Fix this by adding a NULL check before accessing integrated_info. If integrated_info is not available, the driver safely falls back to default watermark tables. Fixes: ../dcn21/rn_clk_mgr.c:775 rn_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 743) ../dcn301/vg_clk_mgr.c:750 vg_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 736) ../dcn31/dcn31_clk_mgr.c:789 dcn31_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 728) ../dcn314/dcn314_clk_mgr.c:906 dcn314_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 845) ../dcn315/dcn315_clk_mgr.c:716 dcn315_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 655) ../dcn316/dcn316_clk_mgr.c:660 dcn316_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 639) ../dcn35/dcn35_clk_mgr.c:1540 dcn35_clk_mgr_construct() warn: variable dereferenced before check 'ctx->dc_bios->integrated_info' (see line 1467) Fixes: 25879d7b4986 ("drm/amd/display: Clean FPGA code in dc") Cc: Roman Li Cc: Alex Hung Cc: Tom Chung Cc: Dan Carpenter Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Hung Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index e18097f820915..09e83097a623b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -740,7 +740,8 @@ void rn_clk_mgr_construct( if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 3600000; - if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { if (clk_mgr->periodic_retraining_disabled) { rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; } else { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c index 7aee02d562923..57ba7bc4d16e6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c @@ -733,11 +733,12 @@ void vg_clk_mgr_construct( if (clk_mgr->base.base.dentist_vco_freq_khz == 0) clk_mgr->base.base.dentist_vco_freq_khz = 3600000; - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) vg_bw_params.wm_table = lpddr5_wm_table; - } else { + else vg_bw_params.wm_table = ddr4_wm_table; - } + /* Saved clocks configured at boot for debug purposes */ vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index 051052bd10c96..44bf48f961832 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -725,11 +725,12 @@ void dcn31_clk_mgr_construct( /* TODO: Check we get what we expect during bringup */ clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) dcn31_bw_params.wm_table = lpddr5_wm_table; - } else { + else dcn31_bw_params.wm_table = ddr5_wm_table; - } + /* Saved clocks configured at boot for debug purposes */ dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 0cb37827a62b6..c69ec7a0e0aeb 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -842,7 +842,8 @@ void dcn314_clk_mgr_construct( /* TODO: Check we get what we expect during bringup */ clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) dcn314_bw_params.wm_table = lpddr5_wm_table; else dcn314_bw_params.wm_table = ddr5_wm_table; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index c49268db85f68..8d6949ad700df 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -652,11 +652,12 @@ void dcn315_clk_mgr_construct( if (clk_mgr->base.smu_ver > 0) clk_mgr->base.smu_present = true; - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) dcn315_bw_params.wm_table = lpddr5_wm_table; - } else { + else dcn315_bw_params.wm_table = ddr5_wm_table; - } + /* Saved clocks configured at boot for debug purposes */ dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index 1769b1f26e757..b858e21ca0707 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -636,11 +636,12 @@ void dcn316_clk_mgr_construct( clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */ - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) dcn316_bw_params.wm_table = lpddr5_wm_table; - } else { + else dcn316_bw_params.wm_table = ddr4_wm_table; - } + /* Saved clocks configured at boot for debug purposes */ dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 6fc5247526132..2798088842f41 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -1464,11 +1464,12 @@ void dcn35_clk_mgr_construct( /* TODO: Check we get what we expect during bringup */ clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + if (ctx->dc_bios->integrated_info && + ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) dcn35_bw_params.wm_table = lpddr5_wm_table; - } else { + else dcn35_bw_params.wm_table = ddr5_wm_table; - } + /* Saved clocks configured at boot for debug purposes */ dcn35_save_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);