From: Varadarajan Narayanan Date: Thu, 5 Feb 2026 08:59:34 +0000 (+0530) Subject: arm64: dts: qcom: ipq9574-rdp433: Reorganize DTS to introduce eMMC support X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fc1fd9d52a88f1efabe9c2e34fa78245cfc6380b;p=thirdparty%2Flinux.git arm64: dts: qcom: ipq9574-rdp433: Reorganize DTS to introduce eMMC support The RDP433 has NAND and eMMC variants. Presently, only NAND variant is supported. To enable support for eMMC variant, move the common nodes from ipq9574-rdp433.dts to ipq9574-rdp433-common.dtsi. ipq9574-rdp433-common.dtsi will be included in rdp433 NAND and eMMC DT files. Reviewed-by: Konrad Dybcio Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20260205085936.3220108-3-varadarajan.narayanan@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi new file mode 100644 index 0000000000000..3422058ac4801 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ9574 RDP433 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2 { + pinctrl-0 = <&pcie2_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie3_phy { + status = "okay"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&tlmm { + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio25"; + function = "pcie1_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio27"; + function = "pcie1_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins = "gpio28"; + function = "pcie2_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio30"; + function = "pcie2_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio31"; + function = "pcie3_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio32"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio33"; + function = "pcie3_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 73091067bad28..88439697c0747 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -8,128 +8,14 @@ /dts-v1/; -#include #include "ipq9574-rdp-common.dtsi" +#include "ipq9574-rdp433-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; }; -&pcie1_phy { - status = "okay"; -}; - -&pcie1 { - pinctrl-0 = <&pcie1_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie2_phy { - status = "okay"; -}; - -&pcie2 { - pinctrl-0 = <&pcie2_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie3_phy { - status = "okay"; -}; - -&pcie3 { - pinctrl-0 = <&pcie3_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - &qpic_nand { status = "okay"; }; - -&tlmm { - - pcie1_default: pcie1-default-state { - clkreq-n-pins { - pins = "gpio25"; - function = "pcie1_clk"; - drive-strength = <6>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio26"; - function = "gpio"; - drive-strength = <8>; - bias-pull-down; - output-low; - }; - - wake-n-pins { - pins = "gpio27"; - function = "pcie1_wake"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - pcie2_default: pcie2-default-state { - clkreq-n-pins { - pins = "gpio28"; - function = "pcie2_clk"; - drive-strength = <6>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio29"; - function = "gpio"; - drive-strength = <8>; - bias-pull-down; - output-low; - }; - - wake-n-pins { - pins = "gpio30"; - function = "pcie2_wake"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - pcie3_default: pcie3-default-state { - clkreq-n-pins { - pins = "gpio31"; - function = "pcie3_clk"; - drive-strength = <6>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio32"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - output-low; - }; - - wake-n-pins { - pins = "gpio33"; - function = "pcie3_wake"; - drive-strength = <6>; - bias-pull-up; - }; - }; -};