From: Claudiu Zissulescu Date: Thu, 14 Nov 2019 09:58:19 +0000 (+0000) Subject: [ARC] Backport from mainline r278056,r278057 X-Git-Tag: releases/gcc-9.3.0~387 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fc2d906f47de521bc97e1d2dcdd65474c3c54f52;p=thirdparty%2Fgcc.git [ARC] Backport from mainline r278056,r278057 From-SVN: r278215 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cbb068fbfe68..63209837908c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2019-11-13 Claudiu Zissulescu + + Backport from mainline + * config/arc/arc.md (movsi_ne): Reorder instruction variants and + use new register constraint letters. + * config/arc/arc.c (arc_legitimize_pic_address): Consider UNSPECs + as well, if interesting recover the symbol and re-legitimize the + pic address. + 2019-11-14 Martin Liska Backport from mainline diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index ee1f70bbb515..e6e4fb18ce1a 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -5992,6 +5992,22 @@ arc_legitimize_pic_address (rtx addr) switch (GET_CODE (addr)) { + case UNSPEC: + /* Can be one or our GOT or GOTOFFPC unspecs. This situation + happens when an address is not a legitimate constant and we + need the resolve it via force_reg in + prepare_move_operands. */ + switch (XINT (addr, 1)) + { + case ARC_UNSPEC_GOT: + case ARC_UNSPEC_GOTOFFPC: + /* Recover the symbol ref. */ + addr = XVECEXP (addr, 0, 0); + break; + default: + return addr; + } + /* Fall through. */ case SYMBOL_REF: /* TLS symbols are handled in different place. */ if (SYMBOL_REF_TLS_MODEL (addr)) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 78e304d4c714..722cccd8be38 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -3742,20 +3742,20 @@ core_3, archs4x, archs4xd, archs4xd_slow" ; cond_exec patterns (define_insn "*movsi_ne" [(cond_exec - (ne (match_operand:CC_Z 2 "cc_use_register" "Rcc, Rcc, Rcc,Rcc,Rcc") (const_int 0)) - (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q, w,w") - (match_operand:SI 1 "nonmemory_operand" "C_0, h, ?Cal, Lc,?Cal")))] + (ne (match_operand:CC_Z 2 "cc_use_register" "Rcc,Rcc,Rcc,Rcc,Rcc") (const_int 0)) + (set (match_operand:SI 0 "dest_reg_operand" "=q, q, r, q, r") + (match_operand:SI 1 "nonmemory_operand" "C_0, h, Lr,Cal,Cal")))] "" "@ - * current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\"; - * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; - * current_insn_predicate = 0; return \"mov%?.ne %0,%1\"; - mov.ne %0,%1 - mov.ne %0,%1" + * current_insn_predicate = 0; return \"sub%?.ne\\t%0,%0,%0\"; + * current_insn_predicate = 0; return \"mov%?.ne\\t%0,%1\"; + mov.ne\\t%0,%1 + * current_insn_predicate = 0; return \"mov%?.ne\\t%0,%1\"; + mov.ne\\t%0,%1" [(set_attr "type" "cmove") - (set_attr "iscompact" "true,true,true_limm,false,false") - (set_attr "length" "2,2,6,4,8") - (set_attr "cpu_facility" "*,av2,av2,*,*")]) + (set_attr "iscompact" "true,true,false,true_limm,false") + (set_attr "length" "2,2,4,6,8") + (set_attr "cpu_facility" "*,av2,*,av2,*")]) (define_insn "*movsi_cond_exec" [(cond_exec diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8f97012e5cd8..1ae0ef123a03 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2019-11-13 Claudiu Zissulescu + + Backport from mainline + * gcc.target/arc/delay-slot-limm.c: New test. + * gcc.target/arc/pic-2.c: New file. + 2019-11-13 Tobias Burnus PR fortran/92470 diff --git a/gcc/testsuite/gcc.target/arc/delay-slot-limm.c b/gcc/testsuite/gcc.target/arc/delay-slot-limm.c new file mode 100644 index 000000000000..e5de3c4baddc --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/delay-slot-limm.c @@ -0,0 +1,52 @@ +/* We have encountered an issue that a "mov_s.ne" instruction * + * with an immediate value was put in the delay slot of a * + * branch: * + * * + * bne.d @.L1 # 33 [c=20 l=4] *branch_insn * + * mov_s.ne r0,7 # 35 [c=0 l=6] *movsi_ne/2 * + * * + * This is not sanctioned and must not happen. The test below * + * is a reduced version of the source code leading to the * + * problem. */ + +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=archs -Og" } */ +typedef struct +{ + struct + { + int length; + } table; +} room; + +struct house +{ + room *r; +}; + +int glob; + +_Bool bar(); + +int func(struct house *h, int i, int whatever) +{ + for (;;) + { + _Bool a; + if (h && h->r[i].table.length == glob) + { + if (whatever) + { + a = bar(); + if (__builtin_expect(!a, 0)) + return 7; + } + break; + } + } + return 0; +} + +/* no 'mov_s.ne r,limm' in a delay slot */ +/* { dg-final { scan-assembler-not "bne.d\.*\n\\s\+mov_s.ne\\s+r\[0-9\]+,7" } } */ diff --git a/gcc/testsuite/gcc.target/arc/pic-2.c b/gcc/testsuite/gcc.target/arc/pic-2.c new file mode 100644 index 000000000000..4b0e17126e91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pic-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-skip-if "PIC not available for ARC6xx" { arc6xx } } */ +/* { dg-options "-mno-sdata -O2 -fpic -fno-builtin" } */ + +/* Check if we resolve correctly complex PIC addresses. */ + +char *foo (unsigned size) +{ + static char buf[32]; + register int i; + + if (size > 31) + size = 31; + + for (i = 0; i < size; i++) + { + buf[i] = ' '; + } + buf[size] = '\0'; + return buf; +} + +/* { dg-final { scan-assembler "@buf.\[0-9\]\+@pcl-1" } } */