From: Ju-Zhe Zhong Date: Tue, 7 Feb 2023 06:29:16 +0000 (+0800) Subject: RISC-V: Add vwmulu C API tests X-Git-Tag: basepoints/gcc-14~1329 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fcbe69a096a1c1b2b2a06c2f740e32e9166e9b99;p=thirdparty%2Fgcc.git RISC-V: Add vwmulu C API tests gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwmulu_vv-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c: New test. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-1.c new file mode 100644 index 000000000000..658bdf33ab2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-2.c new file mode 100644 index 000000000000..e5e8767818eb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-3.c new file mode 100644 index 000000000000..25c01ac54516 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c new file mode 100644 index 000000000000..3c41f86355ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c new file mode 100644 index 000000000000..b6f1e6e8ae46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c new file mode 100644 index 000000000000..9a4c7ca16d48 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c new file mode 100644 index 000000000000..412a79378ac3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c new file mode 100644 index 000000000000..bb65c611efa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c new file mode 100644 index 000000000000..3f8d78488113 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c new file mode 100644 index 000000000000..41f4e018008a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c new file mode 100644 index 000000000000..74c8e54b05e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c new file mode 100644 index 000000000000..39a16149fdf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c new file mode 100644 index 000000000000..b547a9d5336e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c new file mode 100644 index 000000000000..f3b27f118f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c new file mode 100644 index 000000000000..8273d3cc7150 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c new file mode 100644 index 000000000000..692e86a5b29d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c new file mode 100644 index 000000000000..ceea89e9746f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c new file mode 100644 index 000000000000..28c781b667f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulu_vv_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-1.c new file mode 100644 index 000000000000..a9e8e0a401d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-2.c new file mode 100644 index 000000000000..994cdf60370b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-3.c new file mode 100644 index 000000000000..cac5951ad814 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c new file mode 100644 index 000000000000..ac025b59da7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c new file mode 100644 index 000000000000..ef33bd442aa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c new file mode 100644 index 000000000000..439f28274e0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c new file mode 100644 index 000000000000..f646caf36352 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c new file mode 100644 index 000000000000..be84241af867 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c new file mode 100644 index 000000000000..329c0c187477 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c new file mode 100644 index 000000000000..d5de50cf620d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c new file mode 100644 index 000000000000..bcd03dfd4971 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c new file mode 100644 index 000000000000..5b24d72a28f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c new file mode 100644 index 000000000000..a904be747a5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c new file mode 100644 index 000000000000..7435790ce560 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c new file mode 100644 index 000000000000..d1af8f5d9e90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c new file mode 100644 index 000000000000..c85f96aab776 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c new file mode 100644 index 000000000000..6249a048b8ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c new file mode 100644 index 000000000000..804ecac6d8c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmulu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwmulu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwmulu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwmulu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwmulu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwmulu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwmulu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwmulu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwmulu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwmulu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwmulu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwmulu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwmulu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwmulu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwmulu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulu_vx_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */