From: Michal Simek Date: Wed, 21 Nov 2018 12:56:26 +0000 (+0100) Subject: Merge tag 'v2018.11' into master X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fdaaef0ddd48d8ca3031c5b8cbb86eea353551c6;p=thirdparty%2Fu-boot.git Merge tag 'v2018.11' into master Prepare v2018.11 Disable watchdog for zc706, zcu100 and ultra96. Signed-off-by: Michal Simek --- fdaaef0ddd48d8ca3031c5b8cbb86eea353551c6 diff --cc Makefile index d8f419bcd90,552687db538..552687db538 mode 100755,100644..100755 --- a/Makefile +++ b/Makefile diff --cc arch/arm/dts/Makefile index 79a72cec4b9,d36447d18d3..5236fda7365 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@@ -131,14 -134,10 +134,16 @@@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-cc108.dtb \ zynq-cse-nand.dtb \ zynq-cse-nor.dtb \ - zynq-cse-qspi-parallel.dtb \ zynq-cse-qspi-single.dtb \ ++ zynq-cse-qspi-parallel.dtb \ + zynq-cse-qspi-stacked.dtb \ + zynq-cse-qspi-x1-single.dtb \ + zynq-cse-qspi-x1-stacked.dtb \ + zynq-cse-qspi-x2-single.dtb \ + zynq-cse-qspi-x2-stacked.dtb \ + zynq-dlc20-rev1.0.dtb \ zynq-microzed.dtb \ + zynq-minized.dtb \ zynq-picozed.dtb \ zynq-syzygy-hub.dtb \ zynq-topic-miami.dtb \ @@@ -151,21 -150,15 +156,22 @@@ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ - zynq-zturn-myir.dtb \ - zynq-zybo.dtb + zynq-zturn.dtb \ + zynq-zybo.dtb \ + zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ + zynqmp-mini.dtb \ + zynqmp-mini-emmc0.dtb \ + zynqmp-mini-emmc1.dtb \ + zynqmp-mini-nand.dtb \ + zynqmp-mini-qspi.dtb \ + zynqmp-mini-qspi-parallel.dtb \ - zynqmp-mini-qspi-single.dtb \ + zynqmp-mini-qspi-stacked.dtb \ + zynqmp-mini-qspi-x1-single.dtb \ + zynqmp-mini-qspi-x1-stacked.dtb \ + zynqmp-mini-qspi-x2-single.dtb \ + zynqmp-mini-qspi-x2-stacked.dtb \ - zynqmp-mini-nand.dtb \ - zynqmp-mini-emmc0.dtb \ - zynqmp-mini-emmc1.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ diff --cc arch/arm/dts/zynq-zed.dts index 0c6891d6ad2,9c505fb7b87..f9cb66b0d07 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@@ -54,36 -51,12 +54,37 @@@ &qspi { u-boot,dm-pre-reloc; status = "okay"; + is-dual = <0>; num-cs = <1>; flash@0 { - compatible = "n25q128a11"; - reg = <0x0>; + compatible = "spansion,s25fl256s", "spi-flash"; + reg = <0>; - spi-max-frequency = <30000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0xC00000 0x400000>; + }; }; }; diff --cc arch/arm/dts/zynqmp-clk.dtsi index 7b8a91e494a,a795efdc15c..ef6fc8efde3 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@@ -223,15 -219,15 +223,15 @@@ }; &watchdog0 { - clocks = <&clk250>; + clocks = <&clk100>; }; -&xilinx_drm { - clocks = <&drm_clock>; +&lpd_watchdog { + clocks = <&clk250>; }; -&xlnx_dp { - clocks = <&dp_aclk>, <&dp_aud_clk>; +&zynqmp_dpsub { + clocks = <&dp_aclk>, <&dp_aud_clk>, <&drm_clock>; }; &xlnx_dpdma { diff --cc arch/arm/mach-zynq/Kconfig index 601781c02c2,a599ed63ee4..9cdaf9ce867 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@@ -66,18 -67,7 +67,21 @@@ config BOOT_INIT_FIL Add register writes to boot.bin format (max 256 pairs). Expect a table of register-value pairs, e.g. "0x12345678 0x4321" +config ZYNQ_M29EW_WB_HACK + bool "Zynq NOR hack" + default n + help + The option provides hack for Zynq NOR driver which is required + for NOR operations to work as expected. + +# Temporary Kconfig options which needs to be fixed +config SYS_I2C_MUX_ADDR + int + +config SYS_I2C_MUX_EEPROM_SEL + int + + config ZYNQ_SDHCI_MAX_FREQ + default 52000000 + endif diff --cc board/xilinx/zynq/board.c index 10ed4644cb0,614d93c082a..d18c800c620 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@@ -52,49 -35,6 +35,10 @@@ int board_early_init_f(void int board_init(void) { +#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD) + unsigned char eepromsel = CONFIG_SYS_I2C_MUX_EEPROM_SEL; +#endif - #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) - u32 idcode; - - idcode = zynq_slcr_get_idcode(); - - switch (idcode) { - case XILINX_ZYNQ_7007S: - fpga = fpga007s; - break; - case XILINX_ZYNQ_7010: - fpga = fpga010; - break; - case XILINX_ZYNQ_7012S: - fpga = fpga012s; - break; - case XILINX_ZYNQ_7014S: - fpga = fpga014s; - break; - case XILINX_ZYNQ_7015: - fpga = fpga015; - break; - case XILINX_ZYNQ_7020: - fpga = fpga020; - break; - case XILINX_ZYNQ_7030: - fpga = fpga030; - break; - case XILINX_ZYNQ_7035: - fpga = fpga035; - break; - case XILINX_ZYNQ_7045: - fpga = fpga045; - break; - case XILINX_ZYNQ_7100: - fpga = fpga100; - break; - } - #endif + #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { debug("Watchdog: Not found by seq!\n"); @@@ -108,15 -48,6 +52,10 @@@ puts("Watchdog: Started\n"); # endif - #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) - fpga_init(); - fpga_add(fpga_xilinx, &fpga); - #endif +#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD) + if (eeprom_write(CONFIG_SYS_I2C_MUX_ADDR, 0, &eepromsel, 1)) + puts("I2C:EEPROM selection failed\n"); +#endif return 0; } diff --cc configs/avnet_ultra96_rev1_defconfig index 7e337190fda,c49c9f23465..4dcdb757deb --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@@ -11,8 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y ++CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -54,6 -61,6 +62,7 @@@ CONFIG_MMC_SDHCI_ZYNQ= CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -78,7 -86,11 +88,9 @@@ CONFIG_USB_ULPI= CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_WDT=y - CONFIG_WDT_CDNS=y + CONFIG_USB_ETHER=y + CONFIG_USB_ETH_CDC=y + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_ASIX=y -CONFIG_WDT=y -CONFIG_WDT_CDNS=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_mini_defconfig index 3025f281055,00000000000..01e3b7f8e44 mode 100644,000000..100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@@ -1,48 -1,0 +1,49 @@@ +CONFIG_ARM=y - CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini" ++CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0xFFFC0000 +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +CONFIG_ZYNQMP_PSU_INIT_ENABLED=y +# CONFIG_CMD_ZYNQMP is not set - CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" - CONFIG_SYS_EXTRA_OPTIONS="MINI_QSPI" ++# CONFIG_IMAGE_FORMAT_LEGACY is not set +CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_CPUINFO is not set ++# CONFIG_CMDLINE_EDITING is not set ++# CONFIG_AUTO_COMPLETE is not set ++# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set - # CONFIG_CMD_FPGA is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set - # CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +# CONFIG_PARTITIONS is not set +CONFIG_OF_EMBED=y ++CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" ++# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +# CONFIG_EFI_LOADER is not set diff --cc configs/xilinx_zynqmp_mini_qspi_defconfig index 1713b1ad316,db129b6ce7d..7a03ea99e72 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@@ -51,7 -53,6 +53,8 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --cc configs/xilinx_zynqmp_zc1232_revA_defconfig index 5279834302b,7521fc4e34e..d4fd93dea2e --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@@ -13,12 -12,7 +12,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -29,10 -23,7 +24,9 @@@ CONFIG_CMD_CLK= # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y @@@ -48,16 -39,12 +43,17 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y - CONFIG_REGEX=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_zc1254_revA_defconfig index 95c375c0553,e0822b931ed..d7bee77ae07 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@@ -13,12 -12,7 +12,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -29,10 -23,7 +24,9 @@@ CONFIG_CMD_CLK= # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y @@@ -48,16 -39,12 +43,17 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y - CONFIG_REGEX=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_zc1275_revA_defconfig index 1e1254fa191,3afed697370..46500c0ea6a --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@@ -13,12 -12,7 +12,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -29,10 -23,7 +24,9 @@@ CONFIG_CMD_CLK= # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y @@@ -48,16 -39,12 +43,17 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y - CONFIG_REGEX=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_zc1275_revB_defconfig index 8be70ea3b5d,7e31b1112f8..878c66453d7 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@@ -14,12 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -29,15 -24,13 +25,16 @@@ CONFIG_CMD_CLK= # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y - # CONFIG_CMD_NFS is not set + # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y @@@ -50,19 -42,12 +47,21 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_XILINX_GMII2RGMII=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 3a7503059fd,ec26dd70fd5..86913c74f06 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@@ -14,12 -13,8 +13,9 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -63,13 -57,11 +60,15 @@@ CONFIG_DM_I2C= CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y CONFIG_DM_MMC=y + CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -83,12 -75,11 +82,14 @@@ CONFIG_PHY_VITESSE= CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y + CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 29584730e27,c2b3d189ec4..eca389480c5 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@@ -12,12 -13,8 +13,9 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -72,12 -68,11 +70,13 @@@ CONFIG_PHY_VITESSE= CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y + CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index d5ab0c04887,b853e2f56f6..42ae61c4f48 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@@ -14,12 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -75,10 -69,8 +71,10 @@@ CONFIG_ZYNQ_GEM= CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff010000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index f5a69db0fb4,a0bbc0fbde8..ebd9e289b06 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@@ -11,12 -10,8 +10,9 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -53,11 -46,8 +49,12 @@@ CONFIG_MISC= CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -71,9 -61,8 +68,11 @@@ CONFIG_PHY_VITESSE= CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y + CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y diff --cc configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 8f0ee31289a,0625d195c91..1427539fe96 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@@ -10,12 -11,8 +11,9 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -59,10 -55,9 +57,11 @@@ CONFIG_PHY_VITESSE= CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y + CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_zcu100_revC_defconfig index 8accb7f77c8,dc1e7cd8240..3616fbf6f2f --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@@ -12,12 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -83,5 -86,11 +88,9 @@@ CONFIG_USB_ULPI= CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_USB_ETHER=y + CONFIG_USB_ETH_CDC=y + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_ASIX=y -CONFIG_WDT=y -CONFIG_WDT_CDNS=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --cc configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 5448ff4f91e,e41366ecf7d..7013be0afd2 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@@ -3,27 -3,18 +3,21 @@@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_z CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xff000000 + CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y - CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0" - CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y - CONFIG_SPI_GENERIC=y - CONFIG_ZYNQ_I2C0=y - CONFIG_ZYNQ_I2C1=y - CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -50,11 -40,10 +43,11 @@@ CONFIG_CMD_USB= CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y - CONFIG_CMD_AES=y CONFIG_CMD_EXT4_WRITE=y - # CONFIG_SPL_ISO_PARTITION is not set ++CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y @@@ -74,13 -76,11 +80,15 @@@ CONFIG_MMC_SDHCI_ZYNQ= CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_MTD_UBI_BEB_LIMIT=0 CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y diff --cc configs/xilinx_zynqmp_zcu102_revA_defconfig index 17ec94577d2,02dd5ed2b78..e7d3f42317a --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@@ -3,27 -3,18 +3,21 @@@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_z CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xff000000 + CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y - CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA" - CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y - CONFIG_SPI_GENERIC=y - CONFIG_ZYNQ_I2C0=y - CONFIG_ZYNQ_I2C1=y - CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -74,8 -73,6 +77,9 @@@ CONFIG_MMC_SDHCI_ZYNQ= CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --cc configs/xilinx_zynqmp_zcu102_revB_defconfig index b2b029bed65,78deb6a967f..40146224ad4 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@@ -3,27 -3,18 +3,21 @@@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_z CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xff000000 + CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y - CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB" - CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y - CONFIG_SPI_GENERIC=y - CONFIG_ZYNQ_I2C0=y - CONFIG_ZYNQ_I2C1=y - CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y + CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -74,8 -73,6 +77,9 @@@ CONFIG_MMC_SDHCI_ZYNQ= CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --cc configs/xilinx_zynqmp_zcu104_revA_defconfig index 18c95915558,ff57ca8674e..48af3992334 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@@ -15,12 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -68,7 -59,6 +63,8 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -86,10 -77,8 +83,11 @@@ CONFIG_ZYNQ_GEM= CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/xilinx_zynqmp_zcu104_revC_defconfig index 1a7cadf473b,33258e41b20..fc22ea3b65b --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@@ -15,12 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -68,7 -59,6 +63,8 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -86,10 -77,8 +83,11 @@@ CONFIG_ZYNQ_GEM= CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/xilinx_zynqmp_zcu106_revA_defconfig index b725ed29a26,210c9a347fb..36f3b0a46e9 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@@ -3,27 -3,17 +3,20 @@@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_z CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xff000000 + CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y - CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106 revA" - CONFIG_ZYNQMP_QSPI=y CONFIG_ZYNQMP_USB=y - CONFIG_SPI_GENERIC=y - CONFIG_ZYNQ_I2C0=y - CONFIG_ZYNQ_I2C1=y - CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -75,7 -68,6 +74,8 @@@ CONFIG_DM_SPI_FLASH= CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -93,10 -86,8 +94,11 @@@ CONFIG_ZYNQ_GEM= CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/xilinx_zynqmp_zcu111_revA_defconfig index 7ae43ab5b58,8bace6d8088..45f1ad1f7bd --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@@ -16,12 -13,7 +13,8 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="earlycon clk_ignore_unused" +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y @@@ -64,10 -59,8 +62,11 @@@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x2 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_GENERIC=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@@ -85,10 -79,8 +85,11 @@@ CONFIG_ZYNQ_GEM= CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xff000000 - CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --cc configs/zynq_cc108_defconfig index 77bd803692b,c06e546e0a2..d5f3f530f4f --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@@ -23,7 -25,7 +25,8 @@@ CONFIG_CMD_USB= CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_FPGA_XILINX=y diff --cc configs/zynq_cse_nand_defconfig index 7c7e1430c60,44ad5bd69c3..e3dceaead3a --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@@ -2,12 -2,13 +2,16 @@@ CONFIG_ARM= CONFIG_SYS_CONFIG_NAME="zynq_cse" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x100000 + CONFIG_ENV_SIZE=0x190 + CONFIG_SPL=y CONFIG_SPL_STACK_R_ADDR=0x200000 - CONFIG_SYS_MALLOC_LEN=0x20000 - CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" + CONFIG_SYS_MALLOC_LEN=0x1000 + # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y CONFIG_SPL_STACK_R=y ++# CONFIG_CMDLINE_EDITING is not set ++# CONFIG_AUTO_COMPLETE is not set ++# CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@@ -36,11 -36,11 +39,11 @@@ # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set --# CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set # CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" ++# CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --cc configs/zynq_cse_nor_defconfig index 842d5206a7a,b4831f89a1a..331a2783817 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@@ -2,14 -2,14 +2,18 @@@ CONFIG_ARM= CONFIG_SYS_CONFIG_NAME="zynq_cse" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 + CONFIG_ENV_SIZE=0x190 + CONFIG_SPL=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SYS_MALLOC_LEN=0x1000 +CONFIG_ZYNQ_M29EW_WB_HACK=y - CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" CONFIG_BOOTDELAY=-1 + # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y CONFIG_SPL_STACK_R=y ++# CONFIG_CMDLINE_EDITING is not set ++# CONFIG_AUTO_COMPLETE is not set ++# CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@@ -37,11 -36,11 +40,11 @@@ # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set --# CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set # CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" ++# CONFIG_NET is not set # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --cc configs/zynq_cse_qspi_defconfig index 129afa89211,2e1e34d0aec..8db4ea95eab --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@@ -5,13 -9,17 +9,18 @@@ CONFIG_DEBUG_UART_CLOCK= CONFIG_SPL_STACK_R_ADDR=0x200000 # CONFIG_ZYNQ_DDRC_INIT is not set CONFIG_SYS_MALLOC_LEN=0x1000 - CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single" + # CONFIG_CMD_ZYNQ is not set CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=-1 -# CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y + # CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_SPL_STACK_R=y + CONFIG_SPL_SPI_LOAD=y ++# CONFIG_CMDLINE_EDITING is not set ++# CONFIG_AUTO_COMPLETE is not set ++# CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --cc configs/zynq_zc702_RSA_defconfig index 497f6b59e98,00000000000..b6568ee44d2 mode 100644,000000..100644 --- a/configs/zynq_zc702_RSA_defconfig +++ b/configs/zynq_zc702_RSA_defconfig @@@ -1,75 -1,0 +1,84 @@@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc70x" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x800 ++CONFIG_SPL=y ++CONFIG_DEBUG_UART_BASE=0xe0001000 ++CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_IDENT_STRING=" Xilinx Zynq ZC702" +CONFIG_SPL_STACK_R_ADDR=0x200000 - CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" ++CONFIG_CMD_ZYNQ_AES=y +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y ++CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_BOOTCOMMAND="run rsa_$modeboot || run distro_bootcmd" - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_OS_BOOT=y ++CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_PROMPT="Zynq> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_EEPROM=y ++CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y - CONFIG_CMD_ZYNQ_RSA=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y ++CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y ++CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y ++CONFIG_SYS_I2C_ZYNQ=y ++CONFIG_ZYNQ_I2C0=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_XILINX=y ++CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xe0001000 - CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03fd +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_THOR=y diff --cc configs/zynq_zc702_defconfig index 040f4248796,5223a9bc68d..ab5d6afc18c --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@@ -2,10 -2,11 +2,12 @@@ CONFIG_ARM= CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xe0001000 + CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_IDENT_STRING=" Xilinx Zynq ZC702" CONFIG_SPL_STACK_R_ADDR=0x200000 - CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@@ -35,7 -35,7 +37,8 @@@ CONFIG_CMD_USB= CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --cc configs/zynq_zc706_defconfig index 6a691cef35d,bcbfa65e41b..c89f374623b --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@@ -10,11 -12,14 +12,15 @@@ CONFIG_DISTRO_DEFAULTS= CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_PRINT=y + CONFIG_SPL_LOAD_FIT=y + CONFIG_IMAGE_FORMAT_LEGACY=y CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y ++CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y + CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y + CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_EEPROM=y @@@ -33,7 -38,7 +39,8 @@@ CONFIG_CMD_USB= CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y @@@ -72,3 -78,7 +81,5 @@@ CONFIG_USB_GADGET_VENDOR_NUM=0x03f CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_USB_FUNCTION_THOR=y -CONFIG_WDT=y -CONFIG_WDT_CDNS=y + CONFIG_SPL_GZIP=y diff --cc configs/zynq_zc706_eeprom_defconfig index 60d46767f00,00000000000..78441f349fb mode 100644,000000..100644 --- a/configs/zynq_zc706_eeprom_defconfig +++ b/configs/zynq_zc706_eeprom_defconfig @@@ -1,75 -1,0 +1,88 @@@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc70x" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x800 ++CONFIG_ENV_SIZE=0x400 ++CONFIG_SPL=y ++CONFIG_DEBUG_UART_BASE=0xe0001000 ++CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_IDENT_STRING=" Xilinx Zynq ZC706" +CONFIG_SPL_STACK_R_ADDR=0x200000 - CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_PRINT=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_SPL=y +CONFIG_SPL_STACK_R=y ++CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_SPL_OS_BOOT=y ++CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_PROMPT="Zynq> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_EEPROM=y - CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y ++CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_ENV_IS_IN_EEPROM=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y ++CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y ++CONFIG_SYS_I2C_ZYNQ=y ++CONFIG_ZYNQ_I2C0=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_XILINX=y ++CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y - CONFIG_DEBUG_UART_BASE=0xe0001000 - CONFIG_DEBUG_UART_CLOCK=50000000 ++CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03fd +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_THOR=y ++CONFIG_WDT=y ++CONFIG_WDT_CDNS=y ++CONFIG_SPL_GZIP=y diff --cc configs/zynq_zc770_xm010_defconfig index 57c984c8a13,fed1502d1b6..fc228c645a6 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@@ -1,10 -1,11 +1,12 @@@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x800 + CONFIG_SPL=y + CONFIG_DEBUG_UART_BASE=0xe0001000 + CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010" CONFIG_SPL_STACK_R_ADDR=0x200000 - CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@@ -28,7 -29,9 +30,10 @@@ CONFIG_CMD_SF= CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --cc configs/zynq_zc770_xm011_defconfig index 5165fc50a06,c15877d0ad9..ddf9cf26525 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@@ -25,14 -26,17 +26,18 @@@ CONFIG_CMD_GPIO= CONFIG_CMD_NAND_LOCK_UNLOCK=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_BLK=y CONFIG_FPGA_XILINX=y + CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set - CONFIG_DM_MMC=y + CONFIG_MTD_DEVICE=y CONFIG_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_DEBUG_UART_ZYNQ=y diff --cc configs/zynq_zc770_xm011_x16_defconfig index d53f223be42,60627da8e5b..e3c31cf6c3b --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@@ -25,14 -26,17 +26,18 @@@ CONFIG_CMD_GPIO= CONFIG_CMD_NAND_LOCK_UNLOCK=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set - # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011-x16" CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_BLK=y CONFIG_FPGA_XILINX=y + CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set - CONFIG_DM_MMC=y + CONFIG_MTD_DEVICE=y CONFIG_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_DEBUG_UART_ZYNQ=y diff --cc configs/zynq_zc770_xm012_defconfig index 6aac2f72cff,aa20971e441..47201282b72 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@@ -4,8 -5,7 +5,8 @@@ CONFIG_SPL= CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012" CONFIG_SPL_STACK_R_ADDR=0x200000 # CONFIG_SPL_FAT_SUPPORT is not set +CONFIG_ZYNQ_M29EW_WB_HACK=y - CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" + CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@@ -24,11 -22,10 +23,11 @@@ CONFIG_CMD_FPGA_LOADP= CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y - CONFIG_CMD_DHCP=y - CONFIG_CMD_MII=y - CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --cc configs/zynq_zc770_xm013_defconfig index 11338b88a49,a08bd299338..40c7fe928d1 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@@ -23,14 -23,15 +23,16 @@@ CONFIG_CMD_FPGA_LOADP= CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y - CONFIG_CMD_DHCP=y - CONFIG_CMD_MII=y - CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_BLK=y CONFIG_FPGA_XILINX=y + CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --cc configs/zynq_zed_defconfig index bba0a2d6dd8,c583c5c83b9..d98e405f4b3 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@@ -29,7 -31,7 +31,8 @@@ CONFIG_CMD_USB= CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --cc drivers/fpga/zynqpl.c index a4a6fd0a82d,499310d0c0b..ef0f251db26 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@@ -506,27 -504,15 +505,24 @@@ struct xilinx_fpga_op zynq_op = * Load the encrypted image from src addr and decrypt the image and * place it back the decrypted image into dstaddr. */ - int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, - u8 bstype, bool encrypt_part_flag) + int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen) { + u32 isr_status, ts; + - if ((srcaddr < SZ_1M) || (dstaddr < SZ_1M)) { + if (srcaddr < SZ_1M || dstaddr < SZ_1M) { printf("%s: src and dst addr should be > 1M\n", __func__); return FPGA_FAIL; } - if (encrypt_part_flag) { - /* Check AES engine is enabled */ - if (!(readl(&devcfg_base->ctrl) & - DEVCFG_CTRL_PCFG_AES_EN_MASK)) { - printf("%s: AES engine is not enabled\n", __func__); - return FPGA_FAIL; - } ++ /* Check AES engine is enabled */ ++ if (!(readl(&devcfg_base->ctrl) & ++ DEVCFG_CTRL_PCFG_AES_EN_MASK)) { ++ printf("%s: AES engine is not enabled\n", __func__); ++ return FPGA_FAIL; + } + - if (zynq_dma_xfer_init(bstype)) { + if (zynq_dma_xfer_init(BIT_NONE)) { printf("%s: zynq_dma_xfer_init FAIL\n", __func__); return FPGA_FAIL; } @@@ -545,126 -530,15 +540,29 @@@ * Flush destination address range only if image is not * bitstream. */ - if (bstype == BIT_NONE) - flush_dcache_range((u32)dstaddr, (u32)dstaddr + - roundup(dstlen << 2, ARCH_DMA_MINALIGN)); ++ if (dstaddr != 0xFFFFFFFF) + flush_dcache_range((u32)dstaddr, (u32)dstaddr + + roundup(dstlen << 2, ARCH_DMA_MINALIGN)); if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen)) return FPGA_FAIL; - if (bstype == BIT_FULL) { - isr_status = readl(&devcfg_base->int_sts); - /* Check FPGA configuration completion */ - ts = get_timer(0); - while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { - printf("%s: Timeout wait for FPGA to config\n", - __func__); - return FPGA_FAIL; - } - isr_status = readl(&devcfg_base->int_sts); - writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK), - &devcfg_base->ctrl); ++ isr_status = readl(&devcfg_base->int_sts); ++ /* Check FPGA configuration completion */ ++ ts = get_timer(0); ++ while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { ++ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { ++ printf("%s: Timeout wait for FPGA to config\n", ++ __func__); ++ return FPGA_FAIL; + } - - printf("%s: FPGA config done\n", __func__); - - if (bstype != BIT_PARTIAL) - zynq_slcr_devcfg_enable(); - } - - return FPGA_SUCCESS; - } - - - static int do_zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) - { - char *endp; - u32 srcaddr; - u32 srclen; - u32 dstaddr; - u32 dstlen; - u8 imgtype = BIT_NONE; - int status; - u8 i = 1; - - if (argc < 4 && argc > 5) - goto usage; - - if (argc == 4) { - if (!strcmp("load", argv[i])) - imgtype = BIT_FULL; - else if (!strcmp("loadp", argv[i])) - imgtype = BIT_PARTIAL; - else - goto usage; - i++; - } - - srcaddr = simple_strtoul(argv[i], &endp, 16); - if (*argv[i++] == 0 || *endp != 0) - goto usage; - srclen = simple_strtoul(argv[i], &endp, 16); - if (*argv[i++] == 0 || *endp != 0) - goto usage; - if (argc == 4) { - dstaddr = 0xFFFFFFFF; - dstlen = srclen; - } else { - dstaddr = simple_strtoul(argv[i], &endp, 16); - if (*argv[i++] == 0 || *endp != 0) - goto usage; - dstlen = simple_strtoul(argv[i], &endp, 16); - if (*argv[i++] == 0 || *endp != 0) - goto usage; - } - - /* - * If the image is not bitstream but destination address is - * 0xFFFFFFFF - */ - if (imgtype == BIT_NONE && dstaddr == 0xFFFFFFFF) { - printf("ERR:use zynqaes load/loadp encrypted bitstream\n"); - goto usage; ++ isr_status = readl(&devcfg_base->int_sts); + } + - /* - * Roundup source and destination lengths to - * word size - */ - if (srclen % 4) - srclen = roundup(srclen, 4); - if (dstlen % 4) - dstlen = roundup(dstlen, 4); - - status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2, - imgtype, true); - if (status != 0) - return -1; ++ printf("%s: FPGA config done\n", __func__); + - return 0; ++ zynq_slcr_devcfg_enable(); - usage: - return CMD_RET_USAGE; + return FPGA_SUCCESS; } - - #ifdef CONFIG_SYS_LONGHELP - static char zynqaes_help_text[] = - "zynqaes [operation type] -\n" - "Decrypts the encrypted image present in source address\n" - "and places the decrypted image at destination address\n" - "zynqaes operations:\n" - " zynqaes \n" - " zynqaes load \n" - " zynqaes loadp \n" - "if operation type is load or loadp, it loads the encrypted\n" - "full or partial bitstream on to PL respectively. If no valid\n" - "operation type specified then it loads decrypted image back\n" - "to memory and it doesnt support loading PL bistsream\n"; - #endif - - U_BOOT_CMD( - zynqaes, 5, 0, do_zynq_decrypt_image, - "Zynq AES decryption ", zynqaes_help_text - ); - #endif diff --cc drivers/mmc/zynq_sdhci.c index c8667de1b3e,b05334dfc8d..e105ad5f659 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@@ -21,34 -17,6 +17,29 @@@ DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ - # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 - #endif - +#define SDHCI_ITAPDLYSEL_SD_HSD 0x00000015 +#define SDHCI_ITAPDLYSEL_SDR25 0x00000015 +#define SDHCI_ITAPDLYSEL_SDR50 0x00000000 +#define SDHCI_ITAPDLYSEL_SDR104_B2 0x00000000 +#define SDHCI_ITAPDLYSEL_SDR104_B0 0x00000000 +#define SDHCI_ITAPDLYSEL_MMC_HSD 0x00000015 +#define SDHCI_ITAPDLYSEL_SD_DDR50 0x0000003D +#define SDHCI_ITAPDLYSEL_MMC_DDR52 0x00000012 +#define SDHCI_ITAPDLYSEL_MMC_HS200_B2 0x00000000 +#define SDHCI_ITAPDLYSEL_MMC_HS200_B0 0x00000000 +#define SDHCI_OTAPDLYSEL_SD_HSD 0x00000005 +#define SDHCI_OTAPDLYSEL_SDR25 0x00000005 +#define SDHCI_OTAPDLYSEL_SDR50 0x00000003 +#define SDHCI_OTAPDLYSEL_SDR104_B0 0x00000003 +#define SDHCI_OTAPDLYSEL_SDR104_B2 0x00000002 +#define SDHCI_OTAPDLYSEL_MMC_HSD 0x00000006 +#define SDHCI_OTAPDLYSEL_SD_DDR50 0x00000004 +#define SDHCI_OTAPDLYSEL_MMC_DDR52 0x00000006 +#define SDHCI_OTAPDLYSEL_MMC_HS200_B0 0x00000003 +#define SDHCI_OTAPDLYSEL_MMC_HS200_B2 0x00000002 + +#define MMC_BANK2 0x2 + struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; @@@ -178,199 -168,62 +193,241 @@@ static void arasan_sdhci_set_tapdelay(s struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); struct mmc *mmc = (struct mmc *)host->mmc; u8 uhsmode; + u32 itap_delay; + u32 otap_delay; - if (mmc->is_uhs) - uhsmode = mmc->uhsmode; - else if (mmc->card_caps & MMC_MODE_HS) - uhsmode = MMC_TIMING_HS; - else if (mmc->card_caps & MMC_MODE_HS200) - uhsmode = MMC_TIMING_HS200; - else - return; + uhsmode = mode2timing[mmc->selected_mode]; - if (uhsmode >= UHS_SDR25_BUS_SPEED) - arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode, - priv->bank); + debug("%s, host:%s devId:%d, bank:%d, mode:%d\n", __func__, host->name, + priv->deviceid, priv->bank, uhsmode); + if ((uhsmode >= MMC_TIMING_UHS_SDR25) && + (uhsmode <= MMC_TIMING_HS200)) { + itap_delay = priv->itapdly[uhsmode]; + otap_delay = priv->otapdly[uhsmode]; + arasan_zynqmp_set_tapdelay(priv->deviceid, itap_delay, + otap_delay); + } +} + +/** + * arasan_zynqmp_dt_parse_tap_delays - Read Tap Delay values from DT + * + * Called at initialization to parse the values of Tap Delays. + * + * @dev: Pointer to our struct udevice. + */ +static void arasan_zynqmp_dt_parse_tap_delays(struct udevice *dev) +{ + struct arasan_sdhci_priv *priv = dev_get_priv(dev); + u32 *itapdly = priv->itapdly; + u32 *otapdly = priv->otapdly; + int ret; + + /* + * Read Tap Delay values from DT, if the DT does not contain the + * Tap Values then use the pre-defined values + */ + ret = dev_read_u32(dev, "xlnx,itap-delay-sd-hsd", + &itapdly[SD_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for SD_HS_BUS_SPEED\n"); + itapdly[SD_HS_BUS_SPEED] = SDHCI_ITAPDLYSEL_SD_HSD; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sd-hsd", + &otapdly[SD_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for SD_HS_BUS_SPEED\n"); + otapdly[SD_HS_BUS_SPEED] = SDHCI_OTAPDLYSEL_SD_HSD; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sdr25", + &itapdly[MMC_TIMING_UHS_SDR25]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_TIMING_UHS_SDR25\n"); + itapdly[MMC_TIMING_UHS_SDR25] = SDHCI_ITAPDLYSEL_SDR25; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sdr25", + &otapdly[MMC_TIMING_UHS_SDR25]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_TIMING_UHS_SDR25\n"); + otapdly[MMC_TIMING_UHS_SDR25] = SDHCI_OTAPDLYSEL_SDR25; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sdr50", + &itapdly[MMC_TIMING_UHS_SDR50]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_TIMING_UHS_SDR50\n"); + itapdly[MMC_TIMING_UHS_SDR50] = SDHCI_ITAPDLYSEL_SDR50; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sdr50", + &otapdly[MMC_TIMING_UHS_SDR50]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_TIMING_UHS_SDR50\n"); + otapdly[MMC_TIMING_UHS_SDR50] = SDHCI_OTAPDLYSEL_SDR50; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sd-ddr50", + &itapdly[MMC_TIMING_UHS_DDR50]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_TIMING_UHS_DDR50\n"); + itapdly[MMC_TIMING_UHS_DDR50] = SDHCI_ITAPDLYSEL_SD_DDR50; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sd-ddr50", + &otapdly[MMC_TIMING_UHS_DDR50]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_TIMING_UHS_DDR50\n"); + otapdly[MMC_TIMING_UHS_DDR50] = SDHCI_OTAPDLYSEL_SD_DDR50; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-mmc-hsd", + &itapdly[MMC_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_HS_BUS_SPEED\n"); + itapdly[MMC_HS_BUS_SPEED] = SDHCI_ITAPDLYSEL_MMC_HSD; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-mmc-hsd", + &otapdly[MMC_HS_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_HS_BUS_SPEED\n"); + otapdly[MMC_HS_BUS_SPEED] = SDHCI_OTAPDLYSEL_MMC_HSD; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-mmc-ddr52", + &itapdly[MMC_DDR52_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_DDR52_BUS_SPEED\n"); + itapdly[MMC_DDR52_BUS_SPEED] = SDHCI_ITAPDLYSEL_MMC_DDR52; + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-mmc-ddr52", + &otapdly[MMC_DDR52_BUS_SPEED]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_DDR52_BUS_SPEED\n"); + otapdly[MMC_DDR52_BUS_SPEED] = SDHCI_OTAPDLYSEL_MMC_DDR52; + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-sdr104", + &itapdly[MMC_TIMING_UHS_SDR104]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_TIMING_UHS_SDR104\n"); + if (priv->bank == MMC_BANK2) { + itapdly[MMC_TIMING_UHS_SDR104] = + SDHCI_ITAPDLYSEL_SDR104_B2; + } else { + itapdly[MMC_TIMING_UHS_SDR104] = + SDHCI_ITAPDLYSEL_SDR104_B0; + } + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-sdr104", + &otapdly[MMC_TIMING_UHS_SDR104]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_TIMING_UHS_SDR104\n"); + if (priv->bank == MMC_BANK2) { + otapdly[MMC_TIMING_UHS_SDR104] = + SDHCI_OTAPDLYSEL_SDR104_B2; + } else { + otapdly[MMC_TIMING_UHS_SDR104] = + SDHCI_OTAPDLYSEL_SDR104_B0; + } + } + + ret = dev_read_u32(dev, "xlnx,itap-delay-mmc-hs200", + &itapdly[MMC_TIMING_HS200]); + if (ret) { + dev_dbg(dev, + "Using predefined itapdly for MMC_TIMING_HS200\n"); + if (priv->bank == MMC_BANK2) { + itapdly[MMC_TIMING_HS200] = + SDHCI_ITAPDLYSEL_MMC_HS200_B2; + } else { + itapdly[MMC_TIMING_HS200] = + SDHCI_ITAPDLYSEL_MMC_HS200_B0; + } + } + + ret = dev_read_u32(dev, "xlnx,otap-delay-mmc-hs200", + &otapdly[MMC_TIMING_HS200]); + if (ret) { + dev_dbg(dev, + "Using predefined otapdly for MMC_TIMING_HS200\n"); + if (priv->bank == MMC_BANK2) { + otapdly[MMC_TIMING_HS200] = + SDHCI_OTAPDLYSEL_MMC_HS200_B2; + } else { + otapdly[MMC_TIMING_HS200] = + SDHCI_OTAPDLYSEL_MMC_HS200_B0; + } + } } + + static void arasan_sdhci_set_control_reg(struct sdhci_host *host) + { + struct mmc *mmc = (struct mmc *)host->mmc; + u32 reg; + + if (!IS_SD(mmc)) + return; + + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + reg = sdhci_readw(host, SDHCI_HOST_CTRL2); + reg |= SDHCI_18V_SIGNAL; + sdhci_writew(host, reg, SDHCI_HOST_CTRL2); + } + + if (mmc->selected_mode > SD_HS && + mmc->selected_mode <= UHS_DDR50) { + reg = sdhci_readw(host, SDHCI_HOST_CTRL2); + reg &= ~SDHCI_CTRL2_MODE_MASK; + switch (mmc->selected_mode) { + case UHS_SDR12: + reg |= UHS_SDR12_BUS_SPEED; + break; + case UHS_SDR25: + reg |= UHS_SDR25_BUS_SPEED; + break; + case UHS_SDR50: + reg |= UHS_SDR50_BUS_SPEED; + break; + case UHS_SDR104: + reg |= UHS_SDR104_BUS_SPEED; + break; + case UHS_DDR50: + reg |= UHS_DDR50_BUS_SPEED; + break; + default: + break; + } + sdhci_writew(host, reg, SDHCI_HOST_CTRL2); + } + } + #endif + + #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) + const struct sdhci_ops arasan_ops = { + .platform_execute_tuning = &arasan_sdhci_execute_tuning, + .set_delay = &arasan_sdhci_set_tapdelay, + .set_control_reg = &arasan_sdhci_set_control_reg, + }; #endif static int arasan_sdhci_probe(struct udevice *dev) @@@ -454,29 -292,21 +496,25 @@@ static int arasan_sdhci_ofdata_to_platd return -1; priv->host->name = dev->name; - priv->host->ioaddr = (void *)devfdt_get_addr(dev); - plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ); + #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) + priv->host->ops = &arasan_ops; + #endif - priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "xlnx,device_id", -1); - priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "xlnx,mio_bank", -1); + priv->host->ioaddr = (void *)dev_read_addr(dev); + if (IS_ERR(priv->host->ioaddr)) + return PTR_ERR(priv->host->ioaddr); - if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "no-1-8-v", NULL) - #if defined(CONFIG_ARCH_ZYNQMP) - || (chip_id(VERSION) == ZYNQMP_SILICON_V1) - #endif - ) - priv->no_1p8 = 1; - else - priv->no_1p8 = 0; + priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); + priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); + priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); - if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "mmc-pwrseq", - NULL)) - priv->pwrseq = true; ++#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) ++ arasan_zynqmp_dt_parse_tap_delays(dev); ++#endif + + plat->f_max = dev_read_u32_default(dev, "max-frequency", + CONFIG_ZYNQ_SDHCI_MAX_FREQ); return 0; } diff --cc drivers/mtd/spi/Kconfig index d8f93379628,76d5a1d1152..860a802fa28 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@@ -49,12 -49,6 +49,12 @@@ config SF_DUAL_FLAS Enable this option to support two flash memories connected to a single controller. Currently Xilinx Zynq qspi supports this. +config SPI_GENERIC + bool "SPI flash support" - depends on ARCH_ZYNQMP ++ depends on ARCH_ZYNQMP || ARCH_VERSAL + help + Enable the generic SPI flash controller support. + if SPI_FLASH config SPI_FLASH_ATMEL diff --cc drivers/mtd/spi/spi_flash.c index cba61da744a,a87bacd4ac7..9070ff3f733 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@@ -19,21 -20,12 +20,19 @@@ #include "sf_internal.h" - DECLARE_GLOBAL_DATA_PTR; - -static void spi_flash_addr(u32 addr, u8 *cmd) +static void spi_flash_addr(u32 addr, u8 *cmd, u8 four_byte) { /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; + if (four_byte) { + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; + } else { + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; + } } static int read_sr(struct spi_flash *flash, u8 *rs) @@@ -170,16 -128,9 +169,17 @@@ static int clean_bar(struct spi_flash * if (flash->bank_curr == 0) return 0; cmd = flash->bank_write_cmd; + flash->bank_curr = 0; - return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); + ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); + if (ret) { + debug("SF: fail to write bank register\n"); + return ret; + } + + flash->bank_curr = bank_sel; + + return ret; } static int write_bar(struct spi_flash *flash, u32 offset) @@@ -649,35 -468,10 +649,35 @@@ int spi_flash_cmd_read_ops(struct spi_f size_t len, void *data) { struct spi_slave *spi = flash->spi; - u8 *cmd, cmdsz; + u8 cmdsz; u32 remain_len, read_len, read_addr; int bank_sel = 0; - int ret = -1; + int ret = 0; +#if defined(CONFIG_SF_DUAL_FLASH) || defined(CONFIG_SPI_FLASH_BAR) + u32 bank_addr; +#endif + +#ifdef CONFIG_SF_DUAL_FLASH + u8 moveoffs = 0; + void *tempbuf = NULL; + size_t length = len; +#endif + +#ifdef CONFIG_SF_DUAL_FLASH + /* + * Incase of dual parallel, if odd offset is received + * decrease it by 1 and read extra byte, otherwise + * any read with odd offset fails + */ + if (flash->dual_flash == SF_DUAL_PARALLEL_FLASH) { + if (offset & 1) { + offset -= 1; + len += 1; + moveoffs = 1; + tempbuf = data; + } + } +#endif /* Handle memory-mapped SPI */ if (flash->memory_map) { @@@ -694,17 -488,7 +694,13 @@@ } cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + + spi->dummy_bytes = flash->dummy_byte; + + if (flash->spi->bytemode == SPI_4BYTE_MODE) + cmdsz += 1; + - cmd = calloc(1, cmdsz); - if (!cmd) { - debug("SF: Failed to allocate cmd\n"); - return -ENOMEM; - } + u8 cmd[cmdsz]; cmd[0] = flash->read_cmd; while (len) { @@@ -716,43 -497,25 +712,46 @@@ #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash > SF_SINGLE_FLASH) spi_flash_dual(flash, &read_addr); + if (flash->dual_flash == SF_DUAL_STACKED_FLASH) + bank_addr = read_addr; #endif + + if (flash->spi->bytemode != SPI_4BYTE_MODE) { #ifdef CONFIG_SPI_FLASH_BAR - ret = write_bar(flash, read_addr); - if (ret < 0) - return log_ret(ret); - bank_sel = flash->bank_curr; + bank_sel = write_bar(flash, bank_addr); + if (bank_sel < 0) - return ret; ++ return log_ret(ret); + if ((flash->dual_flash == SF_DUAL_STACKED_FLASH) && + (flash->spi->flags & SPI_XFER_U_PAGE)) + bank_sel += (flash->size >> 1)/ + SPI_FLASH_16MB_BOUN; #endif - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * - (bank_sel + 1)) - offset; - if (len < remain_len) - read_len = len; - else - read_len = remain_len; + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; + if (len < remain_len) + read_len = len; + else + read_len = remain_len; + } else { + if (len > (SPI_FLASH_16MB_BOUN << flash->shift)) + read_len = SPI_FLASH_16MB_BOUN << flash->shift; + else + read_len = len; + } + if (spi->max_read_size) + read_len = min(read_len, spi->max_read_size); + - spi_flash_addr(read_addr, cmd); + if (flash->spi->bytemode == SPI_4BYTE_MODE) + spi_flash_addr(read_addr, cmd, 1); + else + spi_flash_addr(read_addr, cmd, 0); + debug("%s: Byte Mode:0x%x\n", __func__, flash->spi->bytemode); +#ifdef CONFIG_SPI_GENERIC + if (flash->dual_flash == SF_DUAL_PARALLEL_FLASH) + flash->spi->flags |= SPI_XFER_STRIPE; +#endif ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { debug("SF: read failed\n"); @@@ -764,25 -527,11 +763,24 @@@ data += read_len; } +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash == SF_DUAL_PARALLEL_FLASH) { + if (moveoffs) { + data = tempbuf + 1; + memcpy(tempbuf, data, length); + } + } +#endif + + spi->dummy_bytes = 0; + + if (flash->spi->bytemode != SPI_4BYTE_MODE) { #ifdef CONFIG_SPI_FLASH_BAR - ret = clean_bar(flash); + ret = clean_bar(flash); #endif + } - free(cmd); - return ret; + return log_ret(ret); } #ifdef CONFIG_SPI_FLASH_SST diff --cc drivers/mtd/spi/spi_flash_ids.c index 66b6c204543,ad0a0c81501..c8a4f755099 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@@ -68,17 -69,13 +69,20 @@@ const struct spi_flash_info spi_flash_i #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ {"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) }, - {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, + {"is25lp008d", INFO(0x9d6014, 0x0, 64 * 1024, 16, RD_QUAD) }, + {"is25wp008d", INFO(0x9d7014, 0x0, 64 * 1024, 16, RD_QUAD) }, + {"is25lp016d", INFO(0x9d6015, 0x0, 64 * 1024, 32, RD_QUAD) }, + {"is25wp016d", INFO(0x9d7015, 0x0, 64 * 1024, 32, RD_QUAD) }, + {"is25lp032d", INFO(0x9d6016, 0x0, 64 * 1024, 64, RD_QUAD) }, + {"is25wp032d", INFO(0x9d7016, 0x0, 64 * 1024, 64, RD_QUAD) }, {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, + {"is25wp064d", INFO(0x9d7017, 0x0, 64 * 1024, 128, RD_QUAD) }, {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, - {"is25lp256", INFO(0x9d6019, 0x0, 64 * 1024, 512, 0) }, + {"is25lp256d", INFO(0x9d6019, 0x0, 64 * 1024, 512, RD_QUAD) }, + {"is25wp032", INFO(0x9d7016, 0x0, 64 * 1024, 64, RD_FULL | SECT_4K) }, + {"is25wp064", INFO(0x9d7017, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, + {"is25wp128", INFO(0x9d7018, 0x0, 64 * 1024, 256, RD_FULL | SECT_4K) }, + {"is25wp256d", INFO(0x9d7019, 0x0, 64 * 1024, 512, RD_QUAD) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, @@@ -90,22 -87,21 +94,25 @@@ {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {"mx25l1633e", INFO(0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, {"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {"mx25u12835f", INFO(0xc22538, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, + {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + {"mx66u1g45g", INFO(0xc2253b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, + {"s25fl064l", INFO(0x016017, 0x0, 64 * 1024, 128, 0) }, - {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 128, 0) }, + {"s25fl208k", INFO(0x014014, 0x0, 64 * 1024, 16, 0) }, + {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) }, {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, diff --cc drivers/net/phy/phy.c index 01c40c43bf5,e837eb7688c..004a932e78e --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@@ -917,30 -900,8 +938,30 @@@ static struct phy_device *phy_connect_f } sn = fdt_next_subnode(gd->fdt_blob, sn); } + + return phydev; +} +#endif + +#ifdef CONFIG_DM_ETH +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct udevice *dev, phy_interface_t interface) +#else +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, + phy_interface_t interface) #endif +{ + struct phy_device *phydev = NULL; + +#ifdef CONFIG_PHY_FIXED + phydev = phy_connect_fixed(bus, dev, interface); +#endif +#ifdef CONFIG_PHY_XILINX_GMII2RGMII + phydev = phy_connect_gmii2rgmii(bus, dev, interface); +#endif + - if (phydev == NULL) + if (!phydev) phydev = phy_find_by_mask(bus, 1 << addr, interface); if (phydev) diff --cc drivers/net/zynq_gem.c index d2e251a789b,bc33126536c..9bd79b198a2 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@@ -203,10 -183,9 +202,10 @@@ struct zynq_gem_priv struct clk clk; u32 max_speed; bool int_pcs; + bool dma_64bit; }; - static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, + static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u32 op, u16 *data) { u32 mgtcr; diff --cc drivers/spi/xilinx_spi.c index c66004a8276,2b5f2cf5483..08f3c20e187 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@@ -20,9 -19,8 +19,10 @@@ #include #include #include + #include +DECLARE_GLOBAL_DATA_PTR; + /* * [0]: http://www.xilinx.com/support/documentation * @@@ -80,11 -78,8 +80,13 @@@ #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) #endif + #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */ + +#define XILINX_SPI_QUAD_MODE 2 + +#define XILINX_SPI_QUAD_EXTRA_DUMMY 3 +#define SPI_QUAD_OUT_FAST_READ 0x6B + /* xilinx spi register set */ struct xilinx_spi_regs { u32 __space0__[7]; @@@ -152,12 -136,8 +154,11 @@@ static void spi_cs_deactivate(struct ud struct udevice *bus = dev_get_parent(dev); struct xilinx_spi_priv *priv = dev_get_priv(bus); struct xilinx_spi_regs *regs = priv->regs; + u32 reg; + reg = readl(®s->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST; + writel(reg, ®s->spicr); writel(SPISSR_OFF, ®s->spissr); - } static int xilinx_spi_claim_bus(struct udevice *dev) diff --cc drivers/spi/zynq_qspi.c index f73394b3d91,9ad1927a5d5..50c995d481a --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@@ -1,9 -1,9 +1,8 @@@ + // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013 Xilinx, Inc. - * (C) Copyright 2015 Jagan Teki + * (C) Copyright 2011 - 2013 Xilinx * * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) - * - * SPDX-License-Identifier: GPL-2.0+ */ #include diff --cc drivers/spi/zynqmp_gqspi.c index cf407763b8a,75459d156ec..b093b8962ce --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@@ -1,36 -1,28 +1,28 @@@ + // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 - 2015 Xilinx - * (C) Copyright 2018 Xilinx ++ * (C) Copyright 2014 - 2018 Xilinx * - * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only) - * - * SPDX-License-Identifier: GPL-2.0 + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) */ #include -#include + #include + #include + #include + #include -#include #include #include - #include #include +#include - #include - #include - #include - #include + #include + #include +#include "../mtd/spi/sf_internal.h" - #include - - DECLARE_GLOBAL_DATA_PTR; - - #define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK (1 << 29) - #define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK (3 << 30) - #define ZYNQMP_QSPI_CONFIG_DMA_MODE (2 << 30) - #define ZYNQMP_QSPI_CONFIG_CPHA_MASK (1 << 2) - #define ZYNQMP_QSPI_CONFIG_CPOL_MASK (1 << 1) - /* QSPI MIO's count for different connection topologies */ - #define ZYNQMP_QSPI_MIO_NUM_QSPI0 6 - #define ZYNQMP_QSPI_MIO_NUM_QSPI1 5 - #define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1 + #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) + #define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) + #define GQSPI_CONFIG_DMA_MODE (2 << 30) + #define GQSPI_CONFIG_CPHA_MASK BIT(2) + #define GQSPI_CONFIG_CPOL_MASK BIT(1) /* * QSPI Interrupt Registers bit Masks @@@ -38,64 -30,79 +30,88 @@@ * All the four interrupt registers (Status/Mask/Enable/Disable) have the same * bit definitions. */ - #define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */ - #define ZYNQMP_QSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */ - #define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */ - #define ZYNQMP_QSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */ - #define ZYNQMP_QSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */ - #define ZYNQMP_QSPI_IXR_ALL_MASK (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \ - ZYNQMP_QSPI_IXR_RXNEMTY_MASK) + #define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */ + #define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */ + #define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */ + #define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */ ++#define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */ + #define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ + GQSPI_IXR_RXNEMTY_MASK) /* * QSPI Enable Register bit Masks * * This register is used to enable or disable the QSPI controller */ - #define ZYNQMP_QSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */ - - #define ZYNQMP_QSPI_GFIFO_LOW_BUS (1 << 14) - #define ZYNQMP_QSPI_GFIFO_CS_LOWER (1 << 12) - #define ZYNQMP_QSPI_GFIFO_UP_BUS (1 << 15) - #define ZYNQMP_QSPI_GFIFO_CS_UPPER (1 << 13) - #define ZYNQMP_QSPI_SPI_MODE_QSPI (3 << 10) - #define ZYNQMP_QSPI_SPI_MODE_SPI (1 << 10) - #define ZYNQMP_QSPI_SPI_MODE_DUAL_SPI (2 << 10) - #define ZYNQMP_QSPI_IMD_DATA_CS_ASSERT 5 - #define ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT 5 - #define ZYNQMP_QSPI_GFIFO_TX (1 << 16) - #define ZYNQMP_QSPI_GFIFO_RX (1 << 17) - #define ZYNQMP_QSPI_GFIFO_STRIPE_MASK (1 << 18) - #define ZYNQMP_QSPI_GFIFO_IMD_MASK 0xFF - #define ZYNQMP_QSPI_GFIFO_EXP_MASK (1 << 9) - #define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK (1 << 8) - #define ZYNQMP_QSPI_STRT_GEN_FIFO (1 << 28) - #define ZYNQMP_QSPI_GEN_FIFO_STRT_MOD (1 << 29) - #define ZYNQMP_QSPI_GFIFO_WP_HOLD (1 << 19) - #define ZYNQMP_QSPI_BAUD_DIV_MASK (7 << 3) - #define ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV (1 << 3) - #define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE - #define ZYNQMP_QSPI_DMA_DST_I_STS_DONE (1 << 1) - #define ZYNQMP_QSPI_DMA_DST_I_STS_MASK 0xFE - #define MODEBITS 0x6 + #define GQSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */ + + #define GQSPI_GFIFO_LOW_BUS BIT(14) + #define GQSPI_GFIFO_CS_LOWER BIT(12) + #define GQSPI_GFIFO_UP_BUS BIT(15) + #define GQSPI_GFIFO_CS_UPPER BIT(13) + #define GQSPI_SPI_MODE_QSPI (3 << 10) + #define GQSPI_SPI_MODE_SPI BIT(10) + #define GQSPI_SPI_MODE_DUAL_SPI (2 << 10) + #define GQSPI_IMD_DATA_CS_ASSERT 5 + #define GQSPI_IMD_DATA_CS_DEASSERT 5 + #define GQSPI_GFIFO_TX BIT(16) + #define GQSPI_GFIFO_RX BIT(17) + #define GQSPI_GFIFO_STRIPE_MASK BIT(18) + #define GQSPI_GFIFO_IMD_MASK 0xFF + #define GQSPI_GFIFO_EXP_MASK BIT(9) + #define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) + #define GQSPI_STRT_GEN_FIFO BIT(28) + #define GQSPI_GEN_FIFO_STRT_MOD BIT(29) + #define GQSPI_GFIFO_WP_HOLD BIT(19) + #define GQSPI_BAUD_DIV_MASK (7 << 3) + #define GQSPI_DFLT_BAUD_RATE_DIV BIT(3) + #define GQSPI_GFIFO_ALL_INT_MASK 0xFBE + #define GQSPI_DMA_DST_I_STS_DONE BIT(1) + #define GQSPI_DMA_DST_I_STS_MASK 0xFE + #define MODEBITS 0x6 +#define QUAD_OUT_READ_CMD 0x6B +#define QUAD_PAGE_PROGRAM_CMD 0x32 +#define DUAL_OUTPUT_FASTRD_CMD 0x3B + - #define ZYNQMP_QSPI_GFIFO_SELECT (1 << 0) + #define GQSPI_GFIFO_SELECT BIT(0) + - #define ZYNQMP_QSPI_FIFO_THRESHOLD 1 - #define ZYNQMP_QSPI_GENFIFO_THRESHOLD 31 + #define GQSPI_FIFO_THRESHOLD 1 ++#define GQSPI_GENFIFO_THRESHOLD 31 - #define SPI_XFER_ON_BOTH 0 - #define SPI_XFER_ON_LOWER 1 - #define SPI_XFER_ON_UPPER 2 + #define SPI_XFER_ON_BOTH 0 + #define SPI_XFER_ON_LOWER 1 + #define SPI_XFER_ON_UPPER 2 - #define ZYNQMP_QSPI_DMA_ALIGN 0x4 - #define ZYNQMP_QSPI_MAX_BAUD_RATE_VAL 7 - #define ZYNQMP_QSPI_DFLT_BAUD_RATE_VAL 2 + #define GQSPI_DMA_ALIGN 0x4 + #define GQSPI_MAX_BAUD_RATE_VAL 7 + #define GQSPI_DFLT_BAUD_RATE_VAL 2 + + #define GQSPI_TIMEOUT 100000000 + ++#if !defined(CONFIG_ARCH_VERSAL) + #define GQSPI_BAUD_DIV_SHIFT 2 + #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 + #define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 + #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 + #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 + #define GQSPI_USE_DATA_DLY 0x1 + #define GQSPI_USE_DATA_DLY_SHIFT 31 + #define GQSPI_DATA_DLY_ADJ_VALUE 0x2 + #define GQSPI_DATA_DLY_ADJ_SHIFT 28 + #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 + #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 + #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 + #define IOU_TAPDLY_BYPASS_OFST 0xFF180390 + #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 + #define GQSPI_FREQ_40MHZ 40000000 + #define GQSPI_FREQ_100MHZ 100000000 + #define GQSPI_FREQ_150MHZ 150000000 + #define IOU_TAPDLY_BYPASS_MASK 0x7 ++#endif - #define ZYNQMP_QSPI_TIMEOUT 100000000 + #define GQSPI_REG_OFFSET 0x100 + #define GQSPI_DMA_REG_OFFSET 0x800 /* QSPI register offsets */ struct zynqmp_qspi_regs { @@@ -148,9 -157,6 +166,8 @@@ struct zynqmp_qspi_platdata struct zynqmp_qspi_dma_regs *dma_regs; u32 frequency; u32 speed_hz; + unsigned int is_dual; - unsigned int tx_rx_mode; + unsigned int io_mode; }; struct zynqmp_qspi_priv { @@@ -163,106 -168,20 +179,45 @@@ int bytes_to_transfer; int bytes_to_receive; unsigned int is_inst; + unsigned int is_dual; + unsigned int u_page; + unsigned int bus; + unsigned int stripe; - unsigned cs_change:1; + unsigned int cs_change:1; + unsigned int dummy_bytes; + unsigned int tx_rx_mode; + unsigned int io_mode; }; +static u8 last_cmd; + static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus) { struct zynqmp_qspi_platdata *plat = bus->platdata; + int is_dual; - u32 mode = 0; - int offset; - u32 value; - int ret; - struct clk clk; - unsigned long clock; debug("%s\n", __func__); - plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) + 0x100); - plat->dma_regs = (struct zynqmp_qspi_dma_regs *)(devfdt_get_addr(bus) + - 0x800); - - ret = clk_get_by_index(bus, 0, &clk); - if (ret < 0) { - dev_err(dev, "failed to get clock\n"); - return ret; - } - - clock = clk_get_rate(&clk); - if (IS_ERR_VALUE(clock)) { - dev_err(dev, "failed to get rate\n"); - return clock; - } - debug("%s: CLK %ld\n", __func__, clock); - - ret = clk_enable(&clk); - if (ret && ret != -ENOSYS) { - dev_err(dev, "failed to enable clock\n"); - return ret; - } + plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) + + GQSPI_REG_OFFSET); + plat->dma_regs = (struct zynqmp_qspi_dma_regs *) + (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET); + is_dual = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "is-dual", -1); + if (is_dual < 0) + plat->is_dual = SF_SINGLE_FLASH; + else if (is_dual == 1) + plat->is_dual = SF_DUAL_PARALLEL_FLASH; + else + if (fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), + "is-stacked", -1) < 0) + plat->is_dual = SF_SINGLE_FLASH; + else + plat->is_dual = SF_DUAL_STACKED_FLASH; + + plat->io_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(bus), + "has-io-mode"); + - offset = fdt_first_subnode(gd->fdt_blob, dev_of_offset(bus)); - - value = fdtdec_get_uint(gd->fdt_blob, offset, "spi-rx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_RX_DUAL; - break; - case 4: - mode |= SPI_RX_QUAD; - break; - default: - printf("Invalid spi-rx-bus-width %d\n", value); - break; - } - - value = dev_read_u32_default(bus, "spi-tx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_TX_DUAL; - break; - case 4: - mode |= SPI_TX_QUAD; - break; - default: - printf("Invalid spi-tx-bus-width %d\n", value); - break; - } - - plat->tx_rx_mode = mode; - - plat->frequency = clock; - plat->speed_hz = plat->frequency; - return 0; } @@@ -271,58 -190,30 +226,58 @@@ static void zynqmp_qspi_init_hw(struct u32 config_reg; struct zynqmp_qspi_regs *regs = priv->regs; - writel(ZYNQMP_QSPI_GFIFO_SELECT, ®s->gqspisel); - writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, ®s->idisr); - writel(ZYNQMP_QSPI_FIFO_THRESHOLD, ®s->txftr); - writel(ZYNQMP_QSPI_FIFO_THRESHOLD, ®s->rxftr); - writel(ZYNQMP_QSPI_GENFIFO_THRESHOLD, ®s->gqfthr); - writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, ®s->isr); + writel(GQSPI_GFIFO_SELECT, ®s->gqspisel); + writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr); + writel(GQSPI_FIFO_THRESHOLD, ®s->txftr); + writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr); ++ writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr); + writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr); + writel(0x0, ®s->enbr); config_reg = readl(®s->confr); - config_reg &= ~(ZYNQMP_QSPI_CONFIG_MODE_EN_MASK); - config_reg |= ZYNQMP_QSPI_GFIFO_WP_HOLD | - ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV; - config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK | - GQSPI_CONFIG_MODE_EN_MASK); - config_reg |= GQSPI_CONFIG_DMA_MODE | - GQSPI_GFIFO_WP_HOLD | ++ config_reg &= ~(GQSPI_CONFIG_MODE_EN_MASK); ++ config_reg |= GQSPI_GFIFO_WP_HOLD | + GQSPI_DFLT_BAUD_RATE_DIV; + if (priv->io_mode) { - config_reg |= ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK; ++ config_reg |= GQSPI_GFIFO_STRT_MODE_MASK; + } else { - config_reg &= ~(ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK); - config_reg |= ZYNQMP_QSPI_CONFIG_DMA_MODE; ++ config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK); ++ config_reg |= GQSPI_CONFIG_DMA_MODE; + } + writel(config_reg, ®s->confr); - writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr); + writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); } static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) { u32 gqspi_fifo_reg = 0; - gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | - GQSPI_GFIFO_CS_LOWER; - + if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) { + if (priv->bus == SPI_XFER_ON_BOTH) - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS | - ZYNQMP_QSPI_GFIFO_UP_BUS | - ZYNQMP_QSPI_GFIFO_CS_UPPER | - ZYNQMP_QSPI_GFIFO_CS_LOWER; ++ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | ++ GQSPI_GFIFO_UP_BUS | ++ GQSPI_GFIFO_CS_UPPER | ++ GQSPI_GFIFO_CS_LOWER; + else if (priv->bus == SPI_XFER_ON_LOWER) - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS | - ZYNQMP_QSPI_GFIFO_CS_UPPER | - ZYNQMP_QSPI_GFIFO_CS_LOWER; ++ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | ++ GQSPI_GFIFO_CS_UPPER | ++ GQSPI_GFIFO_CS_LOWER; + else if (priv->bus == SPI_XFER_ON_UPPER) - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS | - ZYNQMP_QSPI_GFIFO_CS_LOWER | - ZYNQMP_QSPI_GFIFO_CS_UPPER; ++ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS | ++ GQSPI_GFIFO_CS_LOWER | ++ GQSPI_GFIFO_CS_UPPER; + else + debug("Wrong Bus selection:0x%x\n", priv->bus); + } else { + if (priv->u_page) - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS | - ZYNQMP_QSPI_GFIFO_CS_UPPER; ++ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | ++ GQSPI_GFIFO_CS_UPPER; + else - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS | - ZYNQMP_QSPI_GFIFO_CS_LOWER; ++ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | ++ GQSPI_GFIFO_CS_LOWER; + } return gqspi_fifo_reg; } @@@ -330,24 -221,12 +285,26 @@@ static void zynqmp_qspi_fill_gen_fifo(s u32 gqspi_fifo_reg) { struct zynqmp_qspi_regs *regs = priv->regs; - u32 reg, config_reg, ier; ++ u32 config_reg, ier; + int ret = 0; - ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, + config_reg = readl(®s->confr); + /* Manual start if needed */ - if (config_reg & ZYNQMP_QSPI_GEN_FIFO_STRT_MOD) { - config_reg |= ZYNQMP_QSPI_STRT_GEN_FIFO; ++ if (config_reg & GQSPI_GEN_FIFO_STRT_MOD) { ++ config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + + /* Enable interrupts */ + ier = readl(®s->ier); - ier |= ZYNQMP_QSPI_IXR_ALL_MASK; ++ ier |= GQSPI_IXR_ALL_MASK; + writel(ier, ®s->ier); + } + + /* Wait until the fifo is not full to write the new command */ - do { - reg = readl(®s->isr); - } while (!(reg & ZYNQMP_QSPI_IXR_GFNFULL_MASK)); ++ ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1, + GQSPI_TIMEOUT, 1); + if (ret) + printf("%s Timeout\n", __func__); writel(gqspi_fifo_reg, ®s->genfifo); } @@@ -358,17 -237,11 +315,17 @@@ static void zynqmp_qspi_chipselect(stru if (is_on) { gqspi_fifo_reg = zynqmp_qspi_bus_select(priv); - gqspi_fifo_reg |= ZYNQMP_QSPI_SPI_MODE_SPI | - ZYNQMP_QSPI_IMD_DATA_CS_ASSERT; + gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI | + GQSPI_IMD_DATA_CS_ASSERT; } else { - gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS; + if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS | - ZYNQMP_QSPI_GFIFO_LOW_BUS; ++ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS | ++ GQSPI_GFIFO_LOW_BUS; + else if (priv->u_page) - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS; ++ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS; + else - gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS; - gqspi_fifo_reg |= ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT; ++ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS; + gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; } debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); @@@ -376,25 -249,6 +333,7 @@@ zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); } - #define GQSPI_BAUD_DIV_SHIFT 2 - #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 - #define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 - #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 - #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 - #define GQSPI_USE_DATA_DLY 0x1 - #define GQSPI_USE_DATA_DLY_SHIFT 31 - #define GQSPI_DATA_DLY_ADJ_VALUE 0x2 - #define GQSPI_DATA_DLY_ADJ_SHIFT 28 - #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 - #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 - #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 - #define IOU_TAPDLY_BYPASS_OFST 0xFF180390 - #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 - #define GQSPI_FREQ_40MHZ 40000000 - #define GQSPI_FREQ_100MHZ 100000000 - #define GQSPI_FREQ_150MHZ 150000000 - #define IOU_TAPDLY_BYPASS_MASK 0x7 - ++#if !defined(CONFIG_ARCH_VERSAL) void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) { struct zynqmp_qspi_platdata *plat = bus->platdata; @@@ -434,6 -288,6 +373,7 @@@ writel(lpbkdlyadj, ®s->lpbkdly); writel(datadlyadj, ®s->gqspidlyadj); } ++#endif static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) { @@@ -467,43 -321,45 +407,69 @@@ confr |= (baud_rate_val << 3); writel(confr, ®s->confr); ++#if !defined(CONFIG_ARCH_VERSAL) zynqmp_qspi_set_tapdelay(bus, baud_rate_val); ++#endif debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz); return 0; } +static int zynqmp_qspi_child_pre_probe(struct udevice *bus) +{ + struct spi_slave *slave = dev_get_parent_priv(bus); + struct zynqmp_qspi_priv *priv = dev_get_priv(bus->parent); - struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus->parent); + + slave->option = priv->is_dual; - slave->mode = plat->tx_rx_mode; + slave->bytemode = SPI_4BYTE_MODE; + + return 0; +} + static int zynqmp_qspi_probe(struct udevice *bus) { struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus); struct zynqmp_qspi_priv *priv = dev_get_priv(bus); ++#if !defined(CONFIG_ARCH_VERSAL) + struct clk clk; + unsigned long clock; + int ret; ++#endif - debug("zynqmp_qspi_probe: bus:%p, priv:%p \n", bus, priv); + debug("%s: bus:%p, priv:%p\n", __func__, bus, priv); priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; + priv->is_dual = plat->is_dual; - priv->tx_rx_mode = plat->tx_rx_mode; + priv->io_mode = plat->io_mode; + if (priv->is_dual == -1) { + debug("%s: No QSPI device detected based on MIO settings\n", + __func__); + return -1; + } ++#if !defined(CONFIG_ARCH_VERSAL) + ret = clk_get_by_index(bus, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + plat->frequency = clock; - plat->speed_hz = plat->frequency / 2; ++ plat->speed_hz = plat->frequency; ++#endif /* init the zynq spi hw */ zynqmp_qspi_init_hw(priv); @@@ -520,27 -376,23 +486,24 @@@ static int zynqmp_qspi_set_mode(struct debug("%s\n", __func__); /* Set the SPI Clock phase and polarities */ confr = readl(®s->confr); - confr &= ~(ZYNQMP_QSPI_CONFIG_CPHA_MASK | - ZYNQMP_QSPI_CONFIG_CPOL_MASK); + confr &= ~(GQSPI_CONFIG_CPHA_MASK | + GQSPI_CONFIG_CPOL_MASK); - if (priv->mode & SPI_CPHA) - confr |= ZYNQMP_QSPI_CONFIG_CPHA_MASK; - if (priv->mode & SPI_CPOL) - confr |= ZYNQMP_QSPI_CONFIG_CPOL_MASK; + if (mode & SPI_CPHA) + confr |= GQSPI_CONFIG_CPHA_MASK; + if (mode & SPI_CPOL) + confr |= GQSPI_CONFIG_CPOL_MASK; - //writel(confr, ®s->confr); - priv->mode = mode; - - debug("regs=%p, mode=%d\n", priv->regs, priv->mode); + writel(confr, ®s->confr); ++ priv->tx_rx_mode = mode; return 0; } - static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) { - u32 data; + u32 data, config_reg, ier; - u32 timeout = ZYNQMP_QSPI_TIMEOUT; + int ret = 0; struct zynqmp_qspi_regs *regs = priv->regs; u32 *buf = (u32 *)priv->tx_buf; u32 len = size; @@@ -548,56 -400,42 +511,53 @@@ debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr), size); + config_reg = readl(®s->confr); + /* Manual start if needed */ - if (config_reg & ZYNQMP_QSPI_GEN_FIFO_STRT_MOD) { - config_reg |= ZYNQMP_QSPI_STRT_GEN_FIFO; ++ if (config_reg & GQSPI_GEN_FIFO_STRT_MOD) { ++ config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + /* Enable interrupts */ + ier = readl(®s->ier); - ier |= ZYNQMP_QSPI_IXR_ALL_MASK; ++ ier |= GQSPI_IXR_ALL_MASK; + writel(ier, ®s->ier); + } + - while (size && timeout) { - if (readl(®s->isr) & - ZYNQMP_QSPI_IXR_TXNFULL_MASK) { - if (size >= 4) { - writel(*buf, ®s->txd0r); - buf++; - size -= 4; - } else { - switch (size) { - case 1: - data = *((u8 *)buf); - buf += 1; - data |= 0xFFFFFF00; - break; - case 2: - data = *((u16 *)buf); - buf += 2; - data |= 0xFFFF0000; - break; - case 3: - data = *((u16 *)buf); - buf += 2; - data |= (*((u8 *)buf) << 16); - buf += 1; - data |= 0xFF000000; - break; - } - writel(data, ®s->txd0r); - size = 0; - } + while (size) { + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1, + GQSPI_TIMEOUT, 1); + if (ret) { + printf("%s: Timeout\n", __func__); + return ret; + } + + if (size >= 4) { + writel(*buf, ®s->txd0r); + buf++; + size -= 4; } else { - udelay(1); - timeout--; + switch (size) { + case 1: + data = *((u8 *)buf); + buf += 1; + data |= GENMASK(31, 8); + break; + case 2: + data = *((u16 *)buf); + buf += 2; + data |= GENMASK(31, 16); + break; + case 3: + data = *((u16 *)buf); + buf += 2; + data |= (*((u8 *)buf) << 16); + buf += 1; + data |= GENMASK(31, 24); + break; + } + writel(data, ®s->txd0r); + size = 0; } } - if (!timeout) { - printf("zynqmp_qspi_fill_tx_fifo: Timeout\n"); - return -1; - } priv->tx_buf += len; return 0; @@@ -609,19 -446,9 +569,19 @@@ static void zynqmp_qspi_genfifo_cmd(str u32 gen_fifo_cmd; u32 bytecount = 0; + if (priv->dummy_bytes) + priv->len -= priv->dummy_bytes; + while (priv->len) { gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX; - gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI; ++ gen_fifo_cmd |= GQSPI_GFIFO_TX; + + if (command) { + command = 0; + last_cmd = *(u8 *)priv->tx_buf; + } + - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; gen_fifo_cmd |= *(u8 *)priv->tx_buf; bytecount++; priv->len--; @@@ -631,20 -458,6 +591,20 @@@ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); } + + if (priv->dummy_bytes) { + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd &= ~(ZYNQMP_QSPI_GFIFO_TX | ZYNQMP_QSPI_GFIFO_RX); ++ gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX); + if (priv->tx_rx_mode & SPI_RX_QUAD) - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI; + else if (priv->tx_rx_mode & SPI_RX_DUAL) - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_DUAL_SPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_DUAL_SPI; + else - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI; - gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; ++ gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= (priv->dummy_bytes * 8); + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + } } static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv, @@@ -681,16 -494,10 +641,16 @@@ static int zynqmp_qspi_genfifo_fill_tx( int ret = 0; gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX | - ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= GQSPI_GFIFO_TX | + GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + if (priv->stripe) - gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK; ++ gen_fifo_cmd |= GQSPI_GFIFO_STRIPE_MASK; + + if (last_cmd == QUAD_PAGE_PROGRAM_CMD) - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI; + else - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); @@@ -711,83 -518,21 +671,81 @@@ return ret; } +static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, - u32 gen_fifo_cmd, dma_addr_t *buf) ++ u32 gen_fifo_cmd, u32 *buf) +{ + u32 len; + u32 actuallen = priv->len; + u32 config_reg, ier, isr; - u32 timeout = ZYNQMP_QSPI_TIMEOUT; ++ u32 timeout = GQSPI_TIMEOUT; + struct zynqmp_qspi_regs *regs = priv->regs; + u32 last_bits; - void *traverse = (dma_addr_t *)buf; ++ u32 *traverse = buf; + + while (priv->len) { + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); + /* If exponent bit is set, reset immediate to be 2^len */ - if (gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK) ++ if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) + priv->bytes_to_receive = (1 << len); + else + priv->bytes_to_receive = len; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + /* Manual start */ + config_reg = readl(®s->confr); - config_reg |= ZYNQMP_QSPI_STRT_GEN_FIFO; ++ config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + /* Enable RX interrupts for IO mode */ + ier = readl(®s->ier); - ier |= ZYNQMP_QSPI_IXR_ALL_MASK; ++ ier |= GQSPI_IXR_ALL_MASK; + writel(ier, ®s->ier); + while (priv->bytes_to_receive && timeout) { + isr = readl(®s->isr); - if (isr & ZYNQMP_QSPI_IXR_RXNEMTY_MASK) { ++ if (isr & GQSPI_IXR_RXNEMTY_MASK) { + if (priv->bytes_to_receive >= 4) { - (*(u32 *)traverse) = readl(®s->drxr); - traverse += 4; ++ *traverse = readl(®s->drxr); ++ traverse++; + priv->bytes_to_receive -= 4; + } else { + last_bits = readl(®s->drxr); + memcpy(traverse, &last_bits, + priv->bytes_to_receive); + priv->bytes_to_receive = 0; + } - timeout = ZYNQMP_QSPI_TIMEOUT; ++ timeout = GQSPI_TIMEOUT; + } else { + udelay(1); + timeout--; + } + } + - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%llx len: 0x%x\n", ++ debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", + (unsigned long)buf, (unsigned long)priv->rx_buf, + *buf, actuallen); + if (!timeout) { + printf("IO timeout: %d\n", readl(®s->isr)); + return -1; + } + } + + return 0; +} + static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, - u32 gen_fifo_cmd, dma_addr_t *buf) + u32 gen_fifo_cmd, u32 *buf) { - dma_addr_t addr; + u32 addr; u32 size, len; - u32 timeout = ZYNQMP_QSPI_TIMEOUT; u32 actuallen = priv->len; + int ret = 0; struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs; - writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst); - writel(upper_32_bits((unsigned long)buf), &dma_regs->dmadstmsb); - - writel(roundup(priv->len, 4), &dma_regs->dmasize); - writel(ZYNQMP_QSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); + writel((unsigned long)buf, &dma_regs->dmadst); + writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize); + writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; size = roundup(priv->len, ARCH_DMA_MINALIGN); - flush_dcache_range(addr, addr+size); + flush_dcache_range(addr, addr + size); while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); @@@ -833,30 -572,19 +785,30 @@@ static int zynqmp_qspi_genfifo_fill_rx( u32 actuallen = priv->len; gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_RX | - ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= GQSPI_GFIFO_RX | + GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + if (last_cmd == QUAD_OUT_READ_CMD) - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_QSPI; + else if (last_cmd == DUAL_OUTPUT_FASTRD_CMD) - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_DUAL_SPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_DUAL_SPI; + else - gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI; ++ gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; + + if (priv->stripe) - gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK; ++ gen_fifo_cmd |= GQSPI_GFIFO_STRIPE_MASK; /* * Check if receive buffer is aligned to 4 byte and length * is multiples of four byte as we are using dma to receive. */ - if ((!((unsigned long)priv->rx_buf & (ZYNQMP_QSPI_DMA_ALIGN - 1)) && - !(actuallen % ZYNQMP_QSPI_DMA_ALIGN)) || priv->io_mode) { - buf = (dma_addr_t *)priv->rx_buf; - if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && - !(actuallen % GQSPI_DMA_ALIGN)) { ++ if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && ++ !(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) { + buf = (u32 *)priv->rx_buf; - return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); + if (priv->io_mode) + return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf); + else + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); } ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, diff --cc include/configs/xilinx_zynqmp.h index 3405cdbd569,0ab32611cee..ccbfd14b289 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@@ -75,30 -53,9 +53,16 @@@ #ifdef CONFIG_NAND_ARASAN # define CONFIG_SYS_MAX_NAND_DEVICE 1 - # define CONFIG_SYS_NAND_SELF_INIT # define CONFIG_SYS_NAND_ONFI_DETECTION - # define CONFIG_MTD_DEVICE #endif +#if !defined(CONFIG_SPL_BUILD) - #define CONFIG_CMD_UBI - #define CONFIG_RBTREE - #define CONFIG_CMD_UBIFS - #define CONFIG_LZO - - #define CONFIG_CMD_MTDPARTS - #define CONFIG_MTD_DEVICE - #define CONFIG_MTD_PARTITIONS - - #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 - #define CONFIG_MTD_UBI_BEB_LIMIT 0 - - #if defined(CONFIG_ZYNQMP_QSPI) ++#if defined(CONFIG_ZYNQMP_GQSPI) +/* SPI layer registers with MTD */ +#define CONFIG_SPI_FLASH_MTD +#endif +#endif + #if defined(CONFIG_SPL_BUILD) #define CONFIG_ZYNQMP_PSU_INIT_ENABLED #endif @@@ -139,95 -95,6 +102,89 @@@ # define PARTS_DEFAULT #endif +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x80000\0" \ + "initrd_addr=0xa00000\0" \ + "initrd_size=0x2000000\0" \ + "fdt_addr=4000000\0" \ + "fdt_high=0x10000000\0" \ + "loadbootenv_addr=0x100000\0" \ + "sdbootdev=0\0"\ + "kernel_offset=0x280000\0" \ + "fdt_offset=0x200000\0" \ + "kernel_size=0x1e00000\0" \ + "fdt_size=0x80000\0" \ + "bootenv=uEnv.txt\0" \ ++ "partid=auto\0" \ + "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from SD ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \ + "sata_root=if test $scsidevs -gt 0; then setenv bootargs $bootargs root=/dev/sda rw rootfstype=ext4; fi\0" \ + "sataboot=load scsi 0 80000 boot/Image && load scsi 0 $fdt_addr boot/system.dtb && booti 80000 - $fdt_addr\0" \ - "veloce=fdt addr f000000 && fdt resize" \ - "fdt set /amba/misc_clk clock-frequency <48000> && "\ - "fdt set /timer clock-frequency <240000> && " \ - "fdt set /amba/i2c_clk clock-frequency <240000> && " \ - "booti 80000 - f000000\0" \ + "netboot=tftpboot 10000000 image.ub && bootm\0" \ + "qspiboot=sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && " \ + "sf read $kernel_addr $kernel_offset $kernel_size && " \ + "booti $kernel_addr - $fdt_addr\0" \ + "uenvboot=" \ + "if run sd_uEnvtxt_existence_test; then " \ + "run loadbootenv; " \ + "echo Loaded environment from ${bootenv}; " \ + "run importbootenv; " \ + "fi; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi\0" \ + "sdboot=mmc dev $sdbootdev && mmcinfo && run uenvboot || run sdroot$sdbootdev; " \ + "load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ + "load mmc $sdbootdev:$partid $kernel_addr Image && " \ + "booti $kernel_addr - $fdt_addr\0" \ + "emmcboot=run sdboot\0" \ + "nandboot=nand info && nand read $fdt_addr $fdt_offset $fdt_size && " \ + "nand read $kernel_addr $kernel_offset $kernel_size && " \ + "booti $kernel_addr - $fdt_addr\0" \ + "xen_prepare_dt=fdt addr $fdt_addr && fdt resize 128 && " \ + "fdt set /chosen \\\\#address-cells <1> && " \ + "fdt set /chosen \\\\#size-cells <1> && " \ + "fdt mknod /chosen dom0 && " \ + "fdt set /chosen/dom0 compatible \"xen,linux-zimage\" \"xen,multiboot-module\" && " \ + "fdt set /chosen/dom0 reg <0x80000 0x$filesize> && " \ + "fdt set /chosen xen,xen-bootargs \"console=dtuart dtuart=serial0 dom0_mem=768M bootscrub=0 maxcpus=1 timer_slop=0\" && " \ + "fdt set /chosen xen,dom0-bootargs \"console=hvc0 earlycon=xen earlyprintk=xen maxcpus=1 clk_ignore_unused\"\0" \ + "xen_prepare_dt_qemu=run xen_prepare_dt && " \ + "fdt set /cpus/cpu@1 device_type \"none\" && " \ + "fdt set /cpus/cpu@2 device_type \"none\" && " \ + "fdt set /cpus/cpu@3 device_type \"none\" && " \ + "fdt rm /cpus/cpu@1 compatible && " \ + "fdt rm /cpus/cpu@2 compatible && " \ + "fdt rm /cpus/cpu@3 compatible\0" \ + "xen=tftpb $fdt_addr system.dtb && tftpb 0x80000 Image &&" \ + "run xen_prepare_dt && " \ + "tftpb 6000000 xen.ub && tftpb 0x1000000 image.ub && " \ + "bootm 6000000 0x1000000 $fdt_addr\0" \ + "xen_qemu=tftpb $fdt_addr system.dtb && tftpb 0x80000 Image && " \ + "run xen_prepare_dt_qemu && " \ + "tftpb 6000000 xen.ub && tftpb 0x1000000 image.ub && " \ + "bootm 6000000 0x1000000 $fdt_addr\0" \ + "jtagboot=tftpboot 80000 Image && tftpboot $fdt_addr system.dtb && " \ + "tftpboot 6000000 rootfs.cpio.ub && booti 80000 6000000 $fdt_addr\0" \ + "nosmp=setenv bootargs $bootargs maxcpus=1\0" \ + "nfsroot=setenv bootargs $bootargs root=/dev/nfs nfsroot=$serverip:/mnt/sata,tcp ip=$ipaddr:$serverip:$serverip:255.255.255.0:zynqmp:eth0:off rw\0" \ + "sdroot0=setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait\0" \ + "sdroot1=setenv bootargs $bootargs root=/dev/mmcblk1p2 rw rootwait\0" \ + "android=setenv bootargs $bootargs init=/init androidboot.selinux=disabled androidboot.hardware=$board\0" \ + "android_debug=run android && setenv bootargs $bootargs video=DP-1:1024x768@60 drm.debug=0xf\0" \ + "usb_dfu_spl=booti $kernel_addr - $fdt_addr\0" \ + "usbhostboot=usb start && load usb 0 $fdt_addr system.dtb && " \ + "load usb 0 $kernel_addr Image && " \ + "booti $kernel_addr - $fdt_addr\0" \ + PARTS_DEFAULT \ + DFU_ALT_INFO +#endif + - #define CONFIG_PREBOOT "run setup" - /* Monitor Command Prompt */ /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 2048 diff --cc include/configs/zynq-common.h index 623ee49c950,864f3220f36..b57bd1553e9 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@@ -142,16 -112,6 +112,13 @@@ # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 # define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 # define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ +# define CONFIG_SYS_I2C_MUX_ADDR 0x74 +# define CONFIG_SYS_I2C_MUX_EEPROM_SEL 0x4 +#endif + +/* Total Size of Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_EEPROM - # define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE +# define CONFIG_EXTRA_ENV_SETTINGS - #else - # define CONFIG_ENV_SIZE (128 << 10) #endif /* Allow to overwrite serial and ethaddr */ @@@ -322,19 -217,9 +277,12 @@@ /* Miscellaneous configurable options */ - #define CONFIG_CMDLINE_EDITING - #define CONFIG_AUTO_COMPLETE - #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) - #ifndef CONFIG_NR_DRAM_BANKS - # define CONFIG_NR_DRAM_BANKS 1 - #endif - #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 0x1000 @@@ -358,19 -238,6 +301,8 @@@ #define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds" +#undef CONFIG_BOOTM_NETBSD + - #define CONFIG_SYS_HZ 1000 - - /* For development/debugging */ - #ifdef DEBUG - # define CONFIG_CMD_REGINFO - # define CONFIG_PANIC_HANG - #endif - - /* SPL part */ - #define CONFIG_SPL_FRAMEWORK - /* MMC support */ #ifdef CONFIG_MMC_SDHCI_ZYNQ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --cc include/phy.h index cffe1293403,b86fdfb2ce3..bbebf0a0349 --- a/include/phy.h +++ b/include/phy.h @@@ -14,13 -14,9 +14,14 @@@ #include #include #include + #include #define PHY_FIXED_ID 0xa5a55a5a +/* + * There is no actual id for this. + * This is just a dummy id for gmii2rgmmi converter + */ +#define PHY_GMII2RGMII_ID 0x5a5a5a5a #define PHY_MAX_ADDR 32 diff --cc include/spi.h index 0b084a34805,938627bc012..96873cfd857 --- a/include/spi.h +++ b/include/spi.h @@@ -129,13 -105,11 +132,14 @@@ struct spi_slave #endif uint mode; unsigned int wordlen; + unsigned int max_read_size; unsigned int max_write_size; void *memory_map; - - u8 flags; + u8 option; + u8 dio; + u32 bytemode; + u32 flags; + u8 dummy_bytes; #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) diff --cc test/py/tests/test_net.py index 6df495a7aef,2821ce65da8..1933ca36b33 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@@ -150,14 -146,10 +149,14 @@@ def test_net_tftpboot(u_boot_console) addr = f.get('addr', None) if not addr: - addr = u_boot_utils.find_ram_base(u_boot_console) + (1024 * 1024 * 4) + addr = u_boot_utils.find_ram_base(u_boot_console) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] - output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + expected_text = 'Bytes transferred = ' sz = f.get('size', None) if sz: