From: amodra Date: Thu, 29 Nov 2018 04:58:08 +0000 (+0000) Subject: [RS6000] "G" and "H" constraints X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=fea980b417afae0b8e6e094d3611c90553b6f541;p=thirdparty%2Fgcc.git [RS6000] "G" and "H" constraints The patch fixes two cases where the "G" and "H" constraints were used incorrectly. Their purpose is calculating insn lengths. Thus it never makes sense to put "GH" together or with "F" in an insn alternative. movdi_internal32 used "GHF" in an alternative so I replaced that with "F", and added length attributes for the insn, which were missing. There are some formatting changes too, to make alternatives line up with attributes. The FMOVE128 version of mov_softfloat also had "GHF" in an alternative, so "GH" is dropped and "F" moved to a separate alternative in order to get insn lengths correct. Well by correct I mean we need to choose the maximum insn length otherwise branches might not reach. Note the very large length for "F". I think it would be better to force soft-float long double constants to memory in 64-bit mode, but that's a patch for another day. * config/rs6000/constraints.md (G, H): Comment on purpose of constraint. Correct mode comments and "G" mode test. * config/rs6000/rs6000.md (movdi_internal32): Remove "GH" from alternative handling "F". Add length attr. Formatting. (mov_softfloat ): Delete "GH" from alternative, and move "F" to separate alternative. Correct insn lengths. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@266607 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b1ea39997520..95492d4597e9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2018-11-29 Alan Modra + + * config/rs6000/constraints.md (G, H): Comment on purpose of + constraint. Correct mode comments and "G" mode test. + * config/rs6000/rs6000.md (movdi_internal32): Remove "GH" from + alternative handling "F". Add length attr. Formatting. + (mov_softfloat ): Delete "GH" from + alternative, and move "F" to separate alternative. Correct + insn lengths. + 2018-11-29 Alan Modra * config/rs6000/predicates.md (easy_vector_constant): Don't call diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 90aba1e77d34..5b89a836b060 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -252,17 +252,18 @@ (and (match_code "const_int") (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) -;; Floating-point constraints +;; Floating-point constraints. These two are defined so that insn +;; length attributes can be calculated exactly. (define_constraint "G" - "Constant that can be copied into GPR with two insns for DF/DI - and one for SF." + "Constant that can be copied into GPR with two insns for DF/DD + and one for SF/SD." (and (match_code "const_double") (match_test "num_insns_constant (op, mode) - == (mode == SFmode ? 1 : 2)"))) + == (mode == SFmode || mode == SDmode ? 1 : 2)"))) (define_constraint "H" - "DF/DI constant that takes three insns." + "DF/DD constant that takes three insns." (and (match_code "const_double") (match_test "num_insns_constant (op, mode) == 3"))) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8427a5e55bb7..6f371b4d282c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7712,8 +7712,8 @@ [(set_attr "length" "8,8,8,8,20,20,16")]) (define_insn_and_split "*mov_softfloat" - [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=Y,r,r") - (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))] + [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=Y,r,r,r") + (match_operand:FMOVE128 1 "input_operand" "r,Y,F,r"))] "TARGET_SOFT_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7721,7 +7721,19 @@ "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "20,20,16")]) + [(set_attr_alternative "length" + [(if_then_else (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")) + (if_then_else (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")) + (if_then_else (match_test "TARGET_POWERPC64") + (const_string "40") + (const_string "32")) + (if_then_else (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))])]) (define_expand "extenddf2" [(set (match_operand:FLOAT128 0 "gpc_reg_operand") @@ -8656,22 +8668,22 @@ ;; Use of fprs is disparaged slightly otherwise reload prefers to reload ;; a gpr into a fpr instead of reloading an invalid 'Y' address -;; GPR store GPR load GPR move FPR store FPR load FPR move -;; GPR const AVX store AVX store AVX load AVX load VSX move -;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const +;; GPR store GPR load GPR move FPR store FPR load FPR move +;; GPR const AVX store AVX store AVX load AVX load VSX move +;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const ;; AVX const (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=Y, r, r, m, ^d, ^d, - r, wY, Z, ^wb, $wv, ^wi, - *wo, *wo, *wv, *wi, *wi, *wv, + "=Y, r, r, m, ^d, ^d, + r, wY, Z, ^wb, $wv, ^wi, + *wo, *wo, *wv, *wi, *wi, *wv, *wv") (match_operand:DI 1 "input_operand" - "r, Y, r, ^d, m, ^d, - IJKnGHF, ^wb, $wv, wY, Z, ^wi, - Oj, wM, OjwM, Oj, wM, wS, + "r, Y, r, ^d, m, ^d, + IJKnF, ^wb, $wv, wY, Z, ^wi, + Oj, wM, OjwM, Oj, wM, wS, wB"))] "! TARGET_POWERPC64 @@ -8698,11 +8710,16 @@ # #" [(set_attr "type" - "store, load, *, fpstore, fpload, fpsimple, - *, fpstore, fpstore, fpload, fpload, veclogical, - vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, - vecsimple") - (set_attr "size" "64")]) + "store, load, *, fpstore, fpload, fpsimple, + *, fpstore, fpstore, fpload, fpload, veclogical, + vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple, + vecsimple") + (set_attr "size" "64") + (set_attr "length" + "8, 8, 8, 4, 4, 4, + 16, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 8, + 4")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand")