From: Julian Seward <jseward@acm.org>
Date: Tue, 9 Jan 2007 15:20:07 +0000 (+0000)
Subject: Add 'missing' primop Iop_ReinterpF32asI32 and code generation support
X-Git-Tag: svn/VALGRIND_3_3_1^2~62
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ff3108ddb196000467c73f33f24106e8ec14aabb;p=thirdparty%2Fvalgrind.git

Add 'missing' primop Iop_ReinterpF32asI32 and code generation support
for it on x86 hosts.



git-svn-id: svn://svn.valgrind.org/vex/trunk@1721
---

diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index 2c339dbb6e..94a1f5d559 100644
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -1143,6 +1143,29 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
             return dst;
          }
 
+         /* ReinterpF32asI32(e) */
+         /* Given an IEEE754 single, produce an I32 with the same bit
+            pattern.  Keep stack 8-aligned even though only using 4
+            bytes. */
+         case Iop_ReinterpF32asI32: {
+            HReg rf   = iselFltExpr(env, e->Iex.Unop.arg);
+            HReg dst  = newVRegI(env);
+            X86AMode* zero_esp = X86AMode_IR(0, hregX86_ESP());
+            /* paranoia */
+            set_FPU_rounding_default(env);
+            /* subl $8, %esp */
+            sub_from_esp(env, 8);
+            /* gstF %rf, 0(%esp) */
+            addInstr(env,
+                     X86Instr_FpLdSt(False/*store*/, 4, rf, zero_esp));
+            /* movl 0(%esp), %dst */
+            addInstr(env, 
+                     X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(zero_esp), dst));
+            /* addl $8, %esp */
+            add_to_esp(env, 8);
+            return dst;
+         }
+
          case Iop_16to8:
          case Iop_32to8:
          case Iop_32to16:
diff --git a/VEX/priv/ir/irdefs.c b/VEX/priv/ir/irdefs.c
index eb12305224..a6462ba0d4 100644
--- a/VEX/priv/ir/irdefs.c
+++ b/VEX/priv/ir/irdefs.c
@@ -294,6 +294,7 @@ void ppIROp ( IROp op )
 
       case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return;
       case Iop_ReinterpI64asF64: vex_printf("ReinterpI64asF64"); return;
+      case Iop_ReinterpF32asI32: vex_printf("ReinterpF32asI32"); return;
       case Iop_ReinterpI32asF32: vex_printf("ReinterpI32asF32"); return;
 
       case Iop_I32UtoFx4: vex_printf("Iop_I32UtoFx4"); return;
@@ -1655,6 +1656,7 @@ void typeOfPrimop ( IROp op,
       case Iop_ReinterpI64asF64: UNARY(Ity_I64, Ity_F64);
       case Iop_ReinterpF64asI64: UNARY(Ity_F64, Ity_I64);
       case Iop_ReinterpI32asF32: UNARY(Ity_I32, Ity_F32);
+      case Iop_ReinterpF32asI32: UNARY(Ity_F32, Ity_I32);
 
       case Iop_AtanF64: case Iop_Yl2xF64:  case Iop_Yl2xp1F64: 
       case Iop_ScaleF64: case Iop_PRemF64: case Iop_PRem1F64:
diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
index 314322171d..436df5264a 100644
--- a/VEX/pub/libvex_ir.h
+++ b/VEX/pub/libvex_ir.h
@@ -590,7 +590,7 @@ typedef
       /* Reinterpretation.  Take an F64 and produce an I64 with 
          the same bit pattern, or vice versa. */
       Iop_ReinterpF64asI64, Iop_ReinterpI64asF64,
-                            Iop_ReinterpI32asF32,
+      Iop_ReinterpF32asI32, Iop_ReinterpI32asF32,
 
       /* --- guest x86/amd64 specifics, not mandated by 754. --- */