From: Tamar Christina Date: Thu, 9 Nov 2023 14:18:48 +0000 (+0000) Subject: AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient... X-Git-Tag: basepoints/gcc-15~4851 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ffd40d3b233d63c925cceb0dcd5a4fc8925e2993;p=thirdparty%2Fgcc.git AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154] SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has and so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR by immediate and would require a reload then use an unpredicated SVE ORR instead. This has both speed and size improvements. gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64.md (3): Add SVE split case. * config/aarch64/aarch64-simd.md (ior3): Likewise. * config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/sve/fneg-abs_1.c: Updated. * gcc.target/aarch64/sve/fneg-abs_2.c: Updated. * gcc.target/aarch64/sve/fneg-abs_4.c: Updated. --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 33eceb436584..98c418c54a82 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1219,11 +1219,14 @@ (define_insn "ior3" [(set (match_operand:VDQ_I 0 "register_operand") (ior:VDQ_I (match_operand:VDQ_I 1 "register_operand") - (match_operand:VDQ_I 2 "aarch64_reg_or_orr_imm")))] - "TARGET_SIMD" - {@ [ cons: =0 , 1 , 2 ] - [ w , w , w ] orr\t%0., %1., %2. - [ w , 0 , Do ] << aarch64_output_simd_mov_immediate (operands[2], , AARCH64_CHECK_ORR); + (match_operand:VDQ_I 2 "aarch64_orr_imm_sve_advsimd")))] + "TARGET_SIMD" + {@ [ cons: =0 , 1 , 2; attrs: arch ] + [ w , w , w ; simd ] orr\t%0., %1., %2. + [ w , 0 , vsl; sve ] orr\t%Z0., %Z0., #%2 + [ w , 0 , Do ; simd ] \ + << aarch64_output_simd_mov_immediate (operands[2], , \ + AARCH64_CHECK_ORR); } [(set_attr "type" "neon_logic")] ) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4fcd71a2e9d1..c6b1506fe7b4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4599,7 +4599,8 @@ "" {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ] [ r , %r , r ; logic_reg , * ] \t%0, %1, %2 - [ rk , r , ; logic_imm , * ] \t%0, %1, %2 + [ rk , ^r , ; logic_imm , * ] \t%0, %1, %2 + [ w , 0 , ; * , sve ] \t%Z0., %Z0., #%2 [ w , w , w ; neon_logic , simd ] \t%0., %1., %2. } ) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 01de47439744..a73724a7fc05 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -871,6 +871,11 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_sve_logical_immediate"))) +(define_predicate "aarch64_orr_imm_sve_advsimd" + (ior (match_operand 0 "aarch64_reg_or_orr_imm") + (and (match_test "TARGET_SVE") + (match_operand 0 "aarch64_sve_logical_operand")))) + (define_predicate "aarch64_sve_gather_offset_b" (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_sve_gather_immediate_b"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c index 0c7664e6de77..a8b27199ff83 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c @@ -6,7 +6,7 @@ /* ** t1: -** orr v[0-9]+.2s, #128, lsl #24 +** orr z[0-9]+.s, z[0-9]+.s, #-2147483648 ** ret */ float32x2_t t1 (float32x2_t a) @@ -16,7 +16,7 @@ float32x2_t t1 (float32x2_t a) /* ** t2: -** orr v[0-9]+.4s, #128, lsl #24 +** orr z[0-9]+.s, z[0-9]+.s, #-2147483648 ** ret */ float32x4_t t2 (float32x4_t a) @@ -26,9 +26,7 @@ float32x4_t t2 (float32x4_t a) /* ** t3: -** adrp x0, .LC[0-9]+ -** ldr q[0-9]+, \[x0, #:lo12:.LC0\] -** orr v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b +** orr z[0-9]+.d, z[0-9]+.d, #-9223372036854775808 ** ret */ float64x2_t t3 (float64x2_t a) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c index a60cd31b9294..19a7695e605b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c @@ -7,8 +7,7 @@ /* ** f1: -** movi v[0-9]+.2s, 0x80, lsl 24 -** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b +** orr z0.s, z0.s, #-2147483648 ** ret */ float32_t f1 (float32_t a) @@ -18,9 +17,7 @@ float32_t f1 (float32_t a) /* ** f2: -** mov x0, -9223372036854775808 -** fmov d[0-9]+, x0 -** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b +** orr z0.d, z0.d, #-9223372036854775808 ** ret */ float64_t f2 (float64_t a) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c index 21f2a8da2a5d..663d5fe17e09 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c @@ -6,9 +6,7 @@ /* ** negabs: -** mov x0, -9223372036854775808 -** fmov d[0-9]+, x0 -** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b +** orr z0.d, z0.d, #-9223372036854775808 ** ret */ double negabs (double x) @@ -22,8 +20,7 @@ double negabs (double x) /* ** negabsf: -** movi v[0-9]+.2s, 0x80, lsl 24 -** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b +** orr z0.s, z0.s, #-2147483648 ** ret */ float negabsf (float x)