From: Mieczyslaw Nalewaj Date: Mon, 19 May 2025 12:27:36 +0000 (+0200) Subject: treewide: strip trailing whitespace X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=refs%2Fpull%2F18626%2Fhead;p=thirdparty%2Fopenwrt.git treewide: strip trailing whitespace Strip trailing whitespace in all code: find . -type f | grep "\.c$" | xargs sed -i 's/[ \t]\+$//' find . -type f | grep "\.h$" | xargs sed -i 's/[ \t]\+$//' find . -type f | grep "\.dts$" | xargs sed -i 's/[ \t]\+$//' find . -type f | grep "\.dtsi$" | xargs sed -i 's/[ \t]\+$//' Signed-off-by: Mieczyslaw Nalewaj Link: https://github.com/openwrt/openwrt/pull/18626 Signed-off-by: Robert Marko --- diff --git a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c index c75ece2c8e3..2680e1fa866 100644 --- a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c +++ b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c @@ -1489,14 +1489,14 @@ IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t * pDev, long size) allocate_size = size; else allocate_size = SDRAM_SEGMENT_SIZE; - + org_mem_ptr = kmalloc (allocate_size, GFP_KERNEL); if (org_mem_ptr == NULL) { IFX_MEI_EMSG ("%d: kmalloc %d bytes memory fail!\n", idx, allocate_size); err = -ENOMEM; goto allocate_error; } - + if (((unsigned long)org_mem_ptr) & (1023)) { /* Pointer not 1k aligned, so free it and allocate a larger chunk * for further alignment. @@ -1637,7 +1637,7 @@ DSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf, retval = -ENOMEM; goto error; } - + if (((unsigned long)org_mem_ptr) & (1023)) { /* Pointer not 1k aligned, so free it and allocate a larger chunk * for further alignment. @@ -1654,7 +1654,7 @@ DSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf, } else { adsl_mem_info[XDATA_REGISTER].address = org_mem_ptr; } - + adsl_mem_info[XDATA_REGISTER].org_address = org_mem_ptr; adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE; @@ -1770,7 +1770,7 @@ int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p) IFX_MEI_EMSG("Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\n"); #else IFX_MEI_EMSG("Dying Gasp! Shutting Down...\n"); -// kill_proc (1, SIGINT, 1); +// kill_proc (1, SIGINT, 1); #endif return IRQ_HANDLED; } diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_aes.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_aes.c index 85234dd7a8c..fdd172750dc 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_aes.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_aes.c @@ -35,7 +35,7 @@ /*! \defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS \ingroup IFX_DEU - \brief IFX AES driver Functions + \brief IFX AES driver Functions */ @@ -68,7 +68,7 @@ #include "ifxmips_deu.h" -#if defined(CONFIG_DANUBE) +#if defined(CONFIG_DANUBE) #include "ifxmips_deu_danube.h" extern int ifx_danube_pre_1_4; #elif defined(CONFIG_AR9) @@ -114,7 +114,7 @@ void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes); void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes); int aes_memory_allocate(int value); int des_memory_allocate(int value); -void memory_release(u32 *addr); +void memory_release(u32 *addr); extern void ifx_deu_aes (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg, @@ -138,16 +138,16 @@ struct aes_ctx { }; extern int disable_deudma; -extern int disable_multiblock; +extern int disable_multiblock; /*! \fn int aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len) - * \ingroup IFX_AES_FUNCTIONS - * \brief sets the AES keys - * \param tfm linux crypto algo transform - * \param in_key input key - * \param key_len key lengths of 16, 24 and 32 bytes supported + * \ingroup IFX_AES_FUNCTIONS + * \brief sets the AES keys + * \param tfm linux crypto algo transform + * \param in_key input key + * \param key_len key lengths of 16, 24 and 32 bytes supported * \return -EINVAL - bad key length, 0 - SUCCESS -*/ +*/ static int aes_set_key (struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len) { struct aes_ctx *ctx = crypto_tfm_ctx(tfm); @@ -186,7 +186,7 @@ static int aes_set_key_skcipher (struct crypto_skcipher *tfm, const u8 *in_key, /*! \fn void aes_set_key_skcipher (void *ctx_arg) * \ingroup IFX_AES_FUNCTIONS * \brief sets the AES key to the hardware, requires spinlock to be set by caller - * \param ctx_arg crypto algo context + * \param ctx_arg crypto algo context * \return */ static void aes_set_key_hw (void *ctx_arg) @@ -242,15 +242,15 @@ static void aes_set_key_hw (void *ctx_arg) /*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode) * \ingroup IFX_AES_FUNCTIONS * \brief main interface to AES hardware - * \param ctx_arg crypto algo context - * \param out_arg output bytestream - * \param in_arg input bytestream - * \param iv_arg initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param mode operation mode such as ebc, cbc, ctr + * \param ctx_arg crypto algo context + * \param out_arg output bytestream + * \param in_arg input bytestream + * \param iv_arg initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param mode operation mode such as ebc, cbc, ctr * -*/ +*/ void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode) @@ -261,14 +261,14 @@ void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, unsigned long flag; /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ int i = 0; - int byte_cnt = nbytes; + int byte_cnt = nbytes; CRTCL_SECT_START; aes_set_key_hw (ctx_arg); aes->controlr.E_D = !encdec; //encryption - aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR + aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps if (mode > 0) { @@ -286,7 +286,7 @@ void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1)); aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2)); aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3)); /* start crypto */ - + while (aes->controlr.BUS) { // this will not take long } @@ -336,13 +336,13 @@ void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, /*! * \fn int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len) * \ingroup IFX_AES_FUNCTIONS - * \brief sets RFC3686 key - * \param tfm linux crypto algo transform - * \param in_key input key - * \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce + * \brief sets RFC3686 key + * \param tfm linux crypto algo transform + * \param in_key input key + * \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce * \return 0 - SUCCESS * -EINVAL - bad key length -*/ +*/ static int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len) { struct aes_ctx *ctx = crypto_tfm_ctx(tfm); @@ -360,7 +360,7 @@ static int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_ke ctx->key_length = key_len; ctx->use_tweak = 0; - + memcpy ((u8 *) (ctx->buf), in_key, key_len); return 0; @@ -384,13 +384,13 @@ static int ctr_rfc3686_aes_set_key_skcipher (struct crypto_skcipher *tfm, const /*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode) * \ingroup IFX_AES_FUNCTIONS * \brief main interface with deu hardware in DMA mode - * \param ctx_arg crypto algo context - * \param out_arg output bytestream - * \param in_arg input bytestream - * \param iv_arg initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param mode operation mode such as ebc, cbc, ctr + * \param ctx_arg crypto algo context + * \param out_arg output bytestream + * \param in_arg input bytestream + * \param iv_arg initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param mode operation mode such as ebc, cbc, ctr */ @@ -404,15 +404,15 @@ static int ctr_rfc3686_aes_set_key_skcipher (struct crypto_skcipher *tfm, const /*! \fn void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_AES_FUNCTIONS - * \brief sets AES hardware to ECB mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets AES hardware to ECB mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ static void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -421,15 +421,15 @@ static void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_AES_FUNCTIONS - * \brief sets AES hardware to CBC mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets AES hardware to CBC mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ static void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -438,15 +438,15 @@ static void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_AES_FUNCTIONS - * \brief sets AES hardware to OFB mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets AES hardware to OFB mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ static void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -455,15 +455,15 @@ static void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_AES_FUNCTIONS - * \brief sets AES hardware to CFB mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets AES hardware to CFB mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ static void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -472,15 +472,15 @@ static void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_AES_FUNCTIONS - * \brief sets AES hardware to CTR mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets AES hardware to CTR mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ static void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -555,7 +555,7 @@ static int ecb_aes_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes)) { enc_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, NULL, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -581,7 +581,7 @@ static int ecb_aes_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes)) { dec_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, NULL, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -627,7 +627,7 @@ static int cbc_aes_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes)) { u8 *iv = walk.iv; enc_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -654,7 +654,7 @@ static int cbc_aes_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes)) { u8 *iv = walk.iv; dec_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -704,7 +704,7 @@ static void ifx_deu_aes_xts (void *ctx_arg, u8 *out_arg, const u8 *in_arg, /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ u8 oldiv[16]; int i = 0; - int byte_cnt = nbytes; + int byte_cnt = nbytes; CRTCL_SECT_START; @@ -828,7 +828,7 @@ static int xts_aes_encrypt(struct skcipher_request *req) } } } - ifx_deu_aes_xts(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_xts(ctx, walk.dst.virt.addr, walk.src.virt.addr, iv, enc_bytes, CRYPTO_DIR_ENCRYPT); err = skcipher_walk_done(&walk, nbytes - enc_bytes); processed += enc_bytes; @@ -838,7 +838,7 @@ static int xts_aes_encrypt(struct skcipher_request *req) u8 *iv = walk.iv; nbytes = req->cryptlen - processed; scatterwalk_map_and_copy(ctx->lastbuffer, req->src, (req->cryptlen - nbytes), nbytes, 0); - ifx_deu_aes_xts(ctx, ctx->lastbuffer, ctx->lastbuffer, + ifx_deu_aes_xts(ctx, ctx->lastbuffer, ctx->lastbuffer, iv, nbytes, CRYPTO_DIR_ENCRYPT); scatterwalk_map_and_copy(ctx->lastbuffer, req->dst, (req->cryptlen - nbytes), nbytes, 1); skcipher_request_complete(req, 0); @@ -884,7 +884,7 @@ static int xts_aes_decrypt(struct skcipher_request *req) } } } - ifx_deu_aes_xts(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_xts(ctx, walk.dst.virt.addr, walk.src.virt.addr, iv, dec_bytes, CRYPTO_DIR_DECRYPT); err = skcipher_walk_done(&walk, nbytes - dec_bytes); processed += dec_bytes; @@ -894,7 +894,7 @@ static int xts_aes_decrypt(struct skcipher_request *req) u8 *iv = walk.iv; nbytes = req->cryptlen - processed; scatterwalk_map_and_copy(ctx->lastbuffer, req->src, (req->cryptlen - nbytes), nbytes, 0); - ifx_deu_aes_xts(ctx, ctx->lastbuffer, ctx->lastbuffer, + ifx_deu_aes_xts(ctx, ctx->lastbuffer, ctx->lastbuffer, iv, nbytes, CRYPTO_DIR_DECRYPT); scatterwalk_map_and_copy(ctx->lastbuffer, req->dst, (req->cryptlen - nbytes), nbytes, 1); skcipher_request_complete(req, 0); @@ -969,7 +969,7 @@ static int ofb_aes_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { enc_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr, walk.iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1002,7 +1002,7 @@ static int ofb_aes_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { dec_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr, walk.iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1057,7 +1057,7 @@ static int cfb_aes_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { enc_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr, walk.iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1090,7 +1090,7 @@ static int cfb_aes_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { dec_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr, walk.iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1145,7 +1145,7 @@ static int ctr_basic_aes_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { enc_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, walk.iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1178,7 +1178,7 @@ static int ctr_basic_aes_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { dec_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, walk.iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1233,7 +1233,7 @@ static int ctr_rfc3686_aes_encrypt(struct skcipher_request *req) nbytes = walk.nbytes; /* set up counter block */ - memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); + memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE); /* initialize counter portion of counter block */ @@ -1242,7 +1242,7 @@ static int ctr_rfc3686_aes_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { enc_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, rfc3686_iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1276,7 +1276,7 @@ static int ctr_rfc3686_aes_decrypt(struct skcipher_request *req) nbytes = walk.nbytes; /* set up counter block */ - memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); + memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE); /* initialize counter portion of counter block */ @@ -1285,7 +1285,7 @@ static int ctr_rfc3686_aes_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) { dec_bytes -= (nbytes % AES_BLOCK_SIZE); - ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, rfc3686_iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= AES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -1437,7 +1437,7 @@ static int aes_cbcmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_fin aes_set_key_hw (mctx); aes->controlr.E_D = !CRYPTO_DIR_ENCRYPT; //encryption - aes->controlr.O = 1; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR + aes->controlr.O = 1; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps @@ -1477,7 +1477,7 @@ static int aes_cbcmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_fin *((u32 *) mctx->hash + 3) = DEU_ENDIAN_SWAP(aes->IV0R); if (hash_final && offset) { - aes->controlr.O = 0; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR + aes->controlr.O = 0; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR crypto_xor(mctx->block, mctx->hash, offset); memcpy(p, mctx->hash + offset, (AES_BLOCK_SIZE - offset)); diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_arc4.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_arc4.c index 51f988fe43c..d4848569d73 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_arc4.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_arc4.c @@ -33,7 +33,7 @@ \brief ARC4 encryption DEU driver file */ -/*! +/*! \defgroup IFX_ARC4_FUNCTIONS IFX_ARC4_FUNCTIONS \ingroup IFX_DEU \brief IFX deu driver functions @@ -59,7 +59,7 @@ #ifdef CONFIG_VR9 #include "ifxmips_deu_vr9.h" #endif - + static spinlock_t lock; #define CRTCL_SECT_INIT spin_lock_init(&lock) #define CRTCL_SECT_START spin_lock_irqsave(&lock, flag) @@ -78,7 +78,7 @@ extern char debug_level; #define DPRINTF(level, format, args...) #endif -/* +/* * \brief arc4 private structure */ struct arc4_ctx { @@ -91,24 +91,24 @@ extern int disable_multiblock; /*! \fn static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode) \ingroup IFX_ARC4_FUNCTIONS - \brief main interface to ARC4 hardware - \param ctx_arg crypto algo context - \param out_arg output bytestream - \param in_arg input bytestream - \param iv_arg initialization vector - \param nbytes length of bytestream - \param encdec 1 for encrypt; 0 for decrypt - \param mode operation mode such as ebc, cbc, ctr -*/ + \brief main interface to ARC4 hardware + \param ctx_arg crypto algo context + \param out_arg output bytestream + \param in_arg input bytestream + \param iv_arg initialization vector + \param nbytes length of bytestream + \param encdec 1 for encrypt; 0 for decrypt + \param mode operation mode such as ebc, cbc, ctr +*/ static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode) { volatile struct arc4_t *arc4 = (struct arc4_t *) ARC4_START; - + int i = 0; unsigned long flag; - -#if 1 // need to handle nbytes not multiple of 16 + +#if 1 // need to handle nbytes not multiple of 16 volatile u32 tmp_array32[4]; volatile u8 *tmp_ptr8; int remaining_bytes, j; @@ -121,18 +121,18 @@ static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, #if 1 while (i < nbytes) { arc4->ID3R = *((u32 *) in_arg + (i>>2) + 0); - arc4->ID2R = *((u32 *) in_arg + (i>>2) + 1); + arc4->ID2R = *((u32 *) in_arg + (i>>2) + 1); arc4->ID1R = *((u32 *) in_arg + (i>>2) + 2); - arc4->ID0R = *((u32 *) in_arg + (i>>2) + 3); - - arc4->controlr.GO = 1; - + arc4->ID0R = *((u32 *) in_arg + (i>>2) + 3); + + arc4->controlr.GO = 1; + while (arc4->controlr.BUS) { // this will not take long } #if 1 - // need to handle nbytes not multiple of 16 + // need to handle nbytes not multiple of 16 tmp_array32[0] = arc4->OD3R; tmp_array32[1] = arc4->OD2R; tmp_array32[2] = arc4->OD1R; @@ -141,11 +141,11 @@ static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, remaining_bytes = nbytes - i; if (remaining_bytes > 16) remaining_bytes = 16; - + tmp_ptr8 = (u8 *)&tmp_array32[0]; for (j = 0; j < remaining_bytes; j++) *out_arg++ = *tmp_ptr8++; -#else +#else *((u32 *) out_arg + (i>>2) + 0) = arc4->OD3R; *((u32 *) out_arg + (i>>2) + 1) = arc4->OD2R; *((u32 *) out_arg + (i>>2) + 2) = arc4->OD1R; @@ -163,8 +163,8 @@ static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, /*! \fn arc4_chip_init (void) \ingroup IFX_ARC4_FUNCTIONS - \brief initialize arc4 hardware -*/ + \brief initialize arc4 hardware +*/ static void arc4_chip_init (void) { //do nothing @@ -172,18 +172,18 @@ static void arc4_chip_init (void) /*! \fn static int arc4_set_key(struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len) \ingroup IFX_ARC4_FUNCTIONS - \brief sets ARC4 key - \param tfm linux crypto algo transform - \param in_key input key - \param key_len key lengths less than or equal to 16 bytes supported -*/ + \brief sets ARC4 key + \param tfm linux crypto algo transform + \param in_key input key + \param key_len key lengths less than or equal to 16 bytes supported +*/ static int arc4_set_key(struct crypto_tfm *tfm, const u8 *inkey, unsigned int key_len) { //struct arc4_ctx *ctx = crypto_tfm_ctx(tfm); volatile struct arc4_t *arc4 = (struct arc4_t *) ARC4_START; u32 *in_key = (u32 *)inkey; - + // must program all bits at one go?!!! //#if 1 *IFX_ARC4_CON = ( (1<<31) | ((key_len - 1)<<27) | (1<<26) | (3<<16) ); @@ -194,7 +194,7 @@ static int arc4_set_key(struct crypto_tfm *tfm, const u8 *inkey, arc4->K1R = *((u32 *) in_key + 2); arc4->K0R = *((u32 *) in_key + 3); -#if 0 // arc4 is a ugly state machine, KSAE can only be set once per session +#if 0 // arc4 is a ugly state machine, KSAE can only be set once per session ctx->key_length = key_len; memcpy ((u8 *) (ctx->buf), in_key, key_len); @@ -218,15 +218,15 @@ static int arc4_set_key_skcipher(struct crypto_skcipher *tfm, const u8 *inkey, /*! \fn static void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) \ingroup IFX_ARC4_FUNCTIONS - \brief sets ARC4 hardware to ECB mode - \param ctx crypto algo context - \param dst output bytestream - \param src input bytestream - \param iv initialization vector - \param nbytes length of bytestream - \param encdec 1 for encrypt; 0 for decrypt - \param inplace not used -*/ + \brief sets ARC4 hardware to ECB mode + \param ctx crypto algo context + \param dst output bytestream + \param src input bytestream + \param iv initialization vector + \param nbytes length of bytestream + \param encdec 1 for encrypt; 0 for decrypt + \param inplace not used +*/ static void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -235,11 +235,11 @@ static void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn static void arc4_crypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) \ingroup IFX_ARC4_FUNCTIONS - \brief encrypt/decrypt ARC4_BLOCK_SIZE of data - \param tfm linux crypto algo transform - \param out output bytestream - \param in input bytestream -*/ + \brief encrypt/decrypt ARC4_BLOCK_SIZE of data + \param tfm linux crypto algo transform + \param out output bytestream + \param in input bytestream +*/ static void arc4_crypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) { struct arc4_ctx *ctx = crypto_tfm_ctx(tfm); @@ -288,7 +288,7 @@ static int ecb_arc4_encrypt(struct skcipher_request *req) err = skcipher_walk_virt(&walk, req, false); while ((nbytes = walk.nbytes)) { - _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= ARC4_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -313,7 +313,7 @@ static int ecb_arc4_decrypt(struct skcipher_request *req) err = skcipher_walk_virt(&walk, req, false); while ((nbytes = walk.nbytes)) { - _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, NULL, nbytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= ARC4_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -343,8 +343,8 @@ static struct skcipher_alg ifxdeu_ecb_arc4_alg = { /*! \fn int ifxdeu_init_arc4(void) \ingroup IFX_ARC4_FUNCTIONS - \brief initialize arc4 driver -*/ + \brief initialize arc4 driver +*/ int ifxdeu_init_arc4(void) { int ret = -ENOSYS; @@ -376,8 +376,8 @@ ecb_arc4_err: /*! \fn void ifxdeu_fini_arc4(void) \ingroup IFX_ARC4_FUNCTIONS - \brief unregister arc4 driver -*/ + \brief unregister arc4 driver +*/ void ifxdeu_fini_arc4(void) { crypto_unregister_alg (&ifxdeu_arc4_alg); diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_async_aes.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_async_aes.c index 8184fed71fa..e05faa4f3a4 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_async_aes.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_async_aes.c @@ -136,7 +136,7 @@ struct aes_container { u32 nbytes; struct ablkcipher_request arequest; - + }; aes_priv_t *aes_queue; @@ -149,7 +149,7 @@ void hexdump(unsigned char *buf, unsigned int len) buf, len, false); } -/*! \fn void lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, +/*! \fn void lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode) * \ingroup IFX_AES_FUNCTIONS * \brief main interface to AES hardware @@ -226,7 +226,7 @@ static int lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, AES_DMA_MISC_CONFIG(); aes->controlr.E_D = !encdec; //encryption - aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR + aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps if (mode > 0) { @@ -240,8 +240,8 @@ static int lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, /* Prepare Rx buf length used in dma psuedo interrupt */ deu_priv->deu_rx_buf = (u32 *)out_arg; deu_priv->deu_rx_len = nbytes; - - /* memory alignment issue */ + + /* memory alignment issue */ dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, aes_buff_in, BUFFER_IN, nbytes); dma->controlr.ALGO = 1; //AES @@ -274,16 +274,16 @@ static int lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2)); *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3)); } - - return -EINPROGRESS; + + return -EINPROGRESS; } /* \fn static int count_sgs(struct scatterlist *sl, unsigned int total_bytes) * \ingroup IFX_AES_FUNCTIONS - * \brief Counts and return the number of scatterlists + * \brief Counts and return the number of scatterlists * \param *sl Function pointer to the scatterlist * \param total_bytes The total number of bytes that needs to be encrypted/decrypted - * \return The number of scatterlists + * \return The number of scatterlists */ static int count_sgs(struct scatterlist *sl, unsigned int total_bytes) @@ -302,7 +302,7 @@ static int count_sgs(struct scatterlist *sl, unsigned int total_bytes) /* \fn void lq_sg_init(struct scatterlist *src, * struct scatterlist *dst) * \ingroup IFX_AES_FUNCTIONS - * \brief Maps the scatterlists into a source/destination page. + * \brief Maps the scatterlists into a source/destination page. * \param *src Pointer to the source scatterlist * \param *dst Pointer to the destination scatterlist */ @@ -322,12 +322,12 @@ static void lq_sg_init(struct aes_container *aes_con,struct scatterlist *src, } -/* \fn static void lq_sg_complete(struct aes_container *aes_con) +/* \fn static void lq_sg_complete(struct aes_container *aes_con) * \ingroup IFX_AES_FUNCTIONS * \brief Free the used up memory after encryt/decrypt. */ -static void lq_sg_complete(struct aes_container *aes_con) +static void lq_sg_complete(struct aes_container *aes_con) { unsigned long queue_flag; @@ -355,9 +355,9 @@ static inline struct aes_container *aes_container_cast ( * \ingroup IFX_AES_FUNCTIONS * \brief Process next packet to be encrypt/decrypt * \param *aes_con AES container structure - * \param *areq Pointer to memory location where ablkcipher_request is located + * \param *areq Pointer to memory location where ablkcipher_request is located * \param state The state of the current packet (part of scatterlist or new packet) - * \return -EINVAL: error, -EINPROGRESS: Crypto still running, 1: no more scatterlist + * \return -EINVAL: error, -EINPROGRESS: Crypto still running, 1: no more scatterlist */ static int process_next_packet(struct aes_container *aes_con, struct ablkcipher_request *areq, @@ -377,17 +377,17 @@ static int process_next_packet(struct aes_container *aes_con, struct ablkcipher_ dir = aes_con->encdec; mode = aes_con->mode; iv = aes_con->iv; - + if (state & PROCESS_SCATTER) { src = scatterwalk_sg_next(areq->src); dst = scatterwalk_sg_next(areq->dst); - + if (!src || !dst) { spin_unlock_irqrestore(&aes_queue->lock, queue_flag); return 1; } } - else if (state & PROCESS_NEW_PACKET) { + else if (state & PROCESS_NEW_PACKET) { src = areq->src; dst = areq->dst; } @@ -404,7 +404,7 @@ static int process_next_packet(struct aes_container *aes_con, struct ablkcipher_ remain -= inc; aes_con->nbytes = inc; - + if (state & PROCESS_SCATTER) { aes_con->src_buf += aes_con->nbytes; aes_con->dst_buf += aes_con->nbytes; @@ -444,7 +444,7 @@ static int process_next_packet(struct aes_container *aes_con, struct ablkcipher_ * \ingroup IFX_AES_FUNCTIONS * \brief tasklet to signal the dequeuing of the next packet to be processed * \param unsigned long data Not used - * \return void + * \return void */ static void process_queue(unsigned long data) @@ -467,17 +467,17 @@ static int aes_crypto_thread (void *data) struct ablkcipher_request *areq = NULL; int err; unsigned long queue_flag; - + daemonize("lq_aes_thread"); printk("AES Queue Manager Starting\n"); while (1) { - DEU_WAIT_EVENT(deu_dma_priv.deu_thread_wait, AES_ASYNC_EVENT, + DEU_WAIT_EVENT(deu_dma_priv.deu_thread_wait, AES_ASYNC_EVENT, deu_dma_priv.aes_event_flags); spin_lock_irqsave(&aes_queue->lock, queue_flag); - + /* wait to prevent starting a crypto session before * exiting the dma interrupt thread. */ @@ -513,15 +513,15 @@ static int aes_crypto_thread (void *data) if (aes_con->bytes_processed == 0) { goto aes_done; } - + /* Process new packet or the next packet in a scatterlist */ if (aes_con->flag & PROCESS_NEW_PACKET) { aes_con->flag = PROCESS_SCATTER; err = process_next_packet(aes_con, areq, PROCESS_NEW_PACKET); } - else + else err = process_next_packet(aes_con, areq, PROCESS_SCATTER); - + if (err == -EINVAL) { areq->base.complete(&areq->base, err); lq_sg_complete(aes_con); @@ -529,31 +529,31 @@ static int aes_crypto_thread (void *data) } else if (err > 0) { printk("src/dst returned zero in func: %s\n", __func__); - goto aes_done; + goto aes_done; } - + continue; aes_done: //printk("debug line - %d, func: %s, qlen: %d\n", __LINE__, __func__, aes_queue->list.qlen); - areq->base.complete(&areq->base, 0); + areq->base.complete(&areq->base, 0); lq_sg_complete(aes_con); spin_lock_irqsave(&aes_queue->lock, queue_flag); if (aes_queue->list.qlen > 0) { spin_unlock_irqrestore(&aes_queue->lock, queue_flag); - tasklet_schedule(&aes_queue->aes_task); + tasklet_schedule(&aes_queue->aes_task); } else { aes_queue->hw_status = AES_IDLE; spin_unlock_irqrestore(&aes_queue->lock, queue_flag); } } //while(1) - + return 0; -} +} -/* \fn static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq, +/* \fn static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq, u8 *iv, int dir, int mode) * \ingroup IFX_AES_FUNCTIONS * \brief starts the process of queuing DEU requests @@ -565,18 +565,18 @@ aes_done: * \return 0 if success */ -static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq, +static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq, u8 *iv, int dir, int mode) { - int err = -EINVAL; + int err = -EINVAL; unsigned long queue_flag; struct scatterlist *src = areq->src; struct scatterlist *dst = areq->dst; struct aes_container *aes_con = NULL; u32 remain, inc, nbytes = areq->nbytes; u32 chunk_bytes = src->length; - - + + aes_con = (struct aes_container *)kmalloc(sizeof(struct aes_container), GFP_KERNEL); @@ -600,15 +600,15 @@ static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq //printk("debug - Line: %d, func: %s, reqsize: %d, scattersize: %d\n", // __LINE__, __func__, nbytes, chunk_bytes); - if (remain > DEU_MAX_PACKET_SIZE) + if (remain > DEU_MAX_PACKET_SIZE) inc = DEU_MAX_PACKET_SIZE; else if (remain > chunk_bytes) - inc = chunk_bytes; + inc = chunk_bytes; else inc = remain; - + remain -= inc; - lq_sg_init(aes_con, src, dst); + lq_sg_init(aes_con, src, dst); if (remain <= 0) aes_con->complete = 1; @@ -619,7 +619,7 @@ static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq aes_con->iv = iv; aes_con->mode = mode; aes_con->encdec = dir; - + spin_lock_irqsave(&aes_queue->lock, queue_flag); if (aes_queue->hw_status == AES_STARTED || aes_queue->hw_status == AES_BUSY || @@ -638,12 +638,12 @@ static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq spin_unlock_irqrestore(&aes_queue->lock, queue_flag); return -EINPROGRESS; } - else if (aes_queue->hw_status == AES_IDLE) + else if (aes_queue->hw_status == AES_IDLE) aes_queue->hw_status = AES_STARTED; aes_con->flag = PROCESS_SCATTER; aes_con->bytes_processed -= aes_con->nbytes; - /* or enqueue the whole structure so as to get back the info + /* or enqueue the whole structure so as to get back the info * at the moment that it's queued. nbytes might be different */ err = ablkcipher_enqueue_request(&aes_queue->list, &aes_con->arequest); @@ -671,7 +671,7 @@ static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq static int aes_setkey(struct crypto_ablkcipher *tfm, const u8 *in_key, unsigned int keylen) { - struct aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + struct aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); unsigned long *flags = (unsigned long *) &tfm->base.crt_flags; DPRINTF(2, "set_key in %s\n", __FILE__); @@ -790,7 +790,7 @@ static int ecb_aes_encrypt (struct ablkcipher_request *areq) * \brief Decrypt function for AES algo * \param *areq Pointer to ablkcipher request in memory * \return 0 is success, -EINPROGRESS if encryting, EINVAL if failure -*/ +*/ static int ecb_aes_decrypt(struct ablkcipher_request *areq) { @@ -864,7 +864,7 @@ static int cfb_aes_decrypt(struct ablkcipher_request *areq) return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 3); } -#endif +#endif /* \fn static int ctr_aes_encrypt(struct ablkcipher_request *areq) * \ingroup IFX_AES_FUNCTIONS @@ -877,7 +877,7 @@ static int ctr_aes_encrypt (struct ablkcipher_request *areq) { struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher); - + return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 4); } @@ -998,7 +998,7 @@ static struct lq_aes_alg aes_drivers_alg[] = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = AES_BLOCK_SIZE, - } + } } },{ .alg = { @@ -1073,7 +1073,7 @@ static struct lq_aes_alg aes_drivers_alg[] = { int __init lqdeu_async_aes_init (void) { - int i, j, ret = -EINVAL; + int i, j, ret = -EINVAL; #define IFX_DEU_DRV_VERSION "2.0.0" printk(KERN_INFO "Lantiq Technologies DEU Driver version %s\n", IFX_DEU_DRV_VERSION); @@ -1090,16 +1090,16 @@ int __init lqdeu_async_aes_init (void) CRTCL_SECT_INIT; - printk (KERN_NOTICE "Lantiq DEU AES initialized %s %s.\n", + printk (KERN_NOTICE "Lantiq DEU AES initialized %s %s.\n", disable_multiblock ? "" : " (multiblock)", disable_deudma ? "" : " (DMA)"); - + return ret; aes_err: - - for (j = 0; j < i; j++) + + for (j = 0; j < i; j++) crypto_unregister_alg(&aes_drivers_alg[j].alg); - + printk(KERN_ERR "Lantiq %s driver initialization failed!\n", (char *)&aes_drivers_alg[i].alg.cra_driver_name); return ret; @@ -1119,15 +1119,15 @@ ctr_rfc3686_aes_err: void __exit lqdeu_fini_async_aes (void) { int i; - + for (i = 0; i < ARRAY_SIZE(aes_drivers_alg); i++) crypto_unregister_alg(&aes_drivers_alg[i].alg); aes_queue->hw_status = AES_COMPLETED; DEU_WAKEUP_EVENT(deu_dma_priv.deu_thread_wait, AES_ASYNC_EVENT, - deu_dma_priv.aes_event_flags); + deu_dma_priv.aes_event_flags); - kfree(aes_queue); + kfree(aes_queue); } diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_async_des.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_async_des.c index bd560bf6596..4a1988dd3fa 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_async_des.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_async_des.c @@ -258,7 +258,7 @@ static int lq_deu_des_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, /* memory alignment issue */ dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, des_buff_in, BUFFER_IN, nbytes); - + deu_priv->deu_rx_buf = (u32 *) out_arg; deu_priv->deu_rx_len = nbytes; @@ -283,13 +283,13 @@ static int lq_deu_des_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, des_buff_out, BUFFER_OUT, nbytes); deu_priv->outcopy = outcopy; deu_priv->event_src = DES_ASYNC_EVENT; - + if (mode > 0) { *(u32 *) iv_arg = DEU_ENDIAN_SWAP(des->IVHR); *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(des->IVLR); }; - CRTCL_SECT_END; + CRTCL_SECT_END; return -EINPROGRESS; @@ -330,9 +330,9 @@ static inline struct des_container *des_container_cast( static void lq_sg_complete(struct des_container *des_con) { unsigned long queue_flag; - + spin_lock_irqsave(&des_queue->lock, queue_flag); - kfree(des_con); + kfree(des_con); spin_unlock_irqrestore(&des_queue->lock, queue_flag); } @@ -367,7 +367,7 @@ static void lq_sg_init(struct des_container *des_con, struct scatterlist *src, */ static int process_next_packet(struct des_container *des_con, struct ablkcipher_request *areq, - int state) + int state) { u8 *iv; int mode, encdec, err = -EINVAL; @@ -401,7 +401,7 @@ static int process_next_packet(struct des_container *des_con, struct ablkcipher remain = des_con->bytes_processed; chunk_size = src->length; - //printk("debug ln: %d, func: %s, reqsize: %d, scattersize: %d\n", + //printk("debug ln: %d, func: %s, reqsize: %d, scattersize: %d\n", // __LINE__, __func__, areq->nbytes, chunk_size); if (remain > DEU_MAX_PACKET_SIZE) @@ -410,14 +410,14 @@ static int process_next_packet(struct des_container *des_con, struct ablkcipher inc = chunk_size; else inc = remain; - + remain -= inc; des_con->nbytes = inc; - + if (state & PROCESS_SCATTER) { des_con->src_buf += des_con->nbytes; des_con->dst_buf += des_con->nbytes; - } + } lq_sg_init(des_con, src, dst); @@ -429,7 +429,7 @@ static int process_next_packet(struct des_container *des_con, struct ablkcipher if (des_queue->hw_status == DES_IDLE) { des_queue->hw_status = DES_STARTED; } - + des_con->bytes_processed -= des_con->nbytes; err = ablkcipher_enqueue_request(&des_queue->list, &des_con->arequest); if (err == -EBUSY) { @@ -441,7 +441,7 @@ static int process_next_packet(struct des_container *des_con, struct ablkcipher spin_unlock_irqrestore(&des_queue->lock, queue_flag); err = lq_deu_des_core(ctx, des_con->dst_buf, des_con->src_buf, iv, nbytes, encdec, mode); - + return err; } @@ -449,7 +449,7 @@ static int process_next_packet(struct des_container *des_con, struct ablkcipher * \ingroup IFX_DES_FUNCTIONS * \brief Process next packet in queue * \param data not used - * \return + * \return */ static void process_queue(unsigned long data) @@ -474,17 +474,17 @@ static int des_crypto_thread(void *data) unsigned long queue_flag; daemonize("lq_des_thread"); - + while (1) - { - DEU_WAIT_EVENT(deu_dma_priv.deu_thread_wait, DES_ASYNC_EVENT, + { + DEU_WAIT_EVENT(deu_dma_priv.deu_thread_wait, DES_ASYNC_EVENT, deu_dma_priv.des_event_flags); spin_lock_irqsave(&des_queue->lock, queue_flag); - /* wait to prevent starting a crypto session before + /* wait to prevent starting a crypto session before * exiting the dma interrupt thread. */ - + if (des_queue->hw_status == DES_STARTED) { areq = ablkcipher_dequeue_request(&des_queue->list); des_con = des_container_cast(areq); @@ -507,7 +507,7 @@ static int des_crypto_thread(void *data) return 0; } spin_unlock_irqrestore(&des_queue->lock, queue_flag); - + if ((des_con->bytes_processed == 0)) { goto des_done; } @@ -516,25 +516,25 @@ static int des_crypto_thread(void *data) goto des_done; } - if (des_con->flag & PROCESS_NEW_PACKET) { + if (des_con->flag & PROCESS_NEW_PACKET) { des_con->flag = PROCESS_SCATTER; - err = process_next_packet(des_con, areq, PROCESS_NEW_PACKET); + err = process_next_packet(des_con, areq, PROCESS_NEW_PACKET); } else - err = process_next_packet(des_con, areq, PROCESS_SCATTER); - + err = process_next_packet(des_con, areq, PROCESS_SCATTER); + if (err == -EINVAL) { areq->base.complete(&areq->base, err); lq_sg_complete(des_con); printk("src/dst returned -EINVAL in func: %s\n", __func__); } - else if (err > 0) { + else if (err > 0) { printk("src/dst returned zero in func: %s\n", __func__); goto des_done; } continue; - + des_done: //printk("debug line - %d, func: %s, qlen: %d\n", __LINE__, __func__, des_queue->list.qlen); areq->base.complete(&areq->base, 0); @@ -544,13 +544,13 @@ des_done: if (des_queue->list.qlen > 0) { spin_unlock_irqrestore(&des_queue->lock, queue_flag); tasklet_schedule(&des_queue->des_task); - } + } else { des_queue->hw_status = DES_IDLE; spin_unlock_irqrestore(&des_queue->lock, queue_flag); } } // while(1) - + return 0; } @@ -567,7 +567,7 @@ des_done: * \return 0 if success */ -static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, +static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, u8 *iv, int encdec, int mode) { int err = -EINVAL; @@ -577,8 +577,8 @@ static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, struct des_container *des_con = NULL; u32 remain, inc, nbytes = areq->nbytes; u32 chunk_bytes = src->length; - - des_con = (struct des_container *)kmalloc(sizeof(struct des_container), + + des_con = (struct des_container *)kmalloc(sizeof(struct des_container), GFP_KERNEL); if (!(des_con)) { @@ -586,7 +586,7 @@ static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, __func__, __LINE__); return -ENOMEM; } - + /* DES encrypt/decrypt mode */ if (mode == 5) { nbytes = DES_BLOCK_SIZE; @@ -598,26 +598,26 @@ static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, des_con->arequest = (*areq); remain = nbytes; - //printk("debug - Line: %d, func: %s, reqsize: %d, scattersize: %d\n", + //printk("debug - Line: %d, func: %s, reqsize: %d, scattersize: %d\n", // __LINE__, __func__, nbytes, chunk_bytes); - if (remain > DEU_MAX_PACKET_SIZE) + if (remain > DEU_MAX_PACKET_SIZE) inc = DEU_MAX_PACKET_SIZE; else if(remain > chunk_bytes) inc = chunk_bytes; - else + else inc = remain; - + remain -= inc; lq_sg_init(des_con, src, dst); - - if (remain <= 0 ) { + + if (remain <= 0 ) { des_con->complete = 1; } - else + else des_con->complete = 0; - - des_con->nbytes = inc; + + des_con->nbytes = inc; des_con->iv = iv; des_con->mode = mode; des_con->encdec = encdec; @@ -630,20 +630,20 @@ static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, des_con->flag = PROCESS_NEW_PACKET; err = ablkcipher_enqueue_request(&des_queue->list, &des_con->arequest); if (err == -EBUSY) { - spin_unlock_irqrestore(&des_queue->lock, queue_flag); + spin_unlock_irqrestore(&des_queue->lock, queue_flag); printk("Fail to enqueue ablkcipher request ln: %d, err: %d\n", __LINE__, err); return err; } - spin_unlock_irqrestore(&des_queue->lock, queue_flag); + spin_unlock_irqrestore(&des_queue->lock, queue_flag); return -EINPROGRESS; - + } else if (des_queue->hw_status == DES_IDLE) { - des_queue->hw_status = DES_STARTED; + des_queue->hw_status = DES_STARTED; } - + des_con->flag = PROCESS_SCATTER; des_con->bytes_processed -= des_con->nbytes; @@ -655,8 +655,8 @@ static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, spin_unlock_irqrestore(&des_queue->lock, queue_flag); return err; } - - spin_unlock_irqrestore(&des_queue->lock, queue_flag); + + spin_unlock_irqrestore(&des_queue->lock, queue_flag); return lq_deu_des_core(ctx, des_con->dst_buf, des_con->src_buf, iv, inc, encdec, mode); } @@ -667,7 +667,7 @@ static int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, * \param *areq Pointer to ablkcipher request in memory * \return 0 is success, -EINPROGRESS if encryting, EINVAL if failure */ - + static int lq_des_encrypt(struct ablkcipher_request *areq) { struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); @@ -761,7 +761,7 @@ static struct lq_des_alg des_drivers_alg [] = { .alg = { .cra_name = "des", .cra_driver_name = "lqdeu-des", - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct des_ctx), .cra_type = &crypto_ablkcipher_type, @@ -782,7 +782,7 @@ static struct lq_des_alg des_drivers_alg [] = { .alg = { .cra_name = "ecb(des)", .cra_driver_name = "lqdeu-ecb(des)", - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct des_ctx), .cra_type = &crypto_ablkcipher_type, @@ -802,7 +802,7 @@ static struct lq_des_alg des_drivers_alg [] = { .alg = { .cra_name = "cbc(des)", .cra_driver_name = "lqdeu-cbc(des)", - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct des_ctx), .cra_type = &crypto_ablkcipher_type, @@ -822,7 +822,7 @@ static struct lq_des_alg des_drivers_alg [] = { .alg = { .cra_name = "des3_ede", .cra_driver_name = "lqdeu-des3_ede", - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct des_ctx), .cra_type = &crypto_ablkcipher_type, @@ -842,7 +842,7 @@ static struct lq_des_alg des_drivers_alg [] = { .alg = { .cra_name = "ecb(des3_ede)", .cra_driver_name = "lqdeu-ecb(des3_ede)", - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct des_ctx), .cra_type = &crypto_ablkcipher_type, @@ -857,12 +857,12 @@ static struct lq_des_alg des_drivers_alg [] = { .max_keysize = DES3_EDE_KEY_SIZE, .ivsize = DES3_EDE_BLOCK_SIZE, } - } + } },{ .alg = { .cra_name = "cbc(des3_ede)", .cra_driver_name = "lqdeu-cbc(des3_ede)", - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct des_ctx), .cra_type = &crypto_ablkcipher_type, @@ -878,7 +878,7 @@ static struct lq_des_alg des_drivers_alg [] = { .ivsize = DES3_EDE_BLOCK_SIZE, } } - } + } }; /*! \fn int __init lqdeu_async_des_init (void) @@ -895,7 +895,7 @@ int __init lqdeu_async_des_init (void) if (ret) goto des_err; } - + des_chip_init(); CRTCL_SECT_INIT; @@ -904,7 +904,7 @@ int __init lqdeu_async_des_init (void) return ret; des_err: - for (j = 0; j < i; j++) + for (j = 0; j < i; j++) crypto_unregister_alg(&des_drivers_alg[i].alg); printk(KERN_ERR "Lantiq %s driver initialization failed!\n", (char *)&des_drivers_alg[i].alg.cra_driver_name); @@ -914,7 +914,7 @@ cbc_des3_ede_err: for (i = 0; i < ARRAY_SIZE(des_drivers_alg); i++) { if (!strcmp((char *)&des_drivers_alg[i].alg.cra_name, "cbc(des3_ede)")) crypto_unregister_alg(&des_drivers_alg[i].alg); - } + } printk(KERN_ERR "Lantiq %s driver initialization failed!\n", (char *)&des_drivers_alg[i].alg.cra_driver_name); return ret; @@ -927,14 +927,14 @@ cbc_des3_ede_err: void __exit lqdeu_fini_async_des (void) { int i; - + for (i = 0; i < ARRAY_SIZE(des_drivers_alg); i++) crypto_unregister_alg(&des_drivers_alg[i].alg); des_queue->hw_status = DES_COMPLETED; DEU_WAKEUP_EVENT(deu_dma_priv.deu_thread_wait, DES_ASYNC_EVENT, - deu_dma_priv.des_event_flags); - + deu_dma_priv.des_event_flags); + kfree(des_queue); } diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_des.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_des.c index fc376c4d895..3e4db763995 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_des.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_des.c @@ -54,7 +54,7 @@ #include #include "ifxmips_deu.h" -#if defined(CONFIG_DANUBE) +#if defined(CONFIG_DANUBE) #include "ifxmips_deu_danube.h" extern int ifx_danube_pre_1_4; #elif defined(CONFIG_AR9) @@ -68,9 +68,9 @@ extern int ifx_danube_pre_1_4; /* DMA specific header and variables */ #if 0 - #define CRTCL_SECT_INIT - #define CRTCL_SECT_START - #define CRTCL_SECT_END + #define CRTCL_SECT_INIT + #define CRTCL_SECT_START + #define CRTCL_SECT_END #else spinlock_t des_lock; #define CRTCL_SECT_INIT spin_lock_init(&des_lock) @@ -121,11 +121,11 @@ extern int disable_deudma; /*! \fn int des_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) * \ingroup IFX_DES_FUNCTIONS - * \brief sets DES key - * \param tfm linux crypto algo transform - * \param key input key - * \param keylen key length -*/ + * \brief sets DES key + * \param tfm linux crypto algo transform + * \param key input key + * \param keylen key length +*/ static int des_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) { @@ -168,15 +168,15 @@ static int des_setkey_skcipher (struct crypto_skcipher *tfm, const u8 *in_key, u /*! \fn void ifx_deu_des(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode) * \ingroup IFX_DES_FUNCTIONS - * \brief main interface to DES hardware - * \param ctx_arg crypto algo context - * \param out_arg output bytestream - * \param in_arg input bytestream - * \param iv_arg initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param mode operation mode such as ebc, cbc -*/ + * \brief main interface to DES hardware + * \param ctx_arg crypto algo context + * \param out_arg output bytestream + * \param in_arg input bytestream + * \param iv_arg initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param mode operation mode such as ebc, cbc +*/ void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode) @@ -188,7 +188,7 @@ void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg, int i = 0; int nblocks = 0; - + CRTCL_SECT_START; des->controlr.M = dctx->controlr_M; @@ -242,10 +242,10 @@ void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg, #ifdef CRYPTO_DEBUG printk ("ihr: %x\n", (*((u32 *) in_arg + i))); printk ("ilr: %x\n", (*((u32 *) in_arg + 1 + i))); -#endif +#endif des->IHR = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + i)); des->ILR = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + 1 + i)); /* start crypto */ - + while (des->controlr.BUS) { // this will not take long } @@ -256,7 +256,7 @@ void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg, } - + if (mode > 0) { *(u32 *) iv_arg = DEU_ENDIAN_SWAP(des->IVHR); *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(des->IVLR); @@ -275,26 +275,26 @@ void ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg, /*! \fn void ifx_deu_des(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode) * \ingroup IFX_DES_FUNCTIONS - * \brief main interface to DES hardware - * \param ctx_arg crypto algo context - * \param out_arg output bytestream - * \param in_arg input bytestream - * \param iv_arg initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param mode operation mode such as ebc, cbc -*/ + * \brief main interface to DES hardware + * \param ctx_arg crypto algo context + * \param out_arg output bytestream + * \param in_arg input bytestream + * \param iv_arg initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param mode operation mode such as ebc, cbc +*/ /*! \fn void ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_DES_FUNCTIONS - * \brief sets DES hardware to ECB mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used + * \brief sets DES hardware to ECB mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used */ static void ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) @@ -304,15 +304,15 @@ static void ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_DES_FUNCTIONS - * \brief sets DES hardware to CBC mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets DES hardware to CBC mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ static void ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) { @@ -321,15 +321,15 @@ static void ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_DES_FUNCTIONS - * \brief sets DES hardware to OFB mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets DES hardware to OFB mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ /* static void ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) @@ -340,15 +340,15 @@ static void ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) \ingroup IFX_DES_FUNCTIONS - \brief sets DES hardware to CFB mode - \param ctx crypto algo context - \param dst output bytestream - \param src input bytestream - \param iv initialization vector - \param nbytes length of bytestream - \param encdec 1 for encrypt; 0 for decrypt - \param inplace not used -*/ + \brief sets DES hardware to CFB mode + \param ctx crypto algo context + \param dst output bytestream + \param src input bytestream + \param iv initialization vector + \param nbytes length of bytestream + \param encdec 1 for encrypt; 0 for decrypt + \param inplace not used +*/ /* static void ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) @@ -359,15 +359,15 @@ static void ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) * \ingroup IFX_DES_FUNCTIONS - * \brief sets DES hardware to CTR mode - * \param ctx crypto algo context - * \param dst output bytestream - * \param src input bytestream - * \param iv initialization vector - * \param nbytes length of bytestream - * \param encdec 1 for encrypt; 0 for decrypt - * \param inplace not used -*/ + * \brief sets DES hardware to CTR mode + * \param ctx crypto algo context + * \param dst output bytestream + * \param src input bytestream + * \param iv initialization vector + * \param nbytes length of bytestream + * \param encdec 1 for encrypt; 0 for decrypt + * \param inplace not used +*/ /* void ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace) @@ -378,11 +378,11 @@ void ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src, /*! \fn void ifx_deu_des_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in) * \ingroup IFX_DES_FUNCTIONS - * \brief encrypt DES_BLOCK_SIZE of data - * \param tfm linux crypto algo transform - * \param out output bytestream - * \param in input bytestream -*/ + * \brief encrypt DES_BLOCK_SIZE of data + * \param tfm linux crypto algo transform + * \param out output bytestream + * \param in input bytestream +*/ static void ifx_deu_des_encrypt (struct crypto_tfm *tfm, uint8_t * out, const uint8_t * in) { struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(tfm); @@ -393,11 +393,11 @@ static void ifx_deu_des_encrypt (struct crypto_tfm *tfm, uint8_t * out, const ui /*! \fn void ifx_deu_des_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in) * \ingroup IFX_DES_FUNCTIONS - * \brief encrypt DES_BLOCK_SIZE of data - * \param tfm linux crypto algo transform - * \param out output bytestream - * \param in input bytestream -*/ + * \brief encrypt DES_BLOCK_SIZE of data + * \param tfm linux crypto algo transform + * \param out output bytestream + * \param in input bytestream +*/ static void ifx_deu_des_decrypt (struct crypto_tfm *tfm, uint8_t * out, const uint8_t * in) { struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(tfm); @@ -421,11 +421,11 @@ static void ifx_deu_des_decrypt (struct crypto_tfm *tfm, uint8_t * out, const ui /*! \fn int des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) * \ingroup IFX_DES_FUNCTIONS - * \brief sets 3DES key - * \param tfm linux crypto algo transform - * \param key input key - * \param keylen key length -*/ + * \brief sets 3DES key + * \param tfm linux crypto algo transform + * \param key input key + * \param keylen key length +*/ static int des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) { @@ -468,7 +468,7 @@ static int des3_ede_setkey_skcipher(struct crypto_skcipher *tfm, const u8 *key, /* * \brief DES function mappings -*/ +*/ struct crypto_alg ifxdeu_des_alg = { .cra_name = "des", .cra_driver_name = "ifxdeu-des", @@ -489,7 +489,7 @@ struct crypto_alg ifxdeu_des_alg = { /* * \brief DES function mappings -*/ +*/ struct crypto_alg ifxdeu_des3_ede_alg = { .cra_name = "des3_ede", .cra_driver_name = "ifxdeu-des3_ede", @@ -525,7 +525,7 @@ static int ecb_des_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes)) { enc_bytes -= (nbytes % DES_BLOCK_SIZE); - ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, NULL, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= DES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -552,7 +552,7 @@ static int ecb_des_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes)) { dec_bytes -= (nbytes % DES_BLOCK_SIZE); - ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, NULL, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= DES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -618,7 +618,7 @@ static int cbc_des_encrypt(struct skcipher_request *req) while ((nbytes = enc_bytes = walk.nbytes)) { u8 *iv = walk.iv; enc_bytes -= (nbytes % DES_BLOCK_SIZE); - ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0); nbytes &= DES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -646,7 +646,7 @@ static int cbc_des_decrypt(struct skcipher_request *req) while ((nbytes = dec_bytes = walk.nbytes)) { u8 *iv = walk.iv; dec_bytes -= (nbytes % DES_BLOCK_SIZE); - ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, + ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0); nbytes &= DES_BLOCK_SIZE - 1; err = skcipher_walk_done(&walk, nbytes); @@ -697,8 +697,8 @@ struct skcipher_alg ifxdeu_cbc_des3_ede_alg = { /*! \fn int ifxdeu_init_des (void) * \ingroup IFX_DES_FUNCTIONS - * \brief initialize des driver -*/ + * \brief initialize des driver +*/ int ifxdeu_init_des (void) { int ret = -ENOSYS; @@ -765,8 +765,8 @@ cbc_des3_ede_err: /*! \fn void ifxdeu_fini_des (void) * \ingroup IFX_DES_FUNCTIONS - * \brief unregister des driver -*/ + * \brief unregister des driver +*/ void ifxdeu_fini_des (void) { crypto_unregister_alg (&ifxdeu_des_alg); diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c index 684f3c4df0e..33157f89423 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c @@ -65,7 +65,7 @@ #include "ifxmips_deu_ar9.h" #elif defined(CONFIG_VR9) || defined(CONFIG_AR10) #include "ifxmips_deu_vr9.h" -#else +#else #error "Platform unknown!" #endif /* CONFIG_xxxx */ @@ -77,10 +77,10 @@ void chip_version(void); /*! \fn static int __init deu_init (void) * \ingroup IFX_DEU_FUNCTIONS - * \brief link all modules that have been selected in kernel config for ifx hw crypto support - * \return ret -*/ - + * \brief link all modules that have been selected in kernel config for ifx hw crypto support + * \return ret +*/ + static int ltq_deu_probe(struct platform_device *pdev) { int ret = -ENOSYS; @@ -88,7 +88,7 @@ static int ltq_deu_probe(struct platform_device *pdev) START_DEU_POWER; CRTCL_SECT_HASH_INIT; - + #define IFX_DEU_DRV_VERSION "2.0.0" printk(KERN_INFO "Infineon Technologies DEU driver version %s \n", IFX_DEU_DRV_VERSION); @@ -141,8 +141,8 @@ static int ltq_deu_probe(struct platform_device *pdev) /*! \fn static void __exit deu_fini (void) * \ingroup IFX_DEU_FUNCTIONS - * \brief remove the loaded crypto algorithms -*/ + * \brief remove the loaded crypto algorithms +*/ static void ltq_deu_remove(struct platform_device *pdev) { //#ifdef CONFIG_CRYPTO_DEV_PWR_SAVE_MODE diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.h b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.h index 3c994cb3465..63b68acafc9 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.h +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.h @@ -96,8 +96,8 @@ clc->DISR = 1; \ } while (0) -/* - * Not used anymore in UEIP (use IFX_DES_CON, IFX_AES_CON, etc instead) +/* + * Not used anymore in UEIP (use IFX_DES_CON, IFX_AES_CON, etc instead) * #define DEU_BASE (KSEG1+0x1E103100) * #define DES_CON (DEU_BASE+0x10) * #define AES_CON (DEU_BASE+0x50) @@ -153,7 +153,7 @@ extern spinlock_t ltq_deu_hash_lock; set_bit((event), &(flags)); \ wake_up_interruptible(&(queue)); \ }while (0) - + #define DEU_WAIT_EVENT(queue, event, flags) \ do { \ wait_event_interruptible(queue, \ @@ -184,7 +184,7 @@ typedef struct deu_drv_priv { * @lock: spinlock lock * @lock_flag: flag for spinlock activities * @list: crypto queue API list - * @hw_status: DEU hw status flag + * @hw_status: DEU hw status flag * @aes_wait_flag: flag for sleep queue * @aes_wait_queue: queue attributes for aes * @bytes_processed: number of bytes to process by DEU @@ -230,7 +230,7 @@ typedef struct { struct tasklet_struct des_task; } des_priv_t; - + #endif /* IFXMIPS_DEU_H */ diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.c index 9dc3e304278..a20ab989546 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.c @@ -31,8 +31,8 @@ \brief ifx deu board specific driver file for ar9 */ -/*! - \defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS +/*! + \defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS \ingroup IFX_DEU \brief board specific functions */ @@ -71,9 +71,9 @@ u8 *g_dma_block2 = NULL; deu_drv_priv_t deu_dma_priv; -/*! \fn u32 endian_swap(u32 input) +/*! \fn u32 endian_swap(u32 input) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief Swap data given to the function + * \brief Swap data given to the function * \param input Data input to be swapped * \return either the swapped data or the input data depending on whether it is in DMA mode or FPI mode */ @@ -84,7 +84,7 @@ u32 endian_swap(u32 input) /*! \fn u32 input_swap(u32 input) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief Not used + * \brief Not used * \return input */ @@ -95,7 +95,7 @@ u32 input_swap(u32 input) /*! \fn void aes_chip_init (void) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief initialize AES hardware + * \brief initialize AES hardware */ void aes_chip_init (void) @@ -110,8 +110,8 @@ void aes_chip_init (void) /*! \fn void des_chip_init (void) * \ingroup BOARD_SPECIFIC_FUNCTIONS * \brief initialize DES hardware -*/ - +*/ + void des_chip_init (void) { volatile struct des_t *des = (struct des_t *) DES_3DES_START; @@ -123,12 +123,12 @@ void des_chip_init (void) } -/*! \fn void chip_version(void) +/*! \fn void chip_version(void) * \ingroup BOARD_SPECIFIC_FUNCTIONS * \brief not used! -*/ +*/ -void chip_version(void) +void chip_version(void) { return; } diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.h b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.h index 324d20012b4..00fbf40f479 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.h +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.h @@ -65,9 +65,9 @@ #define INPUT_ENDIAN_SWAP(input) input_swap(input) #define DEU_ENDIAN_SWAP(input) endian_swap(input) -#define DELAY_PERIOD 10 +#define DELAY_PERIOD 10 #define FIND_DEU_CHIP_VERSION chip_version() -#define CLC_START IFX_DEU_CLK +#define CLC_START IFX_DEU_CLK #define AES_INIT 0 #define DES_INIT 1 @@ -79,7 +79,7 @@ #define AES_START IFX_AES_CON #define DES_3DES_START IFX_DES_CON - + #define WAIT_AES_DMA_READY() \ do { \ int i; \ @@ -126,7 +126,7 @@ } while(0) /* DEU Common Structures for AR9*/ - + struct clc_controlr_t { u32 Res:26; u32 FSOE:1; @@ -233,7 +233,7 @@ struct arc4_t { u32 reserved3:1; u32 ARS:1; u32 SM:1; - u32 reserved4:4; + u32 reserved4:4; } controlr; u32 K3R; //104h @@ -247,7 +247,7 @@ struct arc4_t { u32 ID2R; //11Ch u32 ID1R; //120h u32 ID0R; //124h - + u32 OD3R; //128h u32 OD2R; //12Ch u32 OD1R; //130h @@ -257,14 +257,14 @@ struct arc4_t { struct deu_hash_t { struct hash_controlr { u32 reserved1:5; - u32 KHS:1; + u32 KHS:1; u32 GO:1; u32 INIT:1; u32 reserved2:6; u32 NDC:1; u32 ENDI:1; u32 reserved3:7; - u32 DGRY:1; + u32 DGRY:1; u32 BSY:1; u32 reserved4:1; u32 IRCL:1; diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.c index 492391d414c..a5e563914e5 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.c @@ -52,14 +52,14 @@ /* Function Declerations */ int aes_memory_allocate(int value); int des_memory_allocate(int value); -void memory_release(u32 *addr); +void memory_release(u32 *addr); int aes_chip_init (void); void des_chip_init (void); int deu_dma_init (void); u32 endian_swap(u32 input); u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes); void dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes); -void chip_version(void); +void chip_version(void); void deu_dma_priv_init(void); void __exit ifxdeu_fini_dma(void); @@ -68,7 +68,7 @@ void __exit ifxdeu_fini_dma(void); #define CLC_START IFX_DEU_CLK /* Variables definition */ -int ifx_danube_pre_1_4; +int ifx_danube_pre_1_4; u8 *g_dma_page_ptr = NULL; u8 *g_dma_block = NULL; u8 *g_dma_block2 = NULL; @@ -76,7 +76,7 @@ u8 *g_dma_block2 = NULL; deu_drv_priv_t deu_dma_priv; -/*! \fn u32 endian_swap(u32 input) +/*! \fn u32 endian_swap(u32 input) * \ingroup BOARD_SPECIFIC_FUNCTIONS * \brief function is not used * \param input Data input to be swapped @@ -91,8 +91,8 @@ u32 endian_swap(u32 input) /*! \fn u32 input_swap(u32 input) * \ingroup BOARD_SPECIFIC_FUNCTIONS * \brief Swap the input data if the current chip is Danube version - * 1.4 and do nothing to the data if the current chip is - * Danube version 1.3 + * 1.4 and do nothing to the data if the current chip is + * Danube version 1.3 * \param input data that needs to be swapped * \return input or swapped input */ @@ -101,9 +101,9 @@ u32 input_swap(u32 input) { if (!ifx_danube_pre_1_4) { u8 *ptr = (u8 *)&input; - return ((ptr[3] << 24) | (ptr[2] << 16) | (ptr[1] << 8) | ptr[0]); + return ((ptr[3] << 24) | (ptr[2] << 16) | (ptr[1] << 8) | ptr[0]); } - else + else return input; } @@ -111,7 +111,7 @@ u32 input_swap(u32 input) /*! \fn void aes_chip_init (void) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief initialize AES hardware + * \brief initialize AES hardware */ int aes_chip_init (void) @@ -127,8 +127,8 @@ int aes_chip_init (void) /*! \fn void des_chip_init (void) * \ingroup BOARD_SPECIFIC_FUNCTIONS * \brief initialize DES hardware -*/ - +*/ + void des_chip_init (void) { volatile struct des_t *des = (struct des_t *) DES_3DES_START; @@ -142,11 +142,11 @@ void des_chip_init (void) * \ingroup IFX_DES_FUNCTIONS * \brief To find the version of the chip by looking at the chip ID * \param ifx_danube_pre_1_4 (sets to 1 if Chip is Danube less than v1.4) -*/ +*/ #define IFX_MPS (KSEG1 | 0x1F107000) #define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -void chip_version(void) +void chip_version(void) { /* DANUBE PRE 1.4 SOFTWARE FIX */ @@ -159,7 +159,7 @@ void chip_version(void) printk("Danube Chip ver. 1.4 detected. \n"); } else { - ifx_danube_pre_1_4 = 1; + ifx_danube_pre_1_4 = 1; printk("Danube Chip ver. 1.3 or below detected. \n"); } diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.h b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.h index eb2f749bb31..9daef9d2d71 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.h +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.h @@ -71,7 +71,7 @@ #define AES_INIT 0 #define DES_INIT 1 -#define SHA1_INIT 2 +#define SHA1_INIT 2 #define MD5_INIT 3 #define WAIT_AES_DMA_READY() \ @@ -94,7 +94,7 @@ udelay(DELAY_PERIOD); \ while (dma->controlr.BSY) {}; \ while (des->controlr.BUS) {}; \ - } while (0) + } while (0) #define SHA_HASH_INIT \ do { \ @@ -167,12 +167,12 @@ struct aes_t { u32 PNK:1; u32 GO:1; u32 STP:1; - + u32 reserved2:6; u32 NDC:1; - u32 ENDI:1; + u32 ENDI:1; u32 reserved3:2; - + u32 F:3; //fbs u32 O:3; //om u32 BUS:1; //bsy @@ -209,14 +209,14 @@ struct aes_t { struct deu_hash_t { struct hash_controlr { u32 reserved1:5; - u32 KHS:1; + u32 KHS:1; u32 GO:1; u32 INIT:1; u32 reserved2:6; u32 NDC:1; u32 ENDI:1; u32 reserved3:7; - u32 DGRY:1; + u32 DGRY:1; u32 BSY:1; u32 reserved4:1; u32 IRCL:1; diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_dma.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_dma.c index 13dc921f7d0..6758a4f1ed3 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_dma.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_dma.c @@ -29,7 +29,7 @@ /*! \file ifxmips_deu_dma.c \ingroup IFX_DEU - \brief DMA deu driver file + \brief DMA deu driver file */ /*! @@ -38,5 +38,5 @@ \brief deu-dma driver functions */ -/* Project header files */ +/* Project header files */ diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c index 8063672613a..ab5c04c2c76 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c @@ -72,9 +72,9 @@ u8 *g_dma_block2 = NULL; deu_drv_priv_t deu_dma_priv; -/*! \fn u32 endian_swap(u32 input) +/*! \fn u32 endian_swap(u32 input) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief Swap data given to the function + * \brief Swap data given to the function * \param input Data input to be swapped * \return either the swapped data or the input data depending on whether it is in DMA mode or FPI mode */ @@ -87,7 +87,7 @@ u32 endian_swap(u32 input) /*! \fn u32 input_swap(u32 input) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief Not used + * \brief Not used * \return input */ @@ -98,7 +98,7 @@ u32 input_swap(u32 input) /*! \fn void aes_chip_init (void) * \ingroup BOARD_SPECIFIC_FUNCTIONS - * \brief initialize AES hardware + * \brief initialize AES hardware */ void aes_chip_init (void) @@ -112,14 +112,14 @@ void aes_chip_init (void) aes->controlr.ENDI = 1; asm("sync"); aes->controlr.ARS = 0; - + } /*! \fn void des_chip_init (void) * \ingroup IFX_AES_FUNCTIONS * \brief initialize DES hardware -*/ - +*/ + void des_chip_init (void) { volatile struct des_t *des = (struct des_t *) DES_3DES_START; @@ -129,7 +129,7 @@ void des_chip_init (void) des->controlr.NDC = 1; asm("sync"); des->controlr.ENDI = 1; - asm("sync"); + asm("sync"); des->controlr.ARS = 0; } @@ -137,7 +137,7 @@ void des_chip_init (void) * \ingroup IFX_DES_FUNCTIONS * \brief function not used in VR9 */ -void chip_version(void) +void chip_version(void) { return; } diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.h b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.h index 235a393e7f4..1107df96de6 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.h +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.h @@ -87,14 +87,14 @@ #define INPUT_ENDIAN_SWAP(input) input_swap(input) #define DEU_ENDIAN_SWAP(input) endian_swap(input) -#define FIND_DEU_CHIP_VERSION chip_version() +#define FIND_DEU_CHIP_VERSION chip_version() #if defined (CONFIG_AR10) #define DELAY_PERIOD 30 #else #define DELAY_PERIOD 10 #endif - + #define WAIT_AES_DMA_READY() \ do { \ int i; \ @@ -143,7 +143,7 @@ } while(0) /* DEU Common Structures for AR9*/ - + struct clc_controlr_t { u32 Res:26; u32 FSOE:1; @@ -250,7 +250,7 @@ struct arc4_t { u32 reserved3:1; u32 ARS:1; u32 SM:1; - u32 reserved4:4; + u32 reserved4:4; } controlr; u32 K3R; //104h @@ -264,7 +264,7 @@ struct arc4_t { u32 ID2R; //11Ch u32 ID1R; //120h u32 ID0R; //124h - + u32 OD3R; //128h u32 OD2R; //12Ch u32 OD1R; //130h @@ -274,14 +274,14 @@ struct arc4_t { struct deu_hash_t { struct hash_controlr { u32 reserved1:5; - u32 KHS:1; + u32 KHS:1; u32 GO:1; u32 INIT:1; u32 reserved2:6; u32 NDC:1; u32 ENDI:1; u32 reserved3:7; - u32 DGRY:1; + u32 DGRY:1; u32 BSY:1; u32 reserved4:1; u32 IRCL:1; diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_md5.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_md5.c index ee7e486b565..80ff41a7383 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_md5.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_md5.c @@ -29,7 +29,7 @@ /*! \file ifxmips_md5.c \ingroup IFX_DEU - \brief MD5 encryption deu driver file + \brief MD5 encryption deu driver file */ /*! @@ -83,10 +83,10 @@ extern int disable_deudma; /*! \fn static void md5_transform(u32 *hash, u32 const *in) * \ingroup IFX_MD5_FUNCTIONS - * \brief main interface to md5 hardware - * \param hash current hash value - * \param in 64-byte block of input -*/ + * \brief main interface to md5 hardware + * \param hash current hash value + * \param in 64-byte block of input +*/ static void md5_transform(struct md5_ctx *mctx, u32 *hash, u32 const *in) { int i; @@ -97,7 +97,7 @@ static void md5_transform(struct md5_ctx *mctx, u32 *hash, u32 const *in) MD5_HASH_INIT; - if (mctx->started) { + if (mctx->started) { hashs->D1R = *((u32 *) hash + 0); hashs->D2R = *((u32 *) hash + 1); hashs->D3R = *((u32 *) hash + 2); @@ -126,9 +126,9 @@ static void md5_transform(struct md5_ctx *mctx, u32 *hash, u32 const *in) /*! \fn static inline void md5_transform_helper(struct md5_ctx *ctx) * \ingroup IFX_MD5_FUNCTIONS - * \brief interfacing function for md5_transform() - * \param ctx crypto context -*/ + * \brief interfacing function for md5_transform() + * \param ctx crypto context +*/ static inline void md5_transform_helper(struct md5_ctx *ctx) { //le32_to_cpu_array(ctx->block, sizeof(ctx->block) / sizeof(u32)); @@ -137,9 +137,9 @@ static inline void md5_transform_helper(struct md5_ctx *ctx) /*! \fn static void md5_init(struct crypto_tfm *tfm) * \ingroup IFX_MD5_FUNCTIONS - * \brief initialize md5 hardware - * \param tfm linux crypto algo transform -*/ + * \brief initialize md5 hardware + * \param tfm linux crypto algo transform +*/ static int md5_init(struct shash_desc *desc) { struct md5_ctx *mctx = shash_desc_ctx(desc); @@ -152,11 +152,11 @@ static int md5_init(struct shash_desc *desc) /*! \fn static void md5_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len) * \ingroup IFX_MD5_FUNCTIONS - * \brief on-the-fly md5 computation - * \param tfm linux crypto algo transform - * \param data input data - * \param len size of input data -*/ + * \brief on-the-fly md5 computation + * \param tfm linux crypto algo transform + * \param data input data + * \param len size of input data +*/ static int md5_update(struct shash_desc *desc, const u8 *data, unsigned int len) { struct md5_ctx *mctx = shash_desc_ctx(desc); @@ -190,10 +190,10 @@ static int md5_update(struct shash_desc *desc, const u8 *data, unsigned int len) /*! \fn static void md5_final(struct crypto_tfm *tfm, u8 *out) * \ingroup IFX_MD5_FUNCTIONS - * \brief compute final md5 value - * \param tfm linux crypto algo transform - * \param out final md5 output value -*/ + * \brief compute final md5 value + * \param tfm linux crypto algo transform + * \param out final md5 output value +*/ static int md5_final(struct shash_desc *desc, u8 *out) { struct md5_ctx *mctx = shash_desc_ctx(desc); @@ -215,7 +215,7 @@ static int md5_final(struct shash_desc *desc, u8 *out) mctx->block[14] = le32_to_cpu(mctx->byte_count << 3); mctx->block[15] = le32_to_cpu(mctx->byte_count >> 29); - md5_transform(mctx, mctx->hash, mctx->block); + md5_transform(mctx, mctx->hash, mctx->block); memcpy(out, mctx->hash, MD5_DIGEST_SIZE); @@ -246,8 +246,8 @@ static struct shash_alg ifxdeu_md5_alg = { /*! \fn int ifxdeu_init_md5 (void) * \ingroup IFX_MD5_FUNCTIONS - * \brief initialize md5 driver -*/ + * \brief initialize md5 driver +*/ int ifxdeu_init_md5 (void) { int ret = -ENOSYS; @@ -266,9 +266,9 @@ md5_err: /*! \fn void ifxdeu_fini_md5 (void) * \ingroup IFX_MD5_FUNCTIONS - * \brief unregister md5 driver -*/ - + * \brief unregister md5 driver +*/ + void ifxdeu_fini_md5 (void) { crypto_unregister_shash(&ifxdeu_md5_alg); diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_md5_hmac.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_md5_hmac.c index 109d27cbfbe..51a623b73d9 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_md5_hmac.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_md5_hmac.c @@ -60,7 +60,7 @@ #define MD5_HMAC_BLOCK_SIZE 64 #define MD5_BLOCK_WORDS 16 #define MD5_HASH_WORDS 4 -#define MD5_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround +#define MD5_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround #define HASH_START IFX_HASH_CON //#define CRYPTO_DEBUG @@ -91,10 +91,10 @@ static int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final /*! \fn static void md5_hmac_transform(struct crypto_tfm *tfm, u32 const *in) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief save input block to context - * \param tfm linux crypto algo transform - * \param in 64-byte block of input -*/ + * \brief save input block to context + * \param tfm linux crypto algo transform + * \param in 64-byte block of input +*/ static void md5_hmac_transform(struct shash_desc *desc, u32 const *in) { struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm); @@ -111,12 +111,12 @@ static void md5_hmac_transform(struct shash_desc *desc, u32 const *in) /*! \fn int md5_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief sets md5 hmac key - * \param tfm linux crypto algo transform - * \param key input key - * \param keylen key length greater than 64 bytes IS NOT SUPPORTED -*/ -static int md5_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen) + * \brief sets md5 hmac key + * \param tfm linux crypto algo transform + * \param key input key + * \param keylen key length greater than 64 bytes IS NOT SUPPORTED +*/ +static int md5_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen) { struct md5_hmac_ctx *mctx = crypto_shash_ctx(tfm); int err; @@ -146,25 +146,25 @@ static int md5_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int /*! \fn int md5_hmac_setkey_hw(const u8 *key, unsigned int keylen) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief sets md5 hmac key into the hardware registers - * \param key input key - * \param keylen key length greater than 64 bytes IS NOT SUPPORTED -*/ + * \brief sets md5 hmac key into the hardware registers + * \param key input key + * \param keylen key length greater than 64 bytes IS NOT SUPPORTED +*/ static int md5_hmac_setkey_hw(const u8 *key, unsigned int keylen) { volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; int i, j; - u32 *in_key = (u32 *)key; + u32 *in_key = (u32 *)key; //printk("\nsetkey keylen: %d\n key: ", keylen); - + hash->KIDX |= 0x80000000; // reset all 16 words of the key to '0' j = 0; for (i = 0; i < keylen; i+=4) { hash->KIDX = j; asm("sync"); - hash->KEY = *((u32 *) in_key + j); + hash->KEY = *((u32 *) in_key + j); asm("sync"); j++; } @@ -174,14 +174,14 @@ static int md5_hmac_setkey_hw(const u8 *key, unsigned int keylen) /*! \fn void md5_hmac_init(struct crypto_tfm *tfm) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief initialize md5 hmac context - * \param tfm linux crypto algo transform -*/ + * \brief initialize md5 hmac context + * \param tfm linux crypto algo transform +*/ static int md5_hmac_init(struct shash_desc *desc) { struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm); - + mctx->dbn = 0; //dbn workaround mctx->started = 0; @@ -189,21 +189,21 @@ static int md5_hmac_init(struct shash_desc *desc) return 0; } - + /*! \fn void md5_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief on-the-fly md5 hmac computation - * \param tfm linux crypto algo transform - * \param data input data - * \param len size of input data -*/ + * \brief on-the-fly md5 hmac computation + * \param tfm linux crypto algo transform + * \param data input data + * \param len size of input data +*/ static int md5_hmac_update(struct shash_desc *desc, const u8 *data, unsigned int len) { struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm); const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f); mctx->byte_count += len; - + if (avail > len) { memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), data, len); @@ -225,15 +225,15 @@ static int md5_hmac_update(struct shash_desc *desc, const u8 *data, unsigned int } memcpy(mctx->block, data, len); - return 0; + return 0; } /*! \fn static int md5_hmac_final(struct crypto_tfm *tfm, u8 *out) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief call md5_hmac_final_impl with hash_final true - * \param tfm linux crypto algo transform - * \param out final md5 hmac output value -*/ + * \brief call md5_hmac_final_impl with hash_final true + * \param tfm linux crypto algo transform + * \param out final md5 hmac output value +*/ static int md5_hmac_final(struct shash_desc *desc, u8 *out) { return md5_hmac_final_impl(desc, out, true); @@ -241,11 +241,11 @@ static int md5_hmac_final(struct shash_desc *desc, u8 *out) /*! \fn static int md5_hmac_final_impl(struct crypto_tfm *tfm, u8 *out, bool hash_final) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief compute final or intermediate md5 hmac value - * \param tfm linux crypto algo transform - * \param out final md5 hmac output value - * \param in finalize or intermediate processing -*/ + * \brief compute final or intermediate md5 hmac value + * \param tfm linux crypto algo transform + * \param out final md5 hmac output value + * \param in finalize or intermediate processing +*/ static int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final) { struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm); @@ -268,7 +268,7 @@ static int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final } memset(p, 0, padding); - mctx->block[14] = le32_to_cpu((mctx->byte_count + 64) << 3); // need to add 512 bit of the IPAD operation + mctx->block[14] = le32_to_cpu((mctx->byte_count + 64) << 3); // need to add 512 bit of the IPAD operation mctx->block[15] = 0x00000000; md5_hmac_transform(desc, mctx->block); @@ -280,15 +280,15 @@ static int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final md5_hmac_setkey_hw(mctx->key, mctx->keylen); - //printk("\ndbn = %d\n", mctx->dbn); + //printk("\ndbn = %d\n", mctx->dbn); if (hash_final) { hashs->DBN = mctx->dbn; } else { hashs->DBN = mctx->dbn + 5; } asm("sync"); - - *IFX_HASH_CON = 0x0703002D; //khs, go, init, ndc, endi, kyue, hmen, md5 + + *IFX_HASH_CON = 0x0703002D; //khs, go, init, ndc, endi, kyue, hmen, md5 //wait for processing while (hashs->controlr.BSY) { @@ -317,7 +317,7 @@ static int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final while (hashs->controlr.BSY) { // this will not take long } - + in += 16; } @@ -374,7 +374,7 @@ static void md5_hmac_exit_tfm(struct crypto_tfm *tfm) kfree(mctx->desc); } -/* +/* * \brief MD5_HMAC function mappings */ static struct shash_alg ifxdeu_md5_hmac_alg = { @@ -399,8 +399,8 @@ static struct shash_alg ifxdeu_md5_hmac_alg = { /*! \fn int ifxdeu_init_md5_hmac (void) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief initialize md5 hmac driver -*/ + * \brief initialize md5 hmac driver +*/ int ifxdeu_init_md5_hmac (void) { @@ -420,8 +420,8 @@ md5_hmac_err: /** \fn void ifxdeu_fini_md5_hmac (void) * \ingroup IFX_MD5_HMAC_FUNCTIONS - * \brief unregister md5 hmac driver -*/ + * \brief unregister md5 hmac driver +*/ void ifxdeu_fini_md5_hmac (void) { crypto_unregister_shash(&ifxdeu_md5_hmac_alg); diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c index 76734917d1e..f67f45531f5 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c @@ -92,10 +92,10 @@ extern int disable_deudma; /*! \fn static void sha1_transform1 (u32 *state, const u32 *in) * \ingroup IFX_SHA1_FUNCTIONS - * \brief main interface to sha1 hardware - * \param state current state - * \param in 64-byte block of input -*/ + * \brief main interface to sha1 hardware + * \param state current state + * \param in 64-byte block of input +*/ static void sha1_transform1 (struct sha1_ctx *sctx, u32 *state, const u32 *in) { int i = 0; @@ -107,7 +107,7 @@ static void sha1_transform1 (struct sha1_ctx *sctx, u32 *state, const u32 *in) SHA_HASH_INIT; /* For context switching purposes, the previous hash output - * is loaded back into the output register + * is loaded back into the output register */ if (sctx->started) { hashs->D1R = *((u32 *) sctx->hash + 0); @@ -125,9 +125,9 @@ static void sha1_transform1 (struct sha1_ctx *sctx, u32 *state, const u32 *in) while (hashs->controlr.BSY) { // this will not take long } - - /* For context switching purposes, the output is saved into a - * context struct which can be used later on + + /* For context switching purposes, the output is saved into a + * context struct which can be used later on */ *((u32 *) sctx->hash + 0) = hashs->D1R; *((u32 *) sctx->hash + 1) = hashs->D2R; @@ -142,13 +142,13 @@ static void sha1_transform1 (struct sha1_ctx *sctx, u32 *state, const u32 *in) /*! \fn static void sha1_init1(struct crypto_tfm *tfm) * \ingroup IFX_SHA1_FUNCTIONS - * \brief initialize sha1 hardware - * \param tfm linux crypto algo transform -*/ + * \brief initialize sha1 hardware + * \param tfm linux crypto algo transform +*/ static int sha1_init1(struct shash_desc *desc) { struct sha1_ctx *sctx = shash_desc_ctx(desc); - + sctx->started = 0; sctx->count = 0; return 0; @@ -156,11 +156,11 @@ static int sha1_init1(struct shash_desc *desc) /*! \fn static void sha1_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len) * \ingroup IFX_SHA1_FUNCTIONS - * \brief on-the-fly sha1 computation - * \param tfm linux crypto algo transform - * \param data input data - * \param len size of input data -*/ + * \brief on-the-fly sha1 computation + * \param tfm linux crypto algo transform + * \param data input data + * \param len size of input data +*/ static int sha1_update(struct shash_desc * desc, const u8 *data, unsigned int len) { @@ -188,10 +188,10 @@ static int sha1_update(struct shash_desc * desc, const u8 *data, /*! \fn static void sha1_final(struct crypto_tfm *tfm, u8 *out) * \ingroup IFX_SHA1_FUNCTIONS - * \brief compute final sha1 value - * \param tfm linux crypto algo transform - * \param out final md5 output value -*/ + * \brief compute final sha1 value + * \param tfm linux crypto algo transform + * \param out final md5 output value +*/ static int sha1_final(struct shash_desc *desc, u8 *out) { struct sha1_ctx *sctx = shash_desc_ctx(desc); @@ -235,7 +235,7 @@ static int sha1_final(struct shash_desc *desc, u8 *out) return 0; } -/* +/* * \brief SHA1 function mappings */ static struct shash_alg ifxdeu_sha1_alg = { @@ -258,8 +258,8 @@ static struct shash_alg ifxdeu_sha1_alg = { /*! \fn int ifxdeu_init_sha1 (void) * \ingroup IFX_SHA1_FUNCTIONS - * \brief initialize sha1 driver -*/ + * \brief initialize sha1 driver +*/ int ifxdeu_init_sha1 (void) { int ret = -ENOSYS; @@ -278,8 +278,8 @@ sha1_err: /*! \fn void ifxdeu_fini_sha1 (void) * \ingroup IFX_SHA1_FUNCTIONS - * \brief unregister sha1 driver -*/ + * \brief unregister sha1 driver +*/ void ifxdeu_fini_sha1 (void) { crypto_unregister_shash(&ifxdeu_sha1_alg); diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c index b58a91a5df7..e18fe2b0e81 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c @@ -32,7 +32,7 @@ \brief SHA1-HMAC deu driver file */ -/*! +/*! \defgroup IFX_SHA1_HMAC_FUNCTIONS IFX_SHA1_HMAC_FUNCTIONS \ingroup IFX_DEU \brief ifx sha1 hmac functions @@ -67,7 +67,7 @@ #define SHA1_BLOCK_WORDS 16 #define SHA1_HASH_WORDS 5 #define SHA1_HMAC_BLOCK_SIZE 64 -#define SHA1_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround +#define SHA1_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround #define HASH_START IFX_HASH_CON #define SHA1_HMAC_MAX_KEYLEN 64 @@ -99,10 +99,10 @@ static int sha1_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_fina /*! \fn static void sha1_hmac_transform(struct crypto_tfm *tfm, u32 const *in) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief save input block to context - * \param tfm linux crypto algo transform - * \param in 64-byte block of input -*/ + * \brief save input block to context + * \param tfm linux crypto algo transform + * \param in 64-byte block of input +*/ static int sha1_hmac_transform(struct shash_desc *desc, u32 const *in) { struct sha1_hmac_ctx *sctx = crypto_shash_ctx(desc->tfm); @@ -121,11 +121,11 @@ static int sha1_hmac_transform(struct shash_desc *desc, u32 const *in) /*! \fn int sha1_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief sets sha1 hmac key - * \param tfm linux crypto algo transform - * \param key input key - * \param keylen key length greater than 64 bytes IS NOT SUPPORTED -*/ + * \brief sets sha1 hmac key + * \param tfm linux crypto algo transform + * \param key input key + * \param keylen key length greater than 64 bytes IS NOT SUPPORTED +*/ static int sha1_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen) { struct sha1_hmac_ctx *sctx = crypto_shash_ctx(tfm); @@ -157,16 +157,16 @@ static int sha1_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned in /*! \fn int sha1_hmac_setkey_hw(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief sets sha1 hmac key into hw registers - * \param tfm linux crypto algo transform - * \param key input key - * \param keylen key length greater than 64 bytes IS NOT SUPPORTED -*/ + * \brief sets sha1 hmac key into hw registers + * \param tfm linux crypto algo transform + * \param key input key + * \param keylen key length greater than 64 bytes IS NOT SUPPORTED +*/ static int sha1_hmac_setkey_hw(const u8 *key, unsigned int keylen) { volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; int i, j; - u32 *in_key = (u32 *)key; + u32 *in_key = (u32 *)key; j = 0; @@ -175,7 +175,7 @@ static int sha1_hmac_setkey_hw(const u8 *key, unsigned int keylen) { hash->KIDX = j; asm("sync"); - hash->KEY = *((u32 *) in_key + j); + hash->KEY = *((u32 *) in_key + j); j++; } @@ -184,9 +184,9 @@ static int sha1_hmac_setkey_hw(const u8 *key, unsigned int keylen) /*! \fn void sha1_hmac_init(struct crypto_tfm *tfm) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief initialize sha1 hmac context - * \param tfm linux crypto algo transform -*/ + * \brief initialize sha1 hmac context + * \param tfm linux crypto algo transform +*/ static int sha1_hmac_init(struct shash_desc *desc) { struct sha1_hmac_ctx *sctx = crypto_shash_ctx(desc->tfm); @@ -201,11 +201,11 @@ static int sha1_hmac_init(struct shash_desc *desc) /*! \fn static void sha1_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief on-the-fly sha1 hmac computation - * \param tfm linux crypto algo transform - * \param data input data - * \param len size of input data -*/ + * \brief on-the-fly sha1 hmac computation + * \param tfm linux crypto algo transform + * \param data input data + * \param len size of input data +*/ static int sha1_hmac_update(struct shash_desc *desc, const u8 *data, unsigned int len) { @@ -234,10 +234,10 @@ static int sha1_hmac_update(struct shash_desc *desc, const u8 *data, /*! \fn static int sha1_hmac_final(struct crypto_tfm *tfm, u8 *out) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief call sha1_hmac_final_impl with hash_final true - * \param tfm linux crypto algo transform - * \param out final sha1 hmac output value -*/ + * \brief call sha1_hmac_final_impl with hash_final true + * \param tfm linux crypto algo transform + * \param out final sha1 hmac output value +*/ static int sha1_hmac_final(struct shash_desc *desc, u8 *out) { return sha1_hmac_final_impl(desc, out, true); @@ -245,11 +245,11 @@ static int sha1_hmac_final(struct shash_desc *desc, u8 *out) /*! \fn static int sha1_hmac_final_impl(struct crypto_tfm *tfm, u8 *out, bool hash_final) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief ompute final or intermediate sha1 hmac value - * \param tfm linux crypto algo transform - * \param out final sha1 hmac output value - * \param in finalize or intermediate processing -*/ + * \brief ompute final or intermediate sha1 hmac value + * \param tfm linux crypto algo transform + * \param out final sha1 hmac output value + * \param in finalize or intermediate processing +*/ static int sha1_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final) { struct sha1_hmac_ctx *sctx = crypto_shash_ctx(desc->tfm); @@ -304,7 +304,7 @@ static int sha1_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_fina asm("sync"); //for vr9 change, ENDI = 1 - *IFX_HASH_CON = HASH_CON_VALUE; + *IFX_HASH_CON = HASH_CON_VALUE; //wait for processing while (hashs->controlr.BSY) { @@ -334,7 +334,7 @@ static int sha1_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_fina while (hashs->controlr.BSY) { // this will not take long } - + in += 16; } @@ -395,7 +395,7 @@ static void sha1_hmac_exit_tfm(struct crypto_tfm *tfm) kfree(sctx->desc); } -/* +/* * \brief SHA1_HMAC function mappings */ @@ -421,8 +421,8 @@ static struct shash_alg ifxdeu_sha1_hmac_alg = { /*! \fn int ifxdeu_init_sha1_hmac (void) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief initialize sha1 hmac driver -*/ + * \brief initialize sha1 hmac driver +*/ int ifxdeu_init_sha1_hmac (void) { int ret = -ENOSYS; @@ -442,8 +442,8 @@ sha1_err: /*! \fn void ifxdeu_fini_sha1_hmac (void) * \ingroup IFX_SHA1_HMAC_FUNCTIONS - * \brief unregister sha1 hmac driver -*/ + * \brief unregister sha1 hmac driver +*/ void ifxdeu_fini_sha1_hmac (void) { diff --git a/package/kernel/lantiq/ltq-deu/src/internal.h b/package/kernel/lantiq/ltq-deu/src/internal.h index 2d226362e59..d4384b08ab2 100644 --- a/package/kernel/lantiq/ltq-deu/src/internal.h +++ b/package/kernel/lantiq/ltq-deu/src/internal.h @@ -6,7 +6,7 @@ * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) + * Software Foundation; either version 2 of the License, or (at your option) * any later version. * */ diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c index b3d14122d62..65c9833a0a5 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c @@ -172,7 +172,7 @@ static void ptm_setup(struct net_device *dev, int ndev) static struct net_device_stats *ptm_get_stats(struct net_device *dev) { struct net_device_stats *s; - + if ( dev != g_net_dev[0] ) return NULL; s = &g_ptm_priv_data.itf[0].stats; diff --git a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.c b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.c index cb8345377ea..3470e55d6ec 100644 --- a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.c +++ b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -46,7 +46,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #endif #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -57,9 +57,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -82,7 +82,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -168,7 +168,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int lc = vs->Properties.lc; #ifdef _LZMA_OUT_READ - + UInt32 Range = vs->Range; UInt32 Code = vs->Code; #ifdef _LZMA_IN_CB @@ -210,7 +210,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); UInt32 i; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; + p[i] = kBitModelTotal >> 1; rep0 = rep1 = rep2 = rep3 = 1; state = 0; globalPos = 0; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + #ifdef _LZMA_IN_CB RC_INIT; #else @@ -275,7 +275,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -287,9 +287,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -338,7 +338,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -365,14 +365,14 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 pos; #endif UpdateBit0(prob); - + #ifdef _LZMA_OUT_READ if (distanceLimit == 0) #else if (nowPos == 0) #endif return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; #ifdef _LZMA_OUT_READ pos = dictionaryPos - rep0; @@ -408,7 +408,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -469,7 +469,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) @@ -524,7 +524,7 @@ int LzmaDecode(CLzmaDecoderState *vs, len += kMatchMinLen; #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) + if (rep0 > distanceLimit) #else if (rep0 > nowPos) #endif diff --git a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.h b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.h index 2870eeb9c9c..bd75525aedb 100644 --- a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.h +++ b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -31,7 +31,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ diff --git a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaTypes.h b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaTypes.h index 9c27290757c..83f96f46437 100644 --- a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaTypes.h +++ b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaTypes.h @@ -1,5 +1,5 @@ -/* -LzmaTypes.h +/* +LzmaTypes.h Types for LZMA Decoder @@ -13,12 +13,12 @@ This file is part of LZMA SDK 4.40 (2006-05-01) #ifndef _7ZIP_BYTE_DEFINED #define _7ZIP_BYTE_DEFINED typedef unsigned char Byte; -#endif +#endif #ifndef _7ZIP_UINT16_DEFINED #define _7ZIP_UINT16_DEFINED typedef unsigned short UInt16; -#endif +#endif #ifndef _7ZIP_UINT32_DEFINED #define _7ZIP_UINT32_DEFINED @@ -27,7 +27,7 @@ typedef unsigned long UInt32; #else typedef unsigned int UInt32; #endif -#endif +#endif /* #define _LZMA_NO_SYSTEM_SIZE_T */ /* You can use it, if you don't want */ diff --git a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaWrapper.c b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaWrapper.c index 89662b9a5f4..c32bd7ce6fe 100644 --- a/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaWrapper.c +++ b/package/kernel/lantiq/ltq-vdsl-fw/src/LzmaWrapper.c @@ -54,9 +54,9 @@ int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_l UInt32 outSizeHigh = 0; SizeT outSizeFull; unsigned char *outStream; - - int waitEOS = 1; - /* waitEOS = 1, if there is no uncompressed size in headers, + + int waitEOS = 1; + /* waitEOS = 1, if there is no uncompressed size in headers, so decoder will wait EOS (End of Stream Marker) in compressed stream */ SizeT compressedSize; @@ -119,7 +119,7 @@ int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_l else outSizeHigh += (UInt32)(b) << ((i - 4) * 8); } - + if (waitEOS) { #if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) @@ -169,7 +169,7 @@ int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_l inStream = source + rpos; } - if (state.Probs == 0 + if (state.Probs == 0 || (outStream == 0 && outSizeFull != 0) || (inStream == 0 && compressedSize != 0) ) diff --git a/package/network/services/ead/src/tinysrp/bn_prime.h b/package/network/services/ead/src/tinysrp/bn_prime.h index b7cf9a9bfe1..51c50791dc5 100644 --- a/package/network/services/ead/src/tinysrp/bn_prime.h +++ b/package/network/services/ead/src/tinysrp/bn_prime.h @@ -5,21 +5,21 @@ * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,10 +34,10 @@ * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -49,7 +49,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/package/network/services/ead/src/tinysrp/t_conv.c b/package/network/services/ead/src/tinysrp/t_conv.c index 3be6d85b541..b7b8b50801d 100644 --- a/package/network/services/ead/src/tinysrp/t_conv.c +++ b/package/network/services/ead/src/tinysrp/t_conv.c @@ -13,9 +13,9 @@ * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, - * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY - * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. + * THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, + * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY + * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. * * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL, * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER diff --git a/package/network/services/ead/src/tinysrp/t_read.c b/package/network/services/ead/src/tinysrp/t_read.c index 087b7d55b85..b83b3e18e08 100644 --- a/package/network/services/ead/src/tinysrp/t_read.c +++ b/package/network/services/ead/src/tinysrp/t_read.c @@ -13,9 +13,9 @@ * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, - * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY - * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. + * THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, + * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY + * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. * * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL, * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER diff --git a/package/network/services/ead/src/tinysrp/t_read.h b/package/network/services/ead/src/tinysrp/t_read.h index e621f793ad6..88fdf82f296 100644 --- a/package/network/services/ead/src/tinysrp/t_read.h +++ b/package/network/services/ead/src/tinysrp/t_read.h @@ -13,9 +13,9 @@ * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, - * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY - * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. + * THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, + * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY + * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. * * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL, * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER diff --git a/package/network/services/hostapd/src/src/ap/ubus.c b/package/network/services/hostapd/src/src/ap/ubus.c index 395e2c2dbce..fab5f31282a 100644 --- a/package/network/services/hostapd/src/src/ap/ubus.c +++ b/package/network/services/hostapd/src/src/ap/ubus.c @@ -362,7 +362,7 @@ hostapd_bss_get_status(struct ubus_context *ctx, struct ubus_object *obj, if (hapd->conf->ssid.ssid_len < SSID_MAX_LEN) ssid_len = hapd->conf->ssid.ssid_len; - + ieee80211_freq_to_channel_ext(hapd->iface->freq, hapd->iconf->secondary_channel, hostapd_get_oper_chwidth(hapd->iconf), @@ -2060,7 +2060,7 @@ void hostapd_ubus_notify_bss_transition_response( blobmsg_add_u8(&b, "bss-termination-delay", bss_termination_delay); if (target_bssid) blobmsg_add_macaddr(&b, "target-bssid", target_bssid); - + hostapd_ubus_notify_bss_transition_add_candidate_list(candidate_list, candidate_list_len); ubus_notify(ctx, &hapd->ubus.obj, "bss-transition-response", b.head, -1); diff --git a/package/network/services/ppp/utils/pfc.c b/package/network/services/ppp/utils/pfc.c index 5476be170ab..6bb5368a3f6 100644 --- a/package/network/services/ppp/utils/pfc.c +++ b/package/network/services/ppp/utils/pfc.c @@ -1,4 +1,4 @@ -/* +/* * Taken from fli4l 3.0 * Make sure you compile it against the same libpcap version used in OpenWrt */ diff --git a/package/network/utils/rssileds/src/rssileds.c b/package/network/utils/rssileds/src/rssileds.c index 60d30f13b7d..93c12b46d8d 100644 --- a/package/network/utils/rssileds/src/rssileds.c +++ b/package/network/utils/rssileds/src/rssileds.c @@ -249,16 +249,16 @@ int main(int argc, char **argv) if ( init_led(&(currentrule->led), argv[i]) ) return 1; - + if ( sscanf(argv[i+1], "%d", &(currentrule->minq)) != 1 ) return 1; if ( sscanf(argv[i+2], "%d", &(currentrule->maxq)) != 1 ) return 1; - + if ( sscanf(argv[i+3], "%d", &(currentrule->boffset)) != 1 ) return 1; - + if ( sscanf(argv[i+4], "%d", &(currentrule->bfactor)) != 1 ) return 1; } diff --git a/package/system/mtd/src/imagetag.c b/package/system/mtd/src/imagetag.c index 673dd44de56..47642478f57 100644 --- a/package/system/mtd/src/imagetag.c +++ b/package/system/mtd/src/imagetag.c @@ -139,7 +139,7 @@ static uint32_t strntoul(char *str, char **endptr, int base, size_t len) { newstr = calloc(len + 1, sizeof(char)); if (newstr) { - strncpy(newstr, str, len); + strncpy(newstr, str, len); res = strtoul(newstr, endptr, base); free(newstr); } @@ -258,7 +258,7 @@ trx_check(int imagefd, const char *mtd, char *buf, int *len) } headerCRC = crc32buf(buf, offsetof(struct bcm_tag, header_crc)); if (*(uint32_t *)(&tag->header_crc) != headerCRC) { - + if (quiet < 2) { fprintf(stderr, "Bad header CRC got %08x, calculated %08x\n", *(uint32_t *)(&tag->header_crc), headerCRC); @@ -276,7 +276,7 @@ trx_check(int imagefd, const char *mtd, char *buf, int *len) } imageLen = strntoul(&tag->total_length[0], NULL, 10, IMAGE_LEN); - + if(mtdsize < imageLen) { fprintf(stderr, "Image too big for partition: %s\n", mtd); close(fd); @@ -355,7 +355,7 @@ mtd_fixtrx(const char *mtd, size_t offset, size_t data_size) rootfslen = strntoul(&tag->root_length[0], NULL, 10, IMAGE_LEN); if (rootfslen == 0) { - if (quiet < 2) + if (quiet < 2) fprintf(stderr, "Header already fixed, exiting\n"); close(fd); return 0; @@ -390,9 +390,9 @@ mtd_fixtrx(const char *mtd, size_t offset, size_t data_size) } if (quiet < 2) { - fprintf(stderr, "New image crc32: 0x%x, rewriting block\n", + fprintf(stderr, "New image crc32: 0x%x, rewriting block\n", *(uint32_t *)(&tag->image_crc)); - fprintf(stderr, "New header crc32: 0x%x, rewriting block\n", headercrc); + fprintf(stderr, "New header crc32: 0x%x, rewriting block\n", headercrc); } if (pwrite(fd, buf, erasesize, block_offset) != erasesize) { diff --git a/package/system/mtd/src/jffs2.c b/package/system/mtd/src/jffs2.c index b432f64ac05..2cfc878b10c 100644 --- a/package/system/mtd/src/jffs2.c +++ b/package/system/mtd/src/jffs2.c @@ -293,7 +293,7 @@ int mtd_write_jffs2(const char *mtd, const char *filename, const char *dir) if (quiet < 2) fprintf(stderr, "Appending %s to jffs2 partition %s\n", filename, mtd); - + buf = malloc(erasesize); if (!buf) { fprintf(stderr, "Out of memory!\n"); diff --git a/package/system/mtd/src/jffs2.h b/package/system/mtd/src/jffs2.h index 858e77a0173..89ac3b76d15 100644 --- a/package/system/mtd/src/jffs2.h +++ b/package/system/mtd/src/jffs2.h @@ -16,7 +16,7 @@ #define JFFS2_SUPER_MAGIC 0x72b6 -/* You must include something which defines the C99 uintXX_t types. +/* You must include something which defines the C99 uintXX_t types. We don't do it from here because this file is used in too many different environments. */ diff --git a/package/utils/fbtest/src/fbtest.c b/package/utils/fbtest/src/fbtest.c index 021b80303ce..9a9bc6494c0 100644 --- a/package/utils/fbtest/src/fbtest.c +++ b/package/utils/fbtest/src/fbtest.c @@ -2,7 +2,7 @@ * fbtest - fbtest.c * test program for the tuxbox-framebuffer device * tests all GTX/eNX supported modes - * + * * (c) 2003 Carsten Juttner (carjay@gmx.net) * * This program is free software; you can redistribute it and/or modify @@ -18,7 +18,7 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * + * ****************************************************************************** * $Id: fbtest.c,v 1.5 2005/01/14 23:14:41 carjay Exp $ ******************************************************************************/ @@ -187,12 +187,12 @@ int setmode(int fbd, const struct pixelformat *pixf,const struct vidsize *vids){ int stat; stat = ioctl (fbd, FBIOGET_VSCREENINFO,&var); if (stat<0) return -2; - + var.xres= vids->width; var.xres_virtual = vids->width; var.yres= vids->height; var.yres_virtual = vids->height; - + var.bits_per_pixel = pixf->bpp; var.red = pixf->red; var.green = pixf->green; @@ -254,7 +254,7 @@ void drawrect(void *videoram, struct rect *r, const struct pixelformat *pixf, co pmem +=((vids->width*bpp)>>3); // skip one whole line, actually should be taken from "fix-info" } } - + // create quick little test image, 4 colours from table void draw4field(void *videoram, const struct pixelformat *pixf, const struct vidsize *vids){ struct rect r; @@ -314,7 +314,7 @@ int main (int argc,char **argv){ int optchar,fmode=-1,smode=-1,clear=1; int i_cmap,i_size,i_pix; extern char *optarg; - + if (argc!=0&&argc>4) usage(argv[0]); while ( (optchar = getopt (argc,argv,"f:s:n"))!= -1){ int i,height,width; @@ -359,7 +359,7 @@ int main (int argc,char **argv){ usage (argv[0]); } } - + fbd = open (FBDEV, O_RDWR); if (fbd<0){ perror ("Error opening framebuffer device"); @@ -396,7 +396,7 @@ int main (int argc,char **argv){ printf ("%dx%d ",vidsizetable[i_size].width,vidsizetable[i_size].height); fflush(stdout); if ((i_size%4)==3) printf ("\n"); - + // try to set mode stat = setmode(fbd,&pixelformattable[i_pix],&vidsizetable[i_size]); if (stat==-2) perror ("fbtest: could not get fb_var-screeninfo from fb-device"); diff --git a/package/utils/fritz-tools/src/fritz_cal_extract.c b/package/utils/fritz-tools/src/fritz_cal_extract.c index c4547bc7e05..7e5f4118f5d 100644 --- a/package/utils/fritz-tools/src/fritz_cal_extract.c +++ b/package/utils/fritz-tools/src/fritz_cal_extract.c @@ -68,10 +68,10 @@ static void buffer_reverse(unsigned char *data, unsigned int top) * or Z_OK if data was retrieved up to limit (*limit == original value). * * Return values (failure): - * Z_MEM_ERROR if memory could not be allocated for processing, - * Z_DATA_ERROR if the deflate data is invalid or incomplete, - * Z_VERSION_ERROR if the version of zlib.h and the version of the - * library linked do not match, or + * Z_MEM_ERROR if memory could not be allocated for processing, + * Z_DATA_ERROR if the deflate data is invalid or incomplete, + * Z_VERSION_ERROR if the version of zlib.h and the version of the + * library linked do not match, or * Z_ERRNO if there is an error reading or writing the files. */ static int inflate_to_buffer(FILE *source, unsigned char *buf, size_t *limit) @@ -305,7 +305,7 @@ int main(int argc, char **argv) buffer_reverse(buf, datasize - 1); if (datasize <= skip) { - fprintf(stderr, "Failed to skip %u bytes, total data size is %u!\n", + fprintf(stderr, "Failed to skip %u bytes, total data size is %u!\n", (unsigned int)skip, (unsigned int)datasize); goto out_bad; } diff --git a/package/utils/px5g-mbedtls/px5g-mbedtls.c b/package/utils/px5g-mbedtls/px5g-mbedtls.c index 63f54bd9aab..b1c809f8346 100644 --- a/package/utils/px5g-mbedtls/px5g-mbedtls.c +++ b/package/utils/px5g-mbedtls/px5g-mbedtls.c @@ -76,7 +76,7 @@ static void write_file(const char *path, size_t len, bool pem, bool cert) fprintf(stderr, "No data to write\n"); exit(1); } - + if (cert) mode |= S_IRGRP | S_IROTH; diff --git a/package/utils/ucode-mod-uline/src/utf8.c b/package/utils/ucode-mod-uline/src/utf8.c index 3f7c75e68eb..c2e696820b1 100644 --- a/package/utils/ucode-mod-uline/src/utf8.c +++ b/package/utils/ucode-mod-uline/src/utf8.c @@ -18,7 +18,7 @@ * adapted from musl code: * * Copyright © 2005-2020 Rich Felker, et al. - * + * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -26,10 +26,10 @@ * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. diff --git a/scripts/config/lexer.lex.c b/scripts/config/lexer.lex.c index c57119fa235..4b197ce50ca 100644 --- a/scripts/config/lexer.lex.c +++ b/scripts/config/lexer.lex.c @@ -49,7 +49,7 @@ typedef uint32_t flex_uint32_t; typedef signed char flex_int8_t; typedef short int flex_int16_t; typedef int flex_int32_t; -typedef unsigned char flex_uint8_t; +typedef unsigned char flex_uint8_t; typedef unsigned short int flex_uint16_t; typedef unsigned int flex_uint32_t; @@ -160,7 +160,7 @@ extern FILE *yyin, *yyout; #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 - + /* Note: We specifically omit the test for yy_rule_can_match_eol because it requires * access to the local variable yy_act. Since yyless() is a macro, it would break * existing scanners that call yyless() from OUTSIDE yylex. @@ -182,7 +182,7 @@ extern FILE *yyin, *yyout; if ( *p == '\n' )\ --yylineno;\ }while(0) - + /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ @@ -2240,9 +2240,9 @@ static const YY_CHAR yy_ec[256] = /* Table of booleans, true if rule could match eol. */ static const flex_int32_t yy_rule_can_match_eol[65] = { 0, -0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, +0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, }; extern int yy_flex_debug; @@ -2397,9 +2397,9 @@ extern int yywrap ( void ); #endif #ifndef YY_NO_UNPUT - + static void yyunput ( int c, char *buf_ptr ); - + #endif #ifndef yytext_ptr @@ -2510,7 +2510,7 @@ YY_DECL yy_state_type yy_current_state; char *yy_cp, *yy_bp; int yy_act; - + if ( !(yy_init) ) { (yy_init) = 1; @@ -2570,7 +2570,7 @@ yy_find_action: int yyl; for ( yyl = 0; yyl < yyleng; ++yyl ) if ( yytext[yyl] == '\n' ) - + yylineno++; ; } @@ -3233,7 +3233,7 @@ static int yy_get_next_buffer (void) { yy_state_type yy_current_state; char *yy_cp; - + yy_current_state = (yy_start); for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) @@ -3252,7 +3252,7 @@ static int yy_get_next_buffer (void) static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) { int yy_is_jam; - + yy_current_state = yy_nxt[yy_current_state][1]; yy_is_jam = (yy_current_state <= 0); @@ -3264,7 +3264,7 @@ static int yy_get_next_buffer (void) static void yyunput (int c, char * yy_bp ) { char *yy_cp; - + yy_cp = (yy_c_buf_p); /* undo effects of setting up yytext */ @@ -3313,7 +3313,7 @@ static int yy_get_next_buffer (void) { int c; - + *(yy_c_buf_p) = (yy_hold_char); if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) @@ -3375,7 +3375,7 @@ static int yy_get_next_buffer (void) (yy_hold_char) = *++(yy_c_buf_p); if ( c == '\n' ) - + yylineno++; ; @@ -3385,12 +3385,12 @@ static int yy_get_next_buffer (void) /** Immediately switch to a different input stream. * @param input_file A readable stream. - * + * * @note This function does not reset the start condition to @c INITIAL . */ void yyrestart (FILE * input_file ) { - + if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = @@ -3403,11 +3403,11 @@ static int yy_get_next_buffer (void) /** Switch to a different input buffer. * @param new_buffer The new input buffer. - * + * */ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ) { - + /* TODO. We should be able to replace this entire function body * with * yypop_buffer_state(); @@ -3447,13 +3447,13 @@ static void yy_load_buffer_state (void) /** Allocate and initialize an input buffer state. * @param file A readable stream. * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. - * + * * @return the allocated buffer state. */ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size ) { YY_BUFFER_STATE b; - + b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); @@ -3476,11 +3476,11 @@ static void yy_load_buffer_state (void) /** Destroy the buffer. * @param b a buffer created with yy_create_buffer() - * + * */ void yy_delete_buffer (YY_BUFFER_STATE b ) { - + if ( ! b ) return; @@ -3501,7 +3501,7 @@ static void yy_load_buffer_state (void) { int oerrno = errno; - + yy_flush_buffer( b ); b->yy_input_file = file; @@ -3517,13 +3517,13 @@ static void yy_load_buffer_state (void) } b->yy_is_interactive = 0; - + errno = oerrno; } /** Discard all buffered characters. On the next scan, YY_INPUT will be called. * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. - * + * */ void yy_flush_buffer (YY_BUFFER_STATE b ) { @@ -3552,7 +3552,7 @@ static void yy_load_buffer_state (void) * the current state. This function will allocate the stack * if necessary. * @param new_buffer The new state. - * + * */ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) { @@ -3582,7 +3582,7 @@ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) /** Removes and deletes the top of the stack, if present. * The next element becomes the new top. - * + * */ void yypop_buffer_state (void) { @@ -3606,7 +3606,7 @@ void yypop_buffer_state (void) static void yyensure_buffer_stack (void) { yy_size_t num_to_alloc; - + if (!(yy_buffer_stack)) { /* First allocation is just for 2 elements, since we don't know if this @@ -3649,13 +3649,13 @@ static void yyensure_buffer_stack (void) /** Setup the input buffer state to scan directly from a user-specified character buffer. * @param base the character buffer * @param size the size in bytes of the character buffer - * + * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) { YY_BUFFER_STATE b; - + if ( size < 2 || base[size-2] != YY_END_OF_BUFFER_CHAR || base[size-1] != YY_END_OF_BUFFER_CHAR ) @@ -3684,14 +3684,14 @@ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) /** Setup the input buffer state to scan a string. The next call to yylex() will * scan from a @e copy of @a str. * @param yystr a NUL-terminated string to scan - * + * * @return the newly allocated buffer state object. * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ YY_BUFFER_STATE yy_scan_string (const char * yystr ) { - + return yy_scan_bytes( yystr, (int) strlen(yystr) ); } @@ -3699,7 +3699,7 @@ YY_BUFFER_STATE yy_scan_string (const char * yystr ) * scan from a @e copy of @a bytes. * @param yybytes the byte buffer to scan * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes. - * + * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) @@ -3708,7 +3708,7 @@ YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) char *buf; yy_size_t n; int i; - + /* Get memory for full buffer, including space for trailing EOB's. */ n = (yy_size_t) (_yybytes_len + 2); buf = (char *) yyalloc( n ); @@ -3762,16 +3762,16 @@ static void yynoreturn yy_fatal_error (const char* msg ) /* Accessor methods (get/set functions) to struct members. */ /** Get the current line number. - * + * */ int yyget_lineno (void) { - + return yylineno; } /** Get the input stream. - * + * */ FILE *yyget_in (void) { @@ -3779,7 +3779,7 @@ FILE *yyget_in (void) } /** Get the output stream. - * + * */ FILE *yyget_out (void) { @@ -3787,7 +3787,7 @@ FILE *yyget_out (void) } /** Get the length of the current token. - * + * */ int yyget_leng (void) { @@ -3795,7 +3795,7 @@ int yyget_leng (void) } /** Get the current token. - * + * */ char *yyget_text (void) @@ -3805,18 +3805,18 @@ char *yyget_text (void) /** Set the current line number. * @param _line_number line number - * + * */ void yyset_lineno (int _line_number ) { - + yylineno = _line_number; } /** Set the input stream. This does not discard the current * input buffer. * @param _in_str A readable stream. - * + * * @see yy_switch_to_buffer */ void yyset_in (FILE * _in_str ) @@ -3847,7 +3847,7 @@ static int yy_init_globals (void) /* We do not touch yylineno unless the option is enabled. */ yylineno = 1; - + (yy_buffer_stack) = NULL; (yy_buffer_stack_top) = 0; (yy_buffer_stack_max) = 0; @@ -3873,7 +3873,7 @@ static int yy_init_globals (void) /* yylex_destroy is for both reentrant and non-reentrant scanners. */ int yylex_destroy (void) { - + /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ yy_delete_buffer( YY_CURRENT_BUFFER ); @@ -3899,7 +3899,7 @@ int yylex_destroy (void) #ifndef yytext_ptr static void yy_flex_strncpy (char* s1, const char * s2, int n ) { - + int i; for ( i = 0; i < n; ++i ) s1[i] = s2[i]; @@ -3924,7 +3924,7 @@ void *yyalloc (yy_size_t size ) void *yyrealloc (void * ptr, yy_size_t size ) { - + /* The cast to (char *) in the following accommodates both * implementations that use char* generic pointers, and those * that use void* generic pointers. It works with the latter diff --git a/target/linux/at91/image/dfboot/src/at45.c b/target/linux/at91/image/dfboot/src/at45.c index 8830d7e9b87..09ee4b69483 100644 --- a/target/linux/at91/image/dfboot/src/at45.c +++ b/target/linux/at91/image/dfboot/src/at45.c @@ -8,7 +8,7 @@ * intellectual property rights of others. *---------------------------------------------------------------------------- * File Name : at45c.h - * Object : + * Object : * * 1.0 10/12/03 HIi : Creation. * 1.01 03/05/04 HIi : Bug Fix in AT91F_DataFlashWaitReady() Function. @@ -28,7 +28,7 @@ /*----------------------------------------------------------------------------*/ void AT91F_SpiInit(void) { /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; @@ -88,7 +88,7 @@ static void AT91F_SpiEnable(int cs) { static unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) { unsigned int timeout; - + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; /* Initialize the Transmit and Receive Pointer */ @@ -138,7 +138,7 @@ static AT91S_DataFlashStatus AT91F_DataFlashSendCommand( unsigned int adr; /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); @@ -152,7 +152,7 @@ static AT91S_DataFlashStatus AT91F_DataFlashSendCommand( pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); } else - { + { pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; @@ -168,7 +168,7 @@ static AT91S_DataFlashStatus AT91F_DataFlashSendCommand( pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); } @@ -245,7 +245,7 @@ static AT91S_DataFlashStatus AT91F_DataFlashContinuousRead( pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - + status = AT91F_DataFlashSendCommand(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); /* Send the command to the dataflash */ return(status); @@ -325,7 +325,7 @@ static AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( pDataFlash->pDataFlashDesc->command[4] = 0; cmdsize = 4; } - + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; @@ -341,7 +341,7 @@ static AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( /*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ +/* Function Name : AT91F_PageErase */ /* Object : Read a page in the SRAM Buffer 1 or 2 */ /* Input Parameters : DataFlash Service */ /* : Page concerned */ @@ -353,10 +353,10 @@ static AT91S_DataFlashStatus AT91F_PageErase( unsigned int page) { int cmdsize; - /* Test if the buffer command is legal */ + /* Test if the buffer command is legal */ /* no data to transmit or receive */ pDataFlash->pDataFlashDesc->tx_data_size = 0; - + cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; @@ -419,11 +419,11 @@ static AT91S_DataFlashStatus AT91F_PartialPageWrite ( /* Read the contents of the page in the Sram Buffer */ AT91F_MainMemoryToBufferTransfer(pDataFlash, DB_PAGE_2_BUF1_TRF, page); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - + /*Update the SRAM buffer */ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - + /* Erase page if a 128 Mbits device */ if (pDataFlash->pDevice->pages_number >= 16384) { @@ -477,26 +477,26 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( src += length; } - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ + /* program dataflash page */ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - + status = AT91F_PageErase(pDataFlash, page); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); if (!status) return AT91C_DATAFLASH_ERROR; - + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); if(!status) return AT91C_DATAFLASH_ERROR; AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); - + /* Update size, source and destination pointers */ size -= pDataFlash->pDevice->pages_size ; dest += pDataFlash->pDevice->pages_size ; @@ -578,7 +578,7 @@ AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash) unsigned int status; AT91F_SpiEnable(pDataFlash->pDevice->cs); - + for(page=0; page < pDataFlash->pDevice->pages_number; page++) { /* Erase dataflash page */ diff --git a/target/linux/at91/image/dfboot/src/com.c b/target/linux/at91/image/dfboot/src/com.c index aacfb555584..081d86fb652 100644 --- a/target/linux/at91/image/dfboot/src/com.c +++ b/target/linux/at91/image/dfboot/src/com.c @@ -8,7 +8,7 @@ * intellectual property rights of others. *---------------------------------------------------------------------------- * File Name : com.c - * Object : + * Object : * Creation : HIi 03/27/2003 * *---------------------------------------------------------------------------- @@ -98,9 +98,9 @@ int at91_serial_getc() /*----------------------------------------------------------------------------- * Function Name : AT91F_ReadLine() - * Object : - * Input Parameters : - * Return value : + * Object : + * Input Parameters : + * Return value : *----------------------------------------------------------------------------- */ int AT91F_ReadLine (const char *const prompt, char *console_buffer) @@ -144,14 +144,14 @@ int AT91F_ReadLine (const char *const prompt, char *console_buffer) /* * Must be a normal character then */ - if (n < (AT91C_CB_SIZE -2)) + if (n < (AT91C_CB_SIZE -2)) { ++col; /* echo input */ putc(c); *p++ = c; ++n; - } - else + } + else { /* Buffer full */ putc('\a'); } @@ -162,9 +162,9 @@ int AT91F_ReadLine (const char *const prompt, char *console_buffer) /*----------------------------------------------------------------------------- * Function Name : AT91F_WaitKeyPressed() - * Object : - * Input Parameters : - * Return value : + * Object : + * Input Parameters : + * Return value : *----------------------------------------------------------------------------- */ void AT91F_WaitKeyPressed(void) @@ -244,7 +244,7 @@ static int number(int num, int base, int size, num = -num; size--; } - + i = 0; if(num == 0) tmp[i++] = digits[0]; @@ -254,11 +254,11 @@ static int number(int num, int base, int size, if(i > precision) precision = i; size -= precision; - + if(!(type&(ZEROPAD+LEFT))) while(size-->0) putc(' '); - + if(sign) putc(sign); @@ -268,7 +268,7 @@ static int number(int num, int base, int size, while (i < precision--) putc('0'); - + while (i-- > 0) putc(tmp[i]); @@ -332,18 +332,18 @@ int hvfprintf(const char *fmt, va_list va) case '%' : putc(*fmt); done = true; - default: + default: putc('%'); putc(*fmt); done = true; break; - } + } } while(!done); } else if(*fmt == '\\') { fmt++; if(*fmt == 'r') { putc('\r'); - } else if(*fmt == 'n') { + } else if(*fmt == 'n') { putc('\n'); } } else { @@ -351,7 +351,7 @@ int hvfprintf(const char *fmt, va_list va) } fmt++; } while(*fmt != 0); - + return 0; } diff --git a/target/linux/at91/image/dfboot/src/com.h b/target/linux/at91/image/dfboot/src/com.h index 7af09e4d6df..fc3d1e2156e 100644 --- a/target/linux/at91/image/dfboot/src/com.h +++ b/target/linux/at91/image/dfboot/src/com.h @@ -8,7 +8,7 @@ * intellectual property rights of others. *---------------------------------------------------------------------------- * File Name : com.h - * Object : + * Object : * * 1.0 27/03/03 HIi : Creation *---------------------------------------------------------------------------- diff --git a/target/linux/at91/image/dfboot/src/dataflash.c b/target/linux/at91/image/dfboot/src/dataflash.c index 5e54460b721..62644485a85 100644 --- a/target/linux/at91/image/dfboot/src/dataflash.c +++ b/target/linux/at91/image/dfboot/src/dataflash.c @@ -30,7 +30,7 @@ int AT91F_DataflashInit(void) int i; int dfcode; int Nb_device = 0; - + AT91F_SpiInit(); for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { @@ -88,7 +88,7 @@ int AT91F_DataflashInit(void) default: break; } - } + } return (Nb_device); } @@ -111,7 +111,7 @@ void AT91F_DataflashPrintInfo(void) case AT45DB642: printf ("642"); break; - case AT45DB128: + case AT45DB128: printf ("128"); break; } diff --git a/target/linux/at91/image/dfboot/src/dataflash.h b/target/linux/at91/image/dfboot/src/dataflash.h index 8fab63fa9e8..cfd5e7e054e 100644 --- a/target/linux/at91/image/dfboot/src/dataflash.h +++ b/target/linux/at91/image/dfboot/src/dataflash.h @@ -22,7 +22,7 @@ #ifdef SPI_LOW_SPEED #define AT91C_SPI_CLK 14976000/4 #else -#define AT91C_SPI_CLK 14976000 +#define AT91C_SPI_CLK 14976000 #endif /* AC characteristics */ diff --git a/target/linux/at91/image/dfboot/src/embedded_services.h b/target/linux/at91/image/dfboot/src/embedded_services.h index 956b9edf069..9c66b09b63e 100644 --- a/target/linux/at91/image/dfboot/src/embedded_services.h +++ b/target/linux/at91/image/dfboot/src/embedded_services.h @@ -382,7 +382,7 @@ extern char const *AT91F_PipeGetError(AT91S_PipeStatus msgId); extern const unsigned char bit_rev[256]; extern void CalculateCrc32(const unsigned char *,unsigned int, unsigned int *); -extern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); +extern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); extern void CalculateCrcHdlc(const unsigned char *, unsigned int, unsigned short *); extern void CalculateCrc16ccitt(const unsigned char *, unsigned int , unsigned short *); @@ -490,7 +490,7 @@ typedef struct _AT91S_RomBoot { const AT91PF_SVC_CRCHDLC CRCHDLC; const AT91PF_SVC_CRC32 CRC32; const AT91PS_SVC_CRC_BIT_REV Bit_Reverse_Array; - const AT91PS_SINE_TAB SineTab; + const AT91PS_SINE_TAB SineTab; const AT91PF_Sinus Sine; } AT91S_RomBoot, *AT91PS_RomBoot; diff --git a/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h b/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h index 43d58352342..a587c5712d1 100644 --- a/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h +++ b/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h @@ -50,7 +50,7 @@ typedef unsigned int AT91S_MCIDeviceStatus; #define AT91C_TIMEOUT_CMDRDY 30 ///////////////////////////////////////////////////////////////////////////////////////////////////// -// MMC & SDCard Structures +// MMC & SDCard Structures ///////////////////////////////////////////////////////////////////////////////////////////////////// /*-----------------------------------------------*/ @@ -70,7 +70,7 @@ typedef struct _AT91S_MciDeviceFeatures { unsigned char Card_Inserted; // (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED) unsigned int Relative_Card_Address; // RCA - unsigned int Max_Read_DataBlock_Length; // 2^(READ_BL_LEN) in CSD + unsigned int Max_Read_DataBlock_Length; // 2^(READ_BL_LEN) in CSD unsigned int Max_Write_DataBlock_Length; // 2^(WRITE_BL_LEN) in CSD unsigned char Read_Partial; // READ_BL_PARTIAL unsigned char Write_Partial; // WRITE_BL_PARTIAL @@ -79,7 +79,7 @@ typedef struct _AT91S_MciDeviceFeatures unsigned char Write_Block_Misalignment; // WRITE_BLK_MISALIGN unsigned char Sector_Size; // SECTOR_SIZE unsigned int Memory_Capacity; // Size in bits of the device - + } AT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ; /*---------------------------------------------*/ @@ -88,15 +88,15 @@ typedef struct _AT91S_MciDeviceFeatures typedef struct _AT91S_MciDevice { AT91PS_MciDeviceDesc pMCI_DeviceDesc; // MCI device descriptor - AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array + AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array }AT91S_MciDevice, *AT91PS_MciDevice; ///////////////////////////////////////////////////////////////////////////////////////////////////// -// MCI_CMD Register Value +// MCI_CMD Register Value ///////////////////////////////////////////////////////////////////////////////////////////////////// #define AT91C_POWER_ON_INIT (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD) -///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// // Class 0 & 1 commands: Basic commands and Read Stream commands ///////////////////////////////////////////////////////////////// @@ -137,7 +137,7 @@ typedef struct _AT91S_MciDevice //*------------------------------------------------ //* Class 4 commands: Block oriented write commands //*------------------------------------------------ - + #define AT91C_WRITE_BLOCK_CMD (24 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_BLOCK & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) #define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) #define AT91C_PROGRAM_CSD_CMD (27 | AT91C_MCI_RSPTYP_48 ) @@ -278,14 +278,14 @@ typedef struct _AT91S_MciDevice #define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) ///////////////////////////////////////////////////////////////////////////////////////////////////// -// MMC CSD register header File +// MMC CSD register header File // AT91C_CSD_xxx_S for shift value // AT91C_CSD_xxx_M for mask value ///////////////////////////////////////////////////////////////////////////////////////////////////// // First Response INT <=> CSD[3] : bits 0 to 31 -#define AT91C_CSD_BIT0_S 0 // [0:0] -#define AT91C_CSD_BIT0_M 0x01 +#define AT91C_CSD_BIT0_S 0 // [0:0] +#define AT91C_CSD_BIT0_M 0x01 #define AT91C_CSD_CRC_S 1 // [7:1] #define AT91C_CSD_CRC_M 0x7F #define AT91C_CSD_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility @@ -314,15 +314,15 @@ typedef struct _AT91S_MciDevice #define AT91C_CSD_WP_GRP_EN_M 0x01 // Seconde Response INT <=> CSD[2] : bits 32 to 63 -#define AT91C_CSD_v21_WP_GRP_SIZE_S 0 // [38:32] -#define AT91C_CSD_v21_WP_GRP_SIZE_M 0x7F +#define AT91C_CSD_v21_WP_GRP_SIZE_S 0 // [38:32] +#define AT91C_CSD_v21_WP_GRP_SIZE_M 0x7F #define AT91C_CSD_v21_SECT_SIZE_S 7 // [45:39] #define AT91C_CSD_v21_SECT_SIZE_M 0x7F #define AT91C_CSD_v21_ER_BLEN_EN_S 14 // [46:46] #define AT91C_CSD_v21_ER_BLEN_EN_M 0x01 -#define AT91C_CSD_v22_WP_GRP_SIZE_S 0 // [36:32] -#define AT91C_CSD_v22_WP_GRP_SIZE_M 0x1F +#define AT91C_CSD_v22_WP_GRP_SIZE_S 0 // [36:32] +#define AT91C_CSD_v22_WP_GRP_SIZE_M 0x1F #define AT91C_CSD_v22_ER_GRP_SIZE_S 5 // [41:37] #define AT91C_CSD_v22_ER_GRP_SIZE_M 0x1F #define AT91C_CSD_v22_SECT_SIZE_S 10 // [46:42] @@ -345,7 +345,7 @@ typedef struct _AT91S_MciDevice #define AT91C_CSD_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE #define AT91C_CSD_CSIZE_H_M 0x03FF // reserved 10 // [75:74] -// reserved 0x03 +// reserved 0x03 #define AT91C_CSD_DSR_I_S 12 // [76:76] #define AT91C_CSD_DSR_I_M 0x01 #define AT91C_CSD_RD_B_MIS_S 13 // [77:77] diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200.h b/target/linux/at91/image/dfboot/src/include/AT91RM9200.h index 0cd153b4210..c14bab005e3 100644 --- a/target/linux/at91/image/dfboot/src/include/AT91RM9200.h +++ b/target/linux/at91/image/dfboot/src/include/AT91RM9200.h @@ -10,7 +10,7 @@ // File Name : AT91RM9200.h // Object : AT91RM9200 definitions // Generated : AT91 SW Application Group 11/19/2003 (17:20:50) -// +// // CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// // CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// // CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// @@ -53,7 +53,7 @@ typedef struct _AT91S_SYS { AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // + AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register @@ -61,11 +61,11 @@ typedef struct _AT91S_SYS { AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // + AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // + AT91_REG Reserved2[45]; // AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register @@ -75,11 +75,11 @@ typedef struct _AT91S_SYS { AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // + AT91_REG Reserved3[7]; // AT91_REG DBGU_C1R; // Chip ID1 Register AT91_REG DBGU_C2R; // Chip ID2 Register AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // + AT91_REG Reserved4[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register @@ -90,19 +90,19 @@ typedef struct _AT91S_SYS { AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // + AT91_REG Reserved5[54]; // AT91_REG PIOA_PER; // PIO Enable Register AT91_REG PIOA_PDR; // PIO Disable Register AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // + AT91_REG Reserved6[1]; // AT91_REG PIOA_OER; // Output Enable Register AT91_REG PIOA_ODR; // Output Disable Registerr AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // + AT91_REG Reserved7[1]; // AT91_REG PIOA_IFER; // Input Filter Enable Register AT91_REG PIOA_IFDR; // Input Filter Disable Register AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // + AT91_REG Reserved8[1]; // AT91_REG PIOA_SODR; // Set Output Data Register AT91_REG PIOA_CODR; // Clear Output Data Register AT91_REG PIOA_ODSR; // Output Data Status Register @@ -114,31 +114,31 @@ typedef struct _AT91S_SYS { AT91_REG PIOA_MDER; // Multi-driver Enable Register AT91_REG PIOA_MDDR; // Multi-driver Disable Register AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // + AT91_REG Reserved9[1]; // AT91_REG PIOA_PPUDR; // Pull-up Disable Register AT91_REG PIOA_PPUER; // Pull-up Enable Register AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved10[1]; // + AT91_REG Reserved10[1]; // AT91_REG PIOA_ASR; // Select A Register AT91_REG PIOA_BSR; // Select B Register AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // + AT91_REG Reserved11[9]; // AT91_REG PIOA_OWER; // Output Write Enable Register AT91_REG PIOA_OWDR; // Output Write Disable Register AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // + AT91_REG Reserved12[85]; // AT91_REG PIOB_PER; // PIO Enable Register AT91_REG PIOB_PDR; // PIO Disable Register AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // + AT91_REG Reserved13[1]; // AT91_REG PIOB_OER; // Output Enable Register AT91_REG PIOB_ODR; // Output Disable Registerr AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // + AT91_REG Reserved14[1]; // AT91_REG PIOB_IFER; // Input Filter Enable Register AT91_REG PIOB_IFDR; // Input Filter Disable Register AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // + AT91_REG Reserved15[1]; // AT91_REG PIOB_SODR; // Set Output Data Register AT91_REG PIOB_CODR; // Clear Output Data Register AT91_REG PIOB_ODSR; // Output Data Status Register @@ -150,31 +150,31 @@ typedef struct _AT91S_SYS { AT91_REG PIOB_MDER; // Multi-driver Enable Register AT91_REG PIOB_MDDR; // Multi-driver Disable Register AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // + AT91_REG Reserved16[1]; // AT91_REG PIOB_PPUDR; // Pull-up Disable Register AT91_REG PIOB_PPUER; // Pull-up Enable Register AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved17[1]; // + AT91_REG Reserved17[1]; // AT91_REG PIOB_ASR; // Select A Register AT91_REG PIOB_BSR; // Select B Register AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // + AT91_REG Reserved18[9]; // AT91_REG PIOB_OWER; // Output Write Enable Register AT91_REG PIOB_OWDR; // Output Write Disable Register AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[85]; // + AT91_REG Reserved19[85]; // AT91_REG PIOC_PER; // PIO Enable Register AT91_REG PIOC_PDR; // PIO Disable Register AT91_REG PIOC_PSR; // PIO Status Register - AT91_REG Reserved20[1]; // + AT91_REG Reserved20[1]; // AT91_REG PIOC_OER; // Output Enable Register AT91_REG PIOC_ODR; // Output Disable Registerr AT91_REG PIOC_OSR; // Output Status Register - AT91_REG Reserved21[1]; // + AT91_REG Reserved21[1]; // AT91_REG PIOC_IFER; // Input Filter Enable Register AT91_REG PIOC_IFDR; // Input Filter Disable Register AT91_REG PIOC_IFSR; // Input Filter Status Register - AT91_REG Reserved22[1]; // + AT91_REG Reserved22[1]; // AT91_REG PIOC_SODR; // Set Output Data Register AT91_REG PIOC_CODR; // Clear Output Data Register AT91_REG PIOC_ODSR; // Output Data Status Register @@ -186,31 +186,31 @@ typedef struct _AT91S_SYS { AT91_REG PIOC_MDER; // Multi-driver Enable Register AT91_REG PIOC_MDDR; // Multi-driver Disable Register AT91_REG PIOC_MDSR; // Multi-driver Status Register - AT91_REG Reserved23[1]; // + AT91_REG Reserved23[1]; // AT91_REG PIOC_PPUDR; // Pull-up Disable Register AT91_REG PIOC_PPUER; // Pull-up Enable Register AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved24[1]; // + AT91_REG Reserved24[1]; // AT91_REG PIOC_ASR; // Select A Register AT91_REG PIOC_BSR; // Select B Register AT91_REG PIOC_ABSR; // AB Select Status Register - AT91_REG Reserved25[9]; // + AT91_REG Reserved25[9]; // AT91_REG PIOC_OWER; // Output Write Enable Register AT91_REG PIOC_OWDR; // Output Write Disable Register AT91_REG PIOC_OWSR; // Output Write Status Register - AT91_REG Reserved26[85]; // + AT91_REG Reserved26[85]; // AT91_REG PIOD_PER; // PIO Enable Register AT91_REG PIOD_PDR; // PIO Disable Register AT91_REG PIOD_PSR; // PIO Status Register - AT91_REG Reserved27[1]; // + AT91_REG Reserved27[1]; // AT91_REG PIOD_OER; // Output Enable Register AT91_REG PIOD_ODR; // Output Disable Registerr AT91_REG PIOD_OSR; // Output Status Register - AT91_REG Reserved28[1]; // + AT91_REG Reserved28[1]; // AT91_REG PIOD_IFER; // Input Filter Enable Register AT91_REG PIOD_IFDR; // Input Filter Disable Register AT91_REG PIOD_IFSR; // Input Filter Status Register - AT91_REG Reserved29[1]; // + AT91_REG Reserved29[1]; // AT91_REG PIOD_SODR; // Set Output Data Register AT91_REG PIOD_CODR; // Clear Output Data Register AT91_REG PIOD_ODSR; // Output Data Status Register @@ -222,39 +222,39 @@ typedef struct _AT91S_SYS { AT91_REG PIOD_MDER; // Multi-driver Enable Register AT91_REG PIOD_MDDR; // Multi-driver Disable Register AT91_REG PIOD_MDSR; // Multi-driver Status Register - AT91_REG Reserved30[1]; // + AT91_REG Reserved30[1]; // AT91_REG PIOD_PPUDR; // Pull-up Disable Register AT91_REG PIOD_PPUER; // Pull-up Enable Register AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved31[1]; // + AT91_REG Reserved31[1]; // AT91_REG PIOD_ASR; // Select A Register AT91_REG PIOD_BSR; // Select B Register AT91_REG PIOD_ABSR; // AB Select Status Register - AT91_REG Reserved32[9]; // + AT91_REG Reserved32[9]; // AT91_REG PIOD_OWER; // Output Write Enable Register AT91_REG PIOD_OWDR; // Output Write Disable Register AT91_REG PIOD_OWSR; // Output Write Status Register - AT91_REG Reserved33[85]; // + AT91_REG Reserved33[85]; // AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved34[1]; // + AT91_REG Reserved34[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved35[1]; // + AT91_REG Reserved35[1]; // AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG CKGR_PLLAR; // PLL A Register AT91_REG CKGR_PLLBR; // PLL B Register AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved36[3]; // + AT91_REG Reserved36[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved37[36]; // + AT91_REG Reserved37[36]; // AT91_REG ST_CR; // Control Register AT91_REG ST_PIMR; // Period Interval Mode Register AT91_REG ST_WDMR; // Watchdog Mode Register @@ -265,7 +265,7 @@ typedef struct _AT91S_SYS { AT91_REG ST_IMR; // Interrupt Mask Register AT91_REG ST_RTAR; // Real-time Alarm Register AT91_REG ST_CRTR; // Current Real-time Register - AT91_REG Reserved38[54]; // + AT91_REG Reserved38[54]; // AT91_REG RTC_CR; // Control Register AT91_REG RTC_MR; // Mode Register AT91_REG RTC_TIMR; // Time Register @@ -278,18 +278,18 @@ typedef struct _AT91S_SYS { AT91_REG RTC_IDR; // Interrupt Disable Register AT91_REG RTC_IMR; // Interrupt Mask Register AT91_REG RTC_VER; // Valid Entry Register - AT91_REG Reserved39[52]; // + AT91_REG Reserved39[52]; // AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved40[1]; // + AT91_REG Reserved40[1]; // AT91_REG MC_PUIA[16]; // MC Protection Unit Area AT91_REG MC_PUP; // MC Protection Unit Peripherals AT91_REG MC_PUER; // MC Protection Unit Enable Register - AT91_REG Reserved41[2]; // + AT91_REG Reserved41[2]; // AT91_REG EBI_CSA; // Chip Select Assignment Register AT91_REG EBI_CFGR; // Configuration Register - AT91_REG Reserved42[2]; // + AT91_REG Reserved42[2]; // AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register @@ -300,7 +300,7 @@ typedef struct _AT91S_SYS { AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register - AT91_REG Reserved43[3]; // + AT91_REG Reserved43[3]; // AT91_REG EBI_BFC_MR; // BFC Mode Register } AT91S_SYS, *AT91PS_SYS; @@ -312,15 +312,15 @@ typedef struct _AT91S_MC { AT91_REG MC_RCR; // MC Remap Control Register AT91_REG MC_ASR; // MC Abort Status Register AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[1]; // + AT91_REG Reserved0[1]; // AT91_REG MC_PUIA[16]; // MC Protection Unit Area AT91_REG MC_PUP; // MC Protection Unit Peripherals AT91_REG MC_PUER; // MC Protection Unit Enable Register } AT91S_MC, *AT91PS_MC; -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- #define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- #define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status #define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status #define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status @@ -336,7 +336,7 @@ typedef struct _AT91S_MC { #define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source #define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source #define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- #define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection #define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access #define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access @@ -360,8 +360,8 @@ typedef struct _AT91S_MC { #define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte #define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte #define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- #define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit // ***************************************************************************** @@ -382,7 +382,7 @@ typedef struct _AT91S_RTC { AT91_REG RTC_VER; // Valid Entry Register } AT91S_RTC, *AT91PS_RTC; -// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- +// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- #define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register #define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register #define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection @@ -394,37 +394,37 @@ typedef struct _AT91S_RTC { #define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). #define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). #define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). -// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- +// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- #define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode -// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- +// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- #define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second #define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute #define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour #define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator -// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- +// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- #define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century #define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year #define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month #define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day #define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date -// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- +// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- #define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable #define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm #define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour -// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- +// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- #define AT91C_RTC_MONTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable #define AT91C_RTC_DATEEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable -// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- +// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- #define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update #define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag #define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event #define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event #define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event -// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- +// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- +// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- +// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- +// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- +// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- #define AT91C_RTC_NVTIM ((unsigned int) 0x1 << 0) // (RTC) Non valid Time #define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar #define AT91C_RTC_NVTIMALR ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm @@ -446,27 +446,27 @@ typedef struct _AT91S_ST { AT91_REG ST_CRTR; // Current Real-time Register } AT91S_ST, *AT91PS_ST; -// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- +// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- #define AT91C_ST_WDRST ((unsigned int) 0x1 << 0) // (ST) Watchdog Timer Restart -// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- +// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- #define AT91C_ST_PIV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart -// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- +// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- #define AT91C_ST_WDV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart #define AT91C_ST_RSTEN ((unsigned int) 0x1 << 16) // (ST) Reset Enable #define AT91C_ST_EXTEN ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable -// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- +// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- #define AT91C_ST_RTPRES ((unsigned int) 0xFFFF << 0) // (ST) Real-time Timer Prescaler Value -// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- +// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- #define AT91C_ST_PITS ((unsigned int) 0x1 << 0) // (ST) Period Interval Timer Interrupt #define AT91C_ST_WDOVF ((unsigned int) 0x1 << 1) // (ST) Watchdog Overflow #define AT91C_ST_RTTINC ((unsigned int) 0x1 << 2) // (ST) Real-time Timer Increment #define AT91C_ST_ALMS ((unsigned int) 0x1 << 3) // (ST) Alarm Status -// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- +// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- +// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- +// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- +// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- #define AT91C_ST_ALMV ((unsigned int) 0xFFFFF << 0) // (ST) Alarm Value Value -// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- +// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- #define AT91C_ST_CRTV ((unsigned int) 0xFFFFF << 0) // (ST) Current Real-time Value // ***************************************************************************** @@ -476,13 +476,13 @@ typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // + AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[5]; // + AT91_REG Reserved1[5]; // AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved2[3]; // + AT91_REG Reserved2[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register @@ -490,7 +490,7 @@ typedef struct _AT91S_PMC { AT91_REG PMC_IMR; // Interrupt Mask Register } AT91S_PMC, *AT91PS_PMC; -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock #define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock #define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend @@ -503,9 +503,9 @@ typedef struct _AT91S_PMC { #define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected @@ -524,8 +524,8 @@ typedef struct _AT91S_PMC { #define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock #define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock #define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask #define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask @@ -538,9 +538,9 @@ typedef struct _AT91S_PMC { #define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Clock Generator Controler @@ -552,14 +552,14 @@ typedef struct _AT91S_CKGR { AT91_REG CKGR_PLLBR; // PLL B Register } AT91S_CKGR, *AT91PS_CKGR; -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 #define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed @@ -571,7 +571,7 @@ typedef struct _AT91S_CKGR { #define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier #define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source -// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 #define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed @@ -592,15 +592,15 @@ typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // + AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // + AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // + AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register @@ -612,15 +612,15 @@ typedef struct _AT91S_PIO { AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // + AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved4[1]; // + AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // + AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register @@ -640,11 +640,11 @@ typedef struct _AT91S_DBGU { AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // + AT91_REG Reserved0[7]; // AT91_REG DBGU_C1R; // Chip ID1 Register AT91_REG DBGU_C2R; // Chip ID2 Register AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // + AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register @@ -657,14 +657,14 @@ typedef struct _AT91S_DBGU { AT91_REG DBGU_PTSR; // PDC Transfer Status Register } AT91S_DBGU, *AT91PS_DBGU; -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity @@ -677,7 +677,7 @@ typedef struct _AT91S_DBGU { #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt @@ -690,10 +690,10 @@ typedef struct _AT91S_DBGU { #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG // ***************************************************************************** @@ -712,12 +712,12 @@ typedef struct _AT91S_PDC { AT91_REG PDC_PTSR; // PDC Transfer Status Register } AT91S_PDC, *AT91PS_PDC; -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller @@ -731,7 +731,7 @@ typedef struct _AT91S_AIC { AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // + AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register @@ -739,13 +739,13 @@ typedef struct _AT91S_AIC { AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // + AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register } AT91S_AIC, *AT91PS_AIC; -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level @@ -754,10 +754,10 @@ typedef struct _AT91S_AIC { #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask @@ -773,9 +773,9 @@ typedef struct _AT91S_SPI { AT91_REG SPI_IER; // Interrupt Enable Register AT91_REG SPI_IDR; // Interrupt Disable Register AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // + AT91_REG Reserved0[4]; // AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // + AT91_REG Reserved1[48]; // AT91_REG SPI_RPR; // Receive Pointer Register AT91_REG SPI_RCR; // Receive Counter Register AT91_REG SPI_TPR; // Transmit Pointer Register @@ -788,11 +788,11 @@ typedef struct _AT91S_SPI { AT91_REG SPI_PTSR; // PDC Transfer Status Register } AT91S_SPI, *AT91PS_SPI; -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select @@ -803,13 +803,13 @@ typedef struct _AT91S_SPI { #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error @@ -819,10 +819,10 @@ typedef struct _AT91S_SPI { #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer @@ -845,14 +845,14 @@ typedef struct _AT91S_SPI { typedef struct _AT91S_SSC { AT91_REG SSC_CR; // Control Register AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // + AT91_REG Reserved0[2]; // AT91_REG SSC_RCMR; // Receive Clock ModeRegister AT91_REG SSC_RFMR; // Receive Frame Mode Register AT91_REG SSC_TCMR; // Transmit Clock Mode Register AT91_REG SSC_TFMR; // Transmit Frame Mode Register AT91_REG SSC_RHR; // Receive Holding Register AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // + AT91_REG Reserved1[2]; // AT91_REG SSC_RSHR; // Receive Sync Holding Register AT91_REG SSC_TSHR; // Transmit Sync Holding Register AT91_REG SSC_RC0R; // Receive Compare 0 Register @@ -861,7 +861,7 @@ typedef struct _AT91S_SSC { AT91_REG SSC_IER; // Interrupt Enable Register AT91_REG SSC_IDR; // Interrupt Disable Register AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved2[44]; // + AT91_REG Reserved2[44]; // AT91_REG SSC_RPR; // Receive Pointer Register AT91_REG SSC_RCR; // Receive Counter Register AT91_REG SSC_TPR; // Transmit Pointer Register @@ -874,13 +874,13 @@ typedef struct _AT91S_SSC { AT91_REG SSC_PTSR; // PDC Transfer Status Register } AT91S_SSC, *AT91PS_SSC; -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal @@ -908,7 +908,7 @@ typedef struct _AT91S_SSC { #define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First @@ -922,11 +922,11 @@ typedef struct _AT91S_SSC { #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission @@ -941,9 +941,9 @@ typedef struct _AT91S_SSC { #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Usart @@ -960,12 +960,12 @@ typedef struct _AT91S_USART { AT91_REG US_BRGR; // Baud Rate Generator Register AT91_REG US_RTOR; // Receiver Time-out Register AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // + AT91_REG Reserved0[5]; // AT91_REG US_FIDI; // FI_DI_Ratio Register AT91_REG US_NER; // Nb Errors Register AT91_REG US_XXR; // XON_XOFF Register AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved1[44]; // + AT91_REG Reserved1[44]; // AT91_REG US_RPR; // Receive Pointer Register AT91_REG US_RCR; // Receive Counter Register AT91_REG US_TPR; // Transmit Pointer Register @@ -978,7 +978,7 @@ typedef struct _AT91S_USART { AT91_REG US_PTSR; // PDC Transfer Status Register } AT91S_USART, *AT91PS_USART; -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break @@ -991,7 +991,7 @@ typedef struct _AT91S_USART { #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 @@ -1024,7 +1024,7 @@ typedef struct _AT91S_USART { #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached @@ -1033,9 +1033,9 @@ typedef struct _AT91S_USART { #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input @@ -1050,7 +1050,7 @@ typedef struct _AT91S_TWI { AT91_REG TWI_SMR; // Slave Mode Register AT91_REG TWI_IADR; // Internal Address Register AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved0[3]; // + AT91_REG Reserved0[3]; // AT91_REG TWI_SR; // Status Register AT91_REG TWI_IER; // Interrupt Enable Register AT91_REG TWI_IDR; // Interrupt Disable Register @@ -1059,7 +1059,7 @@ typedef struct _AT91S_TWI { AT91_REG TWI_THR; // Transmit Holding Register } AT91S_TWI, *AT91PS_TWI; -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled @@ -1067,7 +1067,7 @@ typedef struct _AT91S_TWI { #define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled #define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address @@ -1075,13 +1075,13 @@ typedef struct _AT91S_TWI { #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- #define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY @@ -1092,9 +1092,9 @@ typedef struct _AT91S_TWI { #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged #define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Multimedia Card Interface @@ -1106,16 +1106,16 @@ typedef struct _AT91S_MCI { AT91_REG MCI_SDCR; // MCI SD Card Register AT91_REG MCI_ARGR; // MCI Argument Register AT91_REG MCI_CMDR; // MCI Command Register - AT91_REG Reserved0[2]; // + AT91_REG Reserved0[2]; // AT91_REG MCI_RSPR[4]; // MCI Response Register AT91_REG MCI_RDR; // MCI Receive Data Register AT91_REG MCI_TDR; // MCI Transmit Data Register - AT91_REG Reserved1[2]; // + AT91_REG Reserved1[2]; // AT91_REG MCI_SR; // MCI Status Register AT91_REG MCI_IER; // MCI Interrupt Enable Register AT91_REG MCI_IDR; // MCI Interrupt Disable Register AT91_REG MCI_IMR; // MCI Interrupt Mask Register - AT91_REG Reserved2[44]; // + AT91_REG Reserved2[44]; // AT91_REG MCI_RPR; // Receive Pointer Register AT91_REG MCI_RCR; // Receive Counter Register AT91_REG MCI_TPR; // Transmit Pointer Register @@ -1128,18 +1128,18 @@ typedef struct _AT91S_MCI { AT91_REG MCI_PTSR; // PDC Transfer Status Register } AT91S_MCI, *AT91PS_MCI; -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- #define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable #define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable #define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable #define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- #define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider #define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider #define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value #define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode #define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- #define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number #define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier #define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 @@ -1150,10 +1150,10 @@ typedef struct _AT91S_MCI { #define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 #define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 #define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- #define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector #define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- #define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number #define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type #define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response @@ -1176,7 +1176,7 @@ typedef struct _AT91S_MCI { #define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type #define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type #define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- #define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag #define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag #define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag @@ -1196,9 +1196,9 @@ typedef struct _AT91S_MCI { #define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag #define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag #define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR USB Device Interface @@ -1207,32 +1207,32 @@ typedef struct _AT91S_UDP { AT91_REG UDP_NUM; // Frame Number Register AT91_REG UDP_GLBSTATE; // Global State Register AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // + AT91_REG Reserved0[1]; // AT91_REG UDP_IER; // Interrupt Enable Register AT91_REG UDP_IDR; // Interrupt Disable Register AT91_REG UDP_IMR; // Interrupt Mask Register AT91_REG UDP_ISR; // Interrupt Status Register AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // + AT91_REG Reserved1[1]; // AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // + AT91_REG Reserved2[1]; // AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register } AT91S_UDP, *AT91PS_UDP; -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt @@ -1246,12 +1246,12 @@ typedef struct _AT91S_UDP { #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 @@ -1260,7 +1260,7 @@ typedef struct _AT91S_UDP { #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 #define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 #define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) @@ -1287,7 +1287,7 @@ typedef struct _AT91S_UDP { typedef struct _AT91S_TC { AT91_REG TC_CCR; // Channel Control Register AT91_REG TC_CMR; // Channel Mode Register - AT91_REG Reserved0[2]; // + AT91_REG Reserved0[2]; // AT91_REG TC_CV; // Counter Value AT91_REG TC_RA; // Register A AT91_REG TC_RB; // Register B @@ -1298,11 +1298,11 @@ typedef struct _AT91S_TC { AT91_REG TC_IMR; // Interrupt Mask Register } AT91S_TC, *AT91PS_TC; -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection @@ -1322,7 +1322,7 @@ typedef struct _AT91S_TC { #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set @@ -1363,7 +1363,7 @@ typedef struct _AT91S_TC { #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare @@ -1375,27 +1375,27 @@ typedef struct _AT91S_TC { #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface // ***************************************************************************** typedef struct _AT91S_TCB { AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // + AT91_REG Reserved0[4]; // AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // + AT91_REG Reserved1[4]; // AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // + AT91_REG Reserved2[4]; // AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BMR; // TC Block Mode Register } AT91S_TCB, *AT91PS_TCB; -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 @@ -1452,14 +1452,14 @@ typedef struct _AT91S_EMAC { AT91_REG EMAC_TCR; // Transmit Control Register AT91_REG EMAC_TSR; // Transmit Status Register AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG Reserved0[1]; // + AT91_REG Reserved0[1]; // AT91_REG EMAC_RSR; // Receive Status Register AT91_REG EMAC_ISR; // Interrupt Status Register AT91_REG EMAC_IER; // Interrupt Enable Register AT91_REG EMAC_IDR; // Interrupt Disable Register AT91_REG EMAC_IMR; // Interrupt Mask Register AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG Reserved1[2]; // + AT91_REG Reserved1[2]; // AT91_REG EMAC_FRA; // Frames Transmitted OK Register AT91_REG EMAC_SCOL; // Single Collision Frame Register AT91_REG EMAC_MCOL; // Multiple Collision Frame Register @@ -1477,7 +1477,7 @@ typedef struct _AT91S_EMAC { AT91_REG EMAC_USF; // Undersize Frame Register AT91_REG EMAC_SQEE; // SQE Test Error Register AT91_REG EMAC_DRFC; // Discarded RX Frame Register - AT91_REG Reserved2[3]; // + AT91_REG Reserved2[3]; // AT91_REG EMAC_HSH; // Hash Address High[63:32] AT91_REG EMAC_HSL; // Hash Address Low[31:0] AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes @@ -1490,74 +1490,74 @@ typedef struct _AT91S_EMAC { AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr } AT91S_EMAC, *AT91PS_EMAC; -// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- +// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) // (EMAC) Bit rate. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) // (EMAC) Bit rate. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) // (EMAC) -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) // (EMAC) -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) // (EMAC) +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- +#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) // (EMAC) +#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) // (EMAC) +#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) // (EMAC) // ***************************************************************************** // SOFTWARE API DEFINITION FOR External Bus Interface @@ -1567,7 +1567,7 @@ typedef struct _AT91S_EBI { AT91_REG EBI_CFGR; // Configuration Register } AT91S_EBI, *AT91PS_EBI; -// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- #define AT91C_EBI_CS0A ((unsigned int) 0x1 << 0) // (EBI) Chip Select 0 Assignment #define AT91C_EBI_CS0A_SMC ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. #define AT91C_EBI_CS0A_BFC ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. @@ -1580,7 +1580,7 @@ typedef struct _AT91S_EBI { #define AT91C_EBI_CS4A ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 Assignment #define AT91C_EBI_CS4A_SMC ((unsigned int) 0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. #define AT91C_EBI_CS4A_SMC_CompactFlash ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- +// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- #define AT91C_EBI_DBPUC ((unsigned int) 0x1 << 0) // (EBI) Data Bus Pull-Up Configuration #define AT91C_EBI_EBSEN ((unsigned int) 0x1 << 1) // (EBI) Bus Sharing Enable @@ -1591,7 +1591,7 @@ typedef struct _AT91S_SMC2 { AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register } AT91S_SMC2, *AT91PS_SMC2; -// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- #define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) // (SMC2) Number of Wait States #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) // (SMC2) Wait State Enable #define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) // (SMC2) Data Float Time @@ -1623,7 +1623,7 @@ typedef struct _AT91S_SDRC { AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register } AT91S_SDRC, *AT91PS_SDRC; -// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRC_MODE ((unsigned int) 0xF << 0) // (SDRC) Mode #define AT91C_SDRC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRC) Normal Mode #define AT91C_SDRC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRC) NOP Command @@ -1633,9 +1633,9 @@ typedef struct _AT91S_SDRC { #define AT91C_SDRC_DBW ((unsigned int) 0x1 << 4) // (SDRC) Data Bus Width #define AT91C_SDRC_DBW_32_BITS ((unsigned int) 0x0 << 4) // (SDRC) 32 Bits datas bus #define AT91C_SDRC_DBW_16_BITS ((unsigned int) 0x1 << 4) // (SDRC) 16 Bits datas bus -// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- #define AT91C_SDRC_COUNT ((unsigned int) 0xFFF << 0) // (SDRC) Refresh Counter -// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRC_NC ((unsigned int) 0x3 << 0) // (SDRC) Number of Column Bits #define AT91C_SDRC_NC_8 ((unsigned int) 0x0) // (SDRC) 8 Bits #define AT91C_SDRC_NC_9 ((unsigned int) 0x1) // (SDRC) 9 Bits @@ -1656,15 +1656,15 @@ typedef struct _AT91S_SDRC { #define AT91C_SDRC_TRCD ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles #define AT91C_SDRC_TRAS ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles #define AT91C_SDRC_TXSR ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles -// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- #define AT91C_SDRC_SRCB ((unsigned int) 0x1 << 0) // (SDRC) Self-refresh Command Bit -// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- #define AT91C_SDRC_LPCB ((unsigned int) 0x1 << 0) // (SDRC) Low-power Command Bit -// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- #define AT91C_SDRC_RES ((unsigned int) 0x1 << 0) // (SDRC) Refresh Error Status -// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Burst Flash Controller Interface @@ -1673,7 +1673,7 @@ typedef struct _AT91S_BFC { AT91_REG BFC_MR; // BFC Mode Register } AT91S_BFC, *AT91PS_BFC; -// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- +// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- #define AT91C_BFC_BFCOM ((unsigned int) 0x3 << 0) // (BFC) Burst Flash Controller Operating Mode #define AT91C_BFC_BFCOM_DISABLED ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high. #define AT91C_BFC_BFCOM_ASYNC ((unsigned int) 0x1) // (BFC) Asynchronous @@ -1701,15 +1701,15 @@ typedef struct _AT91S_BFC { // ***************************************************************************** // REGISTER ADDRESS DEFINITION FOR AT91RM9200 // ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for MC peripheral ========== +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for MC peripheral ========== #define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register #define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals #define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for RTC peripheral ========== +// ========== Register definition for RTC peripheral ========== #define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register #define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register #define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register @@ -1722,7 +1722,7 @@ typedef struct _AT91S_BFC { #define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register #define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register #define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register -// ========== Register definition for ST peripheral ========== +// ========== Register definition for ST peripheral ========== #define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register #define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register #define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register @@ -1733,7 +1733,7 @@ typedef struct _AT91S_BFC { #define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register #define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register #define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register -// ========== Register definition for PMC peripheral ========== +// ========== Register definition for PMC peripheral ========== #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register @@ -1746,12 +1746,12 @@ typedef struct _AT91S_BFC { #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for CKGR peripheral ========== +// ========== Register definition for CKGR peripheral ========== #define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register #define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PIOD peripheral ========== +// ========== Register definition for PIOD peripheral ========== #define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register #define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register #define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register @@ -1781,7 +1781,7 @@ typedef struct _AT91S_BFC { #define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register #define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register #define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register -// ========== Register definition for PIOC peripheral ========== +// ========== Register definition for PIOC peripheral ========== #define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register #define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr #define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register @@ -1811,7 +1811,7 @@ typedef struct _AT91S_BFC { #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register #define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register #define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register -// ========== Register definition for PIOB peripheral ========== +// ========== Register definition for PIOB peripheral ========== #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register @@ -1841,7 +1841,7 @@ typedef struct _AT91S_BFC { #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for PIOA peripheral ========== +// ========== Register definition for PIOA peripheral ========== #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register @@ -1871,7 +1871,7 @@ typedef struct _AT91S_BFC { #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for DBGU peripheral ========== +// ========== Register definition for DBGU peripheral ========== #define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register @@ -1884,7 +1884,7 @@ typedef struct _AT91S_BFC { #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== +// ========== Register definition for PDC_DBGU peripheral ========== #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register @@ -1895,7 +1895,7 @@ typedef struct _AT91S_BFC { #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for AIC peripheral ========== +// ========== Register definition for AIC peripheral ========== #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register @@ -1914,7 +1914,7 @@ typedef struct _AT91S_BFC { #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_SPI peripheral ========== +// ========== Register definition for PDC_SPI peripheral ========== #define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register #define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register #define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register @@ -1925,7 +1925,7 @@ typedef struct _AT91S_BFC { #define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register #define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register #define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== +// ========== Register definition for SPI peripheral ========== #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register #define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register #define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register @@ -1935,7 +1935,7 @@ typedef struct _AT91S_BFC { #define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register #define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register #define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_SSC2 peripheral ========== +// ========== Register definition for PDC_SSC2 peripheral ========== #define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register #define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register #define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register @@ -1946,7 +1946,7 @@ typedef struct _AT91S_BFC { #define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register #define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register #define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register -// ========== Register definition for SSC2 peripheral ========== +// ========== Register definition for SSC2 peripheral ========== #define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register #define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register #define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register @@ -1963,7 +1963,7 @@ typedef struct _AT91S_BFC { #define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register #define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register #define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register -// ========== Register definition for PDC_SSC1 peripheral ========== +// ========== Register definition for PDC_SSC1 peripheral ========== #define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register #define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register #define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register @@ -1974,7 +1974,7 @@ typedef struct _AT91S_BFC { #define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register #define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register #define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== +// ========== Register definition for SSC1 peripheral ========== #define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register #define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register #define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register @@ -1991,7 +1991,7 @@ typedef struct _AT91S_BFC { #define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register #define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register #define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_SSC0 peripheral ========== +// ========== Register definition for PDC_SSC0 peripheral ========== #define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register #define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register #define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register @@ -2002,7 +2002,7 @@ typedef struct _AT91S_BFC { #define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register #define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register #define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== +// ========== Register definition for SSC0 peripheral ========== #define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register #define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register #define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register @@ -2019,7 +2019,7 @@ typedef struct _AT91S_BFC { #define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register #define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister #define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_US3 peripheral ========== +// ========== Register definition for PDC_US3 peripheral ========== #define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register #define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register #define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register @@ -2030,7 +2030,7 @@ typedef struct _AT91S_BFC { #define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register #define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register #define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register -// ========== Register definition for US3 peripheral ========== +// ========== Register definition for US3 peripheral ========== #define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register #define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register #define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register @@ -2046,7 +2046,7 @@ typedef struct _AT91S_BFC { #define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register #define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register #define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register -// ========== Register definition for PDC_US2 peripheral ========== +// ========== Register definition for PDC_US2 peripheral ========== #define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register #define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register #define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register @@ -2057,7 +2057,7 @@ typedef struct _AT91S_BFC { #define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register #define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register #define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== +// ========== Register definition for US2 peripheral ========== #define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register #define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register #define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register @@ -2073,7 +2073,7 @@ typedef struct _AT91S_BFC { #define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register #define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register #define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== +// ========== Register definition for PDC_US1 peripheral ========== #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register @@ -2084,7 +2084,7 @@ typedef struct _AT91S_BFC { #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== +// ========== Register definition for US1 peripheral ========== #define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register @@ -2100,7 +2100,7 @@ typedef struct _AT91S_BFC { #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== +// ========== Register definition for PDC_US0 peripheral ========== #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register @@ -2111,7 +2111,7 @@ typedef struct _AT91S_BFC { #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== +// ========== Register definition for US0 peripheral ========== #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register @@ -2127,7 +2127,7 @@ typedef struct _AT91S_BFC { #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== +// ========== Register definition for TWI peripheral ========== #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register @@ -2139,7 +2139,7 @@ typedef struct _AT91S_BFC { #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_MCI peripheral ========== +// ========== Register definition for PDC_MCI peripheral ========== #define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register #define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register #define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register @@ -2150,7 +2150,7 @@ typedef struct _AT91S_BFC { #define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register #define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register #define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register -// ========== Register definition for MCI peripheral ========== +// ========== Register definition for MCI peripheral ========== #define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register #define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register #define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register @@ -2164,7 +2164,7 @@ typedef struct _AT91S_BFC { #define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register #define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register #define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register -// ========== Register definition for UDP peripheral ========== +// ========== Register definition for UDP peripheral ========== #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register @@ -2176,7 +2176,7 @@ typedef struct _AT91S_BFC { #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -// ========== Register definition for TC5 peripheral ========== +// ========== Register definition for TC5 peripheral ========== #define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register #define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register #define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register @@ -2187,7 +2187,7 @@ typedef struct _AT91S_BFC { #define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register #define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C #define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A -// ========== Register definition for TC4 peripheral ========== +// ========== Register definition for TC4 peripheral ========== #define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register #define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register #define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C @@ -2198,7 +2198,7 @@ typedef struct _AT91S_BFC { #define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B #define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value #define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC3 peripheral ========== +// ========== Register definition for TC3 peripheral ========== #define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register #define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value #define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register @@ -2209,10 +2209,10 @@ typedef struct _AT91S_BFC { #define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register #define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B #define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TCB1 peripheral ========== +// ========== Register definition for TCB1 peripheral ========== #define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register #define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register -// ========== Register definition for TC2 peripheral ========== +// ========== Register definition for TC2 peripheral ========== #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C @@ -2223,7 +2223,7 @@ typedef struct _AT91S_BFC { #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== +// ========== Register definition for TC1 peripheral ========== #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C @@ -2234,7 +2234,7 @@ typedef struct _AT91S_BFC { #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== +// ========== Register definition for TC0 peripheral ========== #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C @@ -2245,10 +2245,10 @@ typedef struct _AT91S_BFC { #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== +// ========== Register definition for TCB0 peripheral ========== #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for UHP peripheral ========== +// ========== Register definition for UHP peripheral ========== #define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A #define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register #define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B @@ -2271,7 +2271,7 @@ typedef struct _AT91S_BFC { #define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start #define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold #define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number -// ========== Register definition for EMAC peripheral ========== +// ========== Register definition for EMAC peripheral ========== #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register #define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32] @@ -2311,12 +2311,12 @@ typedef struct _AT91S_BFC { #define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register #define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register -// ========== Register definition for EBI peripheral ========== +// ========== Register definition for EBI peripheral ========== #define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register #define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register -// ========== Register definition for SMC2 peripheral ========== +// ========== Register definition for SMC2 peripheral ========== #define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register -// ========== Register definition for SDRC peripheral ========== +// ========== Register definition for SDRC peripheral ========== #define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register #define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register #define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register @@ -2326,7 +2326,7 @@ typedef struct _AT91S_BFC { #define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register #define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register #define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register -// ========== Register definition for BFC peripheral ========== +// ========== Register definition for BFC peripheral ========== #define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register // ***************************************************************************** @@ -2579,16 +2579,16 @@ typedef struct _AT91S_BFC { #define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) // PMC Programmable Clock Output 3 #define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 #define AT91C_PIO_PD11 ((unsigned int) 1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) // +#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) // #define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 #define AT91C_PIO_PD12 ((unsigned int) 1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) // +#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) // #define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) // ETM Trace Packet 0 #define AT91C_PIO_PD13 ((unsigned int) 1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) // +#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) // #define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) // ETM Trace Packet 1 #define AT91C_PIO_PD14 ((unsigned int) 1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) // +#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) // #define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) // ETM Trace Packet 2 #define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15 #define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) // SSC Transmit data @@ -2652,7 +2652,7 @@ typedef struct _AT91S_BFC { // ***************************************************************************** #define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A #define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B #define AT91C_ID_PIOC ((unsigned int) 4) // Parallel IO Controller C #define AT91C_ID_PIOD ((unsigned int) 5) // Parallel IO Controller D diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h b/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h index dabab01c770..168880818cd 100644 --- a/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h +++ b/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h @@ -10,7 +10,7 @@ // File Name : AT91RM9200.h // Object : AT91RM9200 definitions // Generated : AT91 SW Application Group 11/19/2003 (17:20:51) -// +// // CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// // CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// // CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// @@ -52,9 +52,9 @@ #define MC_PUIA (16) // MC Protection Unit Area #define MC_PUP (80) // MC Protection Unit Peripherals #define MC_PUER (84) // MC Protection Unit Enable Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- #define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- #define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status #define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status #define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status @@ -70,7 +70,7 @@ #define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source #define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source #define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- #define AT91C_MC_PROT (0x3 << 0) // (MC) Protection #define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access #define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access @@ -94,8 +94,8 @@ #define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte #define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte #define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address -// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- -// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- #define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit // ***************************************************************************** @@ -114,7 +114,7 @@ #define RTC_IDR (36) // Interrupt Disable Register #define RTC_IMR (40) // Interrupt Mask Register #define RTC_VER (44) // Valid Entry Register -// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- +// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- #define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register #define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register #define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection @@ -126,37 +126,37 @@ #define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). #define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). #define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). -// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- +// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- #define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode -// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- +// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- #define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second #define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute #define AT91C_RTC_HOUR (0x1F << 16) // (RTC) Current Hour #define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator -// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- +// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- #define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century #define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year #define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month #define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day #define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date -// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- +// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- #define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable #define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm #define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour -// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- +// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- #define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable #define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable -// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- +// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- #define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update #define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag #define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event #define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event #define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event -// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- -// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- -// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- -// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- -// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- +// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- +// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- +// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- +// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- +// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- #define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time #define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar #define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm @@ -176,27 +176,27 @@ #define ST_IMR (28) // Interrupt Mask Register #define ST_RTAR (32) // Real-time Alarm Register #define ST_CRTR (36) // Current Real-time Register -// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- +// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- #define AT91C_ST_WDRST (0x1 << 0) // (ST) Watchdog Timer Restart -// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- +// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- #define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart -// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- +// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- #define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart #define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable #define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable -// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- +// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- #define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value -// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- +// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- #define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt #define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow #define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment #define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status -// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- -// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- -// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- -// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- +// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- +// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- +// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- +// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- #define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value -// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- +// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- #define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value // ***************************************************************************** @@ -215,7 +215,7 @@ #define PMC_IDR (100) // Interrupt Disable Register #define PMC_SR (104) // Status Register #define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock #define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock #define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend @@ -228,9 +228,9 @@ #define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected @@ -249,8 +249,8 @@ #define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock #define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock #define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask #define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask @@ -263,9 +263,9 @@ #define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Clock Generator Controler @@ -275,14 +275,14 @@ #define CKGR_MCFR ( 4) // Main Clock Frequency Register #define CKGR_PLLAR ( 8) // PLL A Register #define CKGR_PLLBR (12) // PLL B Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0 #define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed @@ -294,7 +294,7 @@ #define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier #define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source -// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected #define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0 #define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed @@ -368,14 +368,14 @@ #define DBGU_TNCR (284) // Transmit Next Counter Register #define DBGU_PTCR (288) // PDC Transfer Control Register #define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity @@ -388,7 +388,7 @@ #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt @@ -401,10 +401,10 @@ #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG // ***************************************************************************** @@ -421,12 +421,12 @@ #define PDC_TNCR (28) // Transmit Next Counter Register #define PDC_PTCR (32) // PDC Transfer Control Register #define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller @@ -450,7 +450,7 @@ #define AIC_FFER (320) // Fast Forcing Enable Register #define AIC_FFDR (324) // Fast Forcing Disable Register #define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level @@ -459,10 +459,10 @@ #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask @@ -489,11 +489,11 @@ #define SPI_TNCR (284) // Transmit Next Counter Register #define SPI_PTCR (288) // PDC Transfer Control Register #define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select @@ -504,13 +504,13 @@ #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error @@ -520,10 +520,10 @@ #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer @@ -570,13 +570,13 @@ #define SSC_TNCR (284) // Transmit Next Counter Register #define SSC_PTCR (288) // PDC Transfer Control Register #define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal @@ -604,7 +604,7 @@ #define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First @@ -618,11 +618,11 @@ #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission @@ -637,9 +637,9 @@ #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Usart @@ -670,7 +670,7 @@ #define US_TNCR (284) // Transmit Next Counter Register #define US_PTCR (288) // PDC Transfer Control Register #define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits #define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break #define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break @@ -683,7 +683,7 @@ #define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable #define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable #define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode #define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal #define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 @@ -716,7 +716,7 @@ #define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK #define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions #define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break #define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out #define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached @@ -725,9 +725,9 @@ #define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag #define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- #define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input #define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input #define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input @@ -748,7 +748,7 @@ #define TWI_IMR (44) // Interrupt Mask Register #define TWI_RHR (48) // Receive Holding Register #define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled @@ -756,7 +756,7 @@ #define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled #define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address @@ -764,13 +764,13 @@ #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- #define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- #define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY #define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY @@ -781,9 +781,9 @@ #define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error #define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged #define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Multimedia Card Interface @@ -812,18 +812,18 @@ #define MCI_TNCR (284) // Transmit Next Counter Register #define MCI_PTCR (288) // PDC Transfer Control Register #define MCI_PTSR (292) // PDC Transfer Status Register -// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- #define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable #define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable #define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable #define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable -// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- #define AT91C_MCI_CLKDIV (0x1 << 0) // (MCI) Clock Divider #define AT91C_MCI_PWSDIV (0x1 << 8) // (MCI) Power Saving Divider #define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value #define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode #define AT91C_MCI_BLKLEN (0x1 << 18) // (MCI) Data Block Length -// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- #define AT91C_MCI_DTOCYC (0x1 << 0) // (MCI) Data Timeout Cycle Number #define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier #define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 @@ -834,10 +834,10 @@ #define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 #define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 #define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 -// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- #define AT91C_MCI_SCDSEL (0x1 << 0) // (MCI) SD Card Selector #define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width -// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- #define AT91C_MCI_CMDNB (0x1F << 0) // (MCI) Command Number #define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type #define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response @@ -860,7 +860,7 @@ #define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type #define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type #define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type -// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- #define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag #define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag #define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag @@ -880,9 +880,9 @@ #define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag #define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag #define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag -// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- -// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- -// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR USB Device Interface @@ -899,19 +899,19 @@ #define UDP_RSTEP (40) // Reset Endpoint Register #define UDP_CSR (48) // Endpoint Control and Status Register #define UDP_FDR (80) // Endpoint FIFO Data Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- #define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats #define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error #define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- #define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable #define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured #define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable #define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- #define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value #define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- #define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt @@ -925,12 +925,12 @@ #define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt #define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt #define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- #define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- #define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 #define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 #define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 @@ -939,7 +939,7 @@ #define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 #define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 #define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- #define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR #define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 #define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) @@ -974,11 +974,11 @@ #define TC_IER (36) // Interrupt Enable Register #define TC_IDR (40) // Interrupt Disable Register #define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection @@ -998,7 +998,7 @@ #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_WAVE (0x1 << 15) // (TC) #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set @@ -1039,7 +1039,7 @@ #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare @@ -1051,9 +1051,9 @@ #define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface @@ -1064,9 +1064,9 @@ #define TCB_TC2 (128) // TC Channel 2 #define TCB_BCR (192) // TC Block Control Register #define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 @@ -1154,74 +1154,74 @@ #define EMAC_SA3H (172) // Specific Address 3 High, Last 2 bytes #define EMAC_SA4L (176) // Specific Address 4 Low, First 4 bytes #define EMAC_SA4H (180) // Specific Address 4 High, Last 2 bytesr -// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- +// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- #define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LBL (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CSR (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_ISR (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WES (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_BR (0x1 << 2) // (EMAC) Bit rate. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_LBL (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CSR (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_ISR (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WES (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_BR (0x1 << 2) // (EMAC) Bit rate. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. #define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) #define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 #define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 #define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 #define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_RMII (0x1 << 13) // (EMAC) -// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- -#define AT91C_EMAC_LEN (0x7FF << 0) // (EMAC) -#define AT91C_EMAC_NCRC (0x1 << 15) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- -#define AT91C_EMAC_OVR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLE (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXIDLE (0x1 << 3) // (EMAC) -#define AT91C_EMAC_BNQ (0x1 << 4) // (EMAC) -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_DONE (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOM (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RBNA (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TOVR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUND (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RTRY (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TBRE (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOM (0x1 << 7) // (EMAC) -#define AT91C_EMAC_TIDLE (0x1 << 8) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_HIGH (0x1 << 30) // (EMAC) -#define AT91C_EMAC_LOW (0x1 << 31) // (EMAC) +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_RMII (0x1 << 13) // (EMAC) +// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- +#define AT91C_EMAC_LEN (0x7FF << 0) // (EMAC) +#define AT91C_EMAC_NCRC (0x1 << 15) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- +#define AT91C_EMAC_OVR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLE (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXIDLE (0x1 << 3) // (EMAC) +#define AT91C_EMAC_BNQ (0x1 << 4) // (EMAC) +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_DONE (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOM (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RBNA (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TOVR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUND (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RTRY (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TBRE (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOM (0x1 << 7) // (EMAC) +#define AT91C_EMAC_TIDLE (0x1 << 8) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_HIGH (0x1 << 30) // (EMAC) +#define AT91C_EMAC_LOW (0x1 << 31) // (EMAC) // ***************************************************************************** // SOFTWARE API DEFINITION FOR External Bus Interface @@ -1229,7 +1229,7 @@ // *** Register offset in AT91S_EBI structure *** #define EBI_CSA ( 0) // Chip Select Assignment Register #define EBI_CFGR ( 4) // Configuration Register -// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- #define AT91C_EBI_CS0A (0x1 << 0) // (EBI) Chip Select 0 Assignment #define AT91C_EBI_CS0A_SMC (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. #define AT91C_EBI_CS0A_BFC (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. @@ -1242,7 +1242,7 @@ #define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment #define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. #define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. -// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- +// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- #define AT91C_EBI_DBPUC (0x1 << 0) // (EBI) Data Bus Pull-Up Configuration #define AT91C_EBI_EBSEN (0x1 << 1) // (EBI) Bus Sharing Enable @@ -1251,7 +1251,7 @@ // ***************************************************************************** // *** Register offset in AT91S_SMC2 structure *** #define SMC2_CSR ( 0) // SMC2 Chip Select Register -// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- #define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States #define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable #define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time @@ -1281,7 +1281,7 @@ #define SDRC_IDR (24) // SDRAM Controller Interrupt Disable Register #define SDRC_IMR (28) // SDRAM Controller Interrupt Mask Register #define SDRC_ISR (32) // SDRAM Controller Interrupt Mask Register -// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode #define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode #define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command @@ -1291,9 +1291,9 @@ #define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width #define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus #define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus -// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- #define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter -// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits #define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits #define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits @@ -1314,22 +1314,22 @@ #define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles #define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles #define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles -// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- #define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit -// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- #define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit -// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- #define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status -// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- -// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- -// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Burst Flash Controller Interface // ***************************************************************************** // *** Register offset in AT91S_BFC structure *** #define BFC_MR ( 0) // BFC Mode Register -// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- +// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- #define AT91C_BFC_BFCOM (0x3 << 0) // (BFC) Burst Flash Controller Operating Mode #define AT91C_BFC_BFCOM_DISABLED (0x0) // (BFC) NPCS0 is driven by the SMC or remains high. #define AT91C_BFC_BFCOM_ASYNC (0x1) // (BFC) Asynchronous @@ -1357,15 +1357,15 @@ // ***************************************************************************** // REGISTER ADDRESS DEFINITION FOR AT91RM9200 // ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for MC peripheral ========== +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for MC peripheral ========== #define AT91C_MC_PUER (0xFFFFFF54) // (MC) MC Protection Unit Enable Register #define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register #define AT91C_MC_PUP (0xFFFFFF50) // (MC) MC Protection Unit Peripherals #define AT91C_MC_PUIA (0xFFFFFF10) // (MC) MC Protection Unit Area #define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register #define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for RTC peripheral ========== +// ========== Register definition for RTC peripheral ========== #define AT91C_RTC_IMR (0xFFFFFE28) // (RTC) Interrupt Mask Register #define AT91C_RTC_IER (0xFFFFFE20) // (RTC) Interrupt Enable Register #define AT91C_RTC_SR (0xFFFFFE18) // (RTC) Status Register @@ -1378,7 +1378,7 @@ #define AT91C_RTC_CALALR (0xFFFFFE14) // (RTC) Calendar Alarm Register #define AT91C_RTC_CALR (0xFFFFFE0C) // (RTC) Calendar Register #define AT91C_RTC_MR (0xFFFFFE04) // (RTC) Mode Register -// ========== Register definition for ST peripheral ========== +// ========== Register definition for ST peripheral ========== #define AT91C_ST_CRTR (0xFFFFFD24) // (ST) Current Real-time Register #define AT91C_ST_IMR (0xFFFFFD1C) // (ST) Interrupt Mask Register #define AT91C_ST_IER (0xFFFFFD14) // (ST) Interrupt Enable Register @@ -1389,7 +1389,7 @@ #define AT91C_ST_SR (0xFFFFFD10) // (ST) Status Register #define AT91C_ST_WDMR (0xFFFFFD08) // (ST) Watchdog Mode Register #define AT91C_ST_CR (0xFFFFFD00) // (ST) Control Register -// ========== Register definition for PMC peripheral ========== +// ========== Register definition for PMC peripheral ========== #define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register #define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register #define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register @@ -1402,12 +1402,12 @@ #define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register #define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register #define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for CKGR peripheral ========== +// ========== Register definition for CKGR peripheral ========== #define AT91C_CKGR_PLLBR (0xFFFFFC2C) // (CKGR) PLL B Register #define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register #define AT91C_CKGR_PLLAR (0xFFFFFC28) // (CKGR) PLL A Register #define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PIOD peripheral ========== +// ========== Register definition for PIOD peripheral ========== #define AT91C_PIOD_PDSR (0xFFFFFA3C) // (PIOD) Pin Data Status Register #define AT91C_PIOD_CODR (0xFFFFFA34) // (PIOD) Clear Output Data Register #define AT91C_PIOD_OWER (0xFFFFFAA0) // (PIOD) Output Write Enable Register @@ -1437,7 +1437,7 @@ #define AT91C_PIOD_BSR (0xFFFFFA74) // (PIOD) Select B Register #define AT91C_PIOD_IFDR (0xFFFFFA24) // (PIOD) Input Filter Disable Register #define AT91C_PIOD_IFSR (0xFFFFFA28) // (PIOD) Input Filter Status Register -// ========== Register definition for PIOC peripheral ========== +// ========== Register definition for PIOC peripheral ========== #define AT91C_PIOC_IFDR (0xFFFFF824) // (PIOC) Input Filter Disable Register #define AT91C_PIOC_ODR (0xFFFFF814) // (PIOC) Output Disable Registerr #define AT91C_PIOC_ABSR (0xFFFFF878) // (PIOC) AB Select Status Register @@ -1467,7 +1467,7 @@ #define AT91C_PIOC_PER (0xFFFFF800) // (PIOC) PIO Enable Register #define AT91C_PIOC_BSR (0xFFFFF874) // (PIOC) Select B Register #define AT91C_PIOC_PPUER (0xFFFFF864) // (PIOC) Pull-up Enable Register -// ========== Register definition for PIOB peripheral ========== +// ========== Register definition for PIOB peripheral ========== #define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register #define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pad Pull-up Status Register #define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register @@ -1497,7 +1497,7 @@ #define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register #define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register #define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for PIOA peripheral ========== +// ========== Register definition for PIOA peripheral ========== #define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register #define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register #define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register @@ -1527,7 +1527,7 @@ #define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register #define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register #define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for DBGU peripheral ========== +// ========== Register definition for DBGU peripheral ========== #define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register #define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register #define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register @@ -1540,7 +1540,7 @@ #define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register #define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register #define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== +// ========== Register definition for PDC_DBGU peripheral ========== #define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register #define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register #define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register @@ -1551,7 +1551,7 @@ #define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register #define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register #define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for AIC peripheral ========== +// ========== Register definition for AIC peripheral ========== #define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register #define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register #define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register @@ -1570,7 +1570,7 @@ #define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register #define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register #define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_SPI peripheral ========== +// ========== Register definition for PDC_SPI peripheral ========== #define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register #define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register #define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register @@ -1581,7 +1581,7 @@ #define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register #define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register #define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== +// ========== Register definition for SPI peripheral ========== #define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register #define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register #define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register @@ -1591,7 +1591,7 @@ #define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register #define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register #define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_SSC2 peripheral ========== +// ========== Register definition for PDC_SSC2 peripheral ========== #define AT91C_SSC2_PTCR (0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register #define AT91C_SSC2_TNPR (0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register #define AT91C_SSC2_RNPR (0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register @@ -1602,7 +1602,7 @@ #define AT91C_SSC2_RNCR (0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register #define AT91C_SSC2_TCR (0xFFFD810C) // (PDC_SSC2) Transmit Counter Register #define AT91C_SSC2_RCR (0xFFFD8104) // (PDC_SSC2) Receive Counter Register -// ========== Register definition for SSC2 peripheral ========== +// ========== Register definition for SSC2 peripheral ========== #define AT91C_SSC2_IMR (0xFFFD804C) // (SSC2) Interrupt Mask Register #define AT91C_SSC2_IER (0xFFFD8044) // (SSC2) Interrupt Enable Register #define AT91C_SSC2_RC1R (0xFFFD803C) // (SSC2) Receive Compare 1 Register @@ -1619,7 +1619,7 @@ #define AT91C_SSC2_RC0R (0xFFFD8038) // (SSC2) Receive Compare 0 Register #define AT91C_SSC2_RSHR (0xFFFD8030) // (SSC2) Receive Sync Holding Register #define AT91C_SSC2_RHR (0xFFFD8020) // (SSC2) Receive Holding Register -// ========== Register definition for PDC_SSC1 peripheral ========== +// ========== Register definition for PDC_SSC1 peripheral ========== #define AT91C_SSC1_PTCR (0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register #define AT91C_SSC1_TNPR (0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register #define AT91C_SSC1_RNPR (0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register @@ -1630,7 +1630,7 @@ #define AT91C_SSC1_RNCR (0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register #define AT91C_SSC1_TCR (0xFFFD410C) // (PDC_SSC1) Transmit Counter Register #define AT91C_SSC1_RCR (0xFFFD4104) // (PDC_SSC1) Receive Counter Register -// ========== Register definition for SSC1 peripheral ========== +// ========== Register definition for SSC1 peripheral ========== #define AT91C_SSC1_RFMR (0xFFFD4014) // (SSC1) Receive Frame Mode Register #define AT91C_SSC1_CMR (0xFFFD4004) // (SSC1) Clock Mode Register #define AT91C_SSC1_IDR (0xFFFD4048) // (SSC1) Interrupt Disable Register @@ -1647,7 +1647,7 @@ #define AT91C_SSC1_TSHR (0xFFFD4034) // (SSC1) Transmit Sync Holding Register #define AT91C_SSC1_THR (0xFFFD4024) // (SSC1) Transmit Holding Register #define AT91C_SSC1_TFMR (0xFFFD401C) // (SSC1) Transmit Frame Mode Register -// ========== Register definition for PDC_SSC0 peripheral ========== +// ========== Register definition for PDC_SSC0 peripheral ========== #define AT91C_SSC0_PTCR (0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register #define AT91C_SSC0_TNPR (0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register #define AT91C_SSC0_RNPR (0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register @@ -1658,7 +1658,7 @@ #define AT91C_SSC0_RNCR (0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register #define AT91C_SSC0_TCR (0xFFFD010C) // (PDC_SSC0) Transmit Counter Register #define AT91C_SSC0_RCR (0xFFFD0104) // (PDC_SSC0) Receive Counter Register -// ========== Register definition for SSC0 peripheral ========== +// ========== Register definition for SSC0 peripheral ========== #define AT91C_SSC0_IMR (0xFFFD004C) // (SSC0) Interrupt Mask Register #define AT91C_SSC0_IER (0xFFFD0044) // (SSC0) Interrupt Enable Register #define AT91C_SSC0_RC1R (0xFFFD003C) // (SSC0) Receive Compare 1 Register @@ -1675,7 +1675,7 @@ #define AT91C_SSC0_TCMR (0xFFFD0018) // (SSC0) Transmit Clock Mode Register #define AT91C_SSC0_RCMR (0xFFFD0010) // (SSC0) Receive Clock ModeRegister #define AT91C_SSC0_CR (0xFFFD0000) // (SSC0) Control Register -// ========== Register definition for PDC_US3 peripheral ========== +// ========== Register definition for PDC_US3 peripheral ========== #define AT91C_US3_PTSR (0xFFFCC124) // (PDC_US3) PDC Transfer Status Register #define AT91C_US3_TNCR (0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register #define AT91C_US3_RNCR (0xFFFCC114) // (PDC_US3) Receive Next Counter Register @@ -1686,7 +1686,7 @@ #define AT91C_US3_RNPR (0xFFFCC110) // (PDC_US3) Receive Next Pointer Register #define AT91C_US3_TPR (0xFFFCC108) // (PDC_US3) Transmit Pointer Register #define AT91C_US3_RPR (0xFFFCC100) // (PDC_US3) Receive Pointer Register -// ========== Register definition for US3 peripheral ========== +// ========== Register definition for US3 peripheral ========== #define AT91C_US3_IF (0xFFFCC04C) // (US3) IRDA_FILTER Register #define AT91C_US3_NER (0xFFFCC044) // (US3) Nb Errors Register #define AT91C_US3_RTOR (0xFFFCC024) // (US3) Receiver Time-out Register @@ -1702,7 +1702,7 @@ #define AT91C_US3_IMR (0xFFFCC010) // (US3) Interrupt Mask Register #define AT91C_US3_IER (0xFFFCC008) // (US3) Interrupt Enable Register #define AT91C_US3_CR (0xFFFCC000) // (US3) Control Register -// ========== Register definition for PDC_US2 peripheral ========== +// ========== Register definition for PDC_US2 peripheral ========== #define AT91C_US2_PTSR (0xFFFC8124) // (PDC_US2) PDC Transfer Status Register #define AT91C_US2_TNCR (0xFFFC811C) // (PDC_US2) Transmit Next Counter Register #define AT91C_US2_RNCR (0xFFFC8114) // (PDC_US2) Receive Next Counter Register @@ -1713,7 +1713,7 @@ #define AT91C_US2_RPR (0xFFFC8100) // (PDC_US2) Receive Pointer Register #define AT91C_US2_TPR (0xFFFC8108) // (PDC_US2) Transmit Pointer Register #define AT91C_US2_RNPR (0xFFFC8110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== +// ========== Register definition for US2 peripheral ========== #define AT91C_US2_XXR (0xFFFC8048) // (US2) XON_XOFF Register #define AT91C_US2_FIDI (0xFFFC8040) // (US2) FI_DI_Ratio Register #define AT91C_US2_TTGR (0xFFFC8028) // (US2) Transmitter Time-guard Register @@ -1729,7 +1729,7 @@ #define AT91C_US2_CSR (0xFFFC8014) // (US2) Channel Status Register #define AT91C_US2_IDR (0xFFFC800C) // (US2) Interrupt Disable Register #define AT91C_US2_MR (0xFFFC8004) // (US2) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== +// ========== Register definition for PDC_US1 peripheral ========== #define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register #define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register #define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register @@ -1740,7 +1740,7 @@ #define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register #define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register #define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== +// ========== Register definition for US1 peripheral ========== #define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register #define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register #define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register @@ -1756,7 +1756,7 @@ #define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register #define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register #define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== +// ========== Register definition for PDC_US0 peripheral ========== #define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register #define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register #define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register @@ -1767,7 +1767,7 @@ #define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register #define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register #define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== +// ========== Register definition for US0 peripheral ========== #define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register #define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register #define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register @@ -1783,7 +1783,7 @@ #define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register #define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register #define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== +// ========== Register definition for TWI peripheral ========== #define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register #define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register #define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register @@ -1795,7 +1795,7 @@ #define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register #define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register #define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PDC_MCI peripheral ========== +// ========== Register definition for PDC_MCI peripheral ========== #define AT91C_MCI_PTCR (0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register #define AT91C_MCI_TNPR (0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register #define AT91C_MCI_RNPR (0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register @@ -1806,7 +1806,7 @@ #define AT91C_MCI_RNCR (0xFFFB4114) // (PDC_MCI) Receive Next Counter Register #define AT91C_MCI_TCR (0xFFFB410C) // (PDC_MCI) Transmit Counter Register #define AT91C_MCI_RCR (0xFFFB4104) // (PDC_MCI) Receive Counter Register -// ========== Register definition for MCI peripheral ========== +// ========== Register definition for MCI peripheral ========== #define AT91C_MCI_IDR (0xFFFB4048) // (MCI) MCI Interrupt Disable Register #define AT91C_MCI_SR (0xFFFB4040) // (MCI) MCI Status Register #define AT91C_MCI_RDR (0xFFFB4030) // (MCI) MCI Receive Data Register @@ -1820,7 +1820,7 @@ #define AT91C_MCI_CMDR (0xFFFB4014) // (MCI) MCI Command Register #define AT91C_MCI_SDCR (0xFFFB400C) // (MCI) MCI SD Card Register #define AT91C_MCI_MR (0xFFFB4004) // (MCI) MCI Mode Register -// ========== Register definition for UDP peripheral ========== +// ========== Register definition for UDP peripheral ========== #define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register #define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register #define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register @@ -1832,7 +1832,7 @@ #define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register #define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register #define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -// ========== Register definition for TC5 peripheral ========== +// ========== Register definition for TC5 peripheral ========== #define AT91C_TC5_CMR (0xFFFA4084) // (TC5) Channel Mode Register #define AT91C_TC5_IDR (0xFFFA40A8) // (TC5) Interrupt Disable Register #define AT91C_TC5_SR (0xFFFA40A0) // (TC5) Status Register @@ -1843,7 +1843,7 @@ #define AT91C_TC5_IER (0xFFFA40A4) // (TC5) Interrupt Enable Register #define AT91C_TC5_RC (0xFFFA409C) // (TC5) Register C #define AT91C_TC5_RA (0xFFFA4094) // (TC5) Register A -// ========== Register definition for TC4 peripheral ========== +// ========== Register definition for TC4 peripheral ========== #define AT91C_TC4_IMR (0xFFFA406C) // (TC4) Interrupt Mask Register #define AT91C_TC4_IER (0xFFFA4064) // (TC4) Interrupt Enable Register #define AT91C_TC4_RC (0xFFFA405C) // (TC4) Register C @@ -1854,7 +1854,7 @@ #define AT91C_TC4_RB (0xFFFA4058) // (TC4) Register B #define AT91C_TC4_CV (0xFFFA4050) // (TC4) Counter Value #define AT91C_TC4_CCR (0xFFFA4040) // (TC4) Channel Control Register -// ========== Register definition for TC3 peripheral ========== +// ========== Register definition for TC3 peripheral ========== #define AT91C_TC3_IMR (0xFFFA402C) // (TC3) Interrupt Mask Register #define AT91C_TC3_CV (0xFFFA4010) // (TC3) Counter Value #define AT91C_TC3_CCR (0xFFFA4000) // (TC3) Channel Control Register @@ -1865,10 +1865,10 @@ #define AT91C_TC3_IDR (0xFFFA4028) // (TC3) Interrupt Disable Register #define AT91C_TC3_RB (0xFFFA4018) // (TC3) Register B #define AT91C_TC3_SR (0xFFFA4020) // (TC3) Status Register -// ========== Register definition for TCB1 peripheral ========== +// ========== Register definition for TCB1 peripheral ========== #define AT91C_TCB1_BCR (0xFFFA4140) // (TCB1) TC Block Control Register #define AT91C_TCB1_BMR (0xFFFA4144) // (TCB1) TC Block Mode Register -// ========== Register definition for TC2 peripheral ========== +// ========== Register definition for TC2 peripheral ========== #define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register #define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register #define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C @@ -1879,7 +1879,7 @@ #define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B #define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value #define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== +// ========== Register definition for TC1 peripheral ========== #define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register #define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register #define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C @@ -1890,7 +1890,7 @@ #define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B #define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value #define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== +// ========== Register definition for TC0 peripheral ========== #define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register #define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register #define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C @@ -1901,10 +1901,10 @@ #define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B #define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value #define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB0 peripheral ========== +// ========== Register definition for TCB0 peripheral ========== #define AT91C_TCB0_BMR (0xFFFA00C4) // (TCB0) TC Block Mode Register #define AT91C_TCB0_BCR (0xFFFA00C0) // (TCB0) TC Block Control Register -// ========== Register definition for UHP peripheral ========== +// ========== Register definition for UHP peripheral ========== #define AT91C_UHP_HcRhDescriptorA (0x00300048) // (UHP) Root Hub characteristics A #define AT91C_UHP_HcRhPortStatus (0x00300054) // (UHP) Root Hub Port Status Register #define AT91C_UHP_HcRhDescriptorB (0x0030004C) // (UHP) Root Hub characteristics B @@ -1927,7 +1927,7 @@ #define AT91C_UHP_HcPeriodicStart (0x00300040) // (UHP) Periodic Start #define AT91C_UHP_HcLSThreshold (0x00300044) // (UHP) LS Threshold #define AT91C_UHP_HcFmNumber (0x0030003C) // (UHP) Frame number -// ========== Register definition for EMAC peripheral ========== +// ========== Register definition for EMAC peripheral ========== #define AT91C_EMAC_RSR (0xFFFBC020) // (EMAC) Receive Status Register #define AT91C_EMAC_MAN (0xFFFBC034) // (EMAC) PHY Maintenance Register #define AT91C_EMAC_HSH (0xFFFBC090) // (EMAC) Hash Address High[63:32] @@ -1967,12 +1967,12 @@ #define AT91C_EMAC_SQEE (0xFFFBC07C) // (EMAC) SQE Test Error Register #define AT91C_EMAC_TSR (0xFFFBC014) // (EMAC) Transmit Status Register #define AT91C_EMAC_DRFC (0xFFFBC080) // (EMAC) Discarded RX Frame Register -// ========== Register definition for EBI peripheral ========== +// ========== Register definition for EBI peripheral ========== #define AT91C_EBI_CFGR (0xFFFFFF64) // (EBI) Configuration Register #define AT91C_EBI_CSA (0xFFFFFF60) // (EBI) Chip Select Assignment Register -// ========== Register definition for SMC2 peripheral ========== +// ========== Register definition for SMC2 peripheral ========== #define AT91C_SMC2_CSR (0xFFFFFF70) // (SMC2) SMC2 Chip Select Register -// ========== Register definition for SDRC peripheral ========== +// ========== Register definition for SDRC peripheral ========== #define AT91C_SDRC_IMR (0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register #define AT91C_SDRC_IER (0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register #define AT91C_SDRC_SRR (0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register @@ -1982,7 +1982,7 @@ #define AT91C_SDRC_LPR (0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register #define AT91C_SDRC_CR (0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register #define AT91C_SDRC_MR (0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register -// ========== Register definition for BFC peripheral ========== +// ========== Register definition for BFC peripheral ========== #define AT91C_BFC_MR (0xFFFFFFC0) // (BFC) BFC Mode Register // ***************************************************************************** @@ -2235,16 +2235,16 @@ #define AT91C_PD10_PCK3 (AT91C_PIO_PD10) // PMC Programmable Clock Output 3 #define AT91C_PD10_TPS1 (AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 #define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_ (AT91C_PIO_PD11) // +#define AT91C_PD11_ (AT91C_PIO_PD11) // #define AT91C_PD11_TPS2 (AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 #define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_ (AT91C_PIO_PD12) // +#define AT91C_PD12_ (AT91C_PIO_PD12) // #define AT91C_PD12_TPK0 (AT91C_PIO_PD12) // ETM Trace Packet 0 #define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_ (AT91C_PIO_PD13) // +#define AT91C_PD13_ (AT91C_PIO_PD13) // #define AT91C_PD13_TPK1 (AT91C_PIO_PD13) // ETM Trace Packet 1 #define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_ (AT91C_PIO_PD14) // +#define AT91C_PD14_ (AT91C_PIO_PD14) // #define AT91C_PD14_TPK2 (AT91C_PIO_PD14) // ETM Trace Packet 2 #define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15 #define AT91C_PD15_TD0 (AT91C_PIO_PD15) // SSC Transmit data @@ -2308,7 +2308,7 @@ // ***************************************************************************** #define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) #define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A #define AT91C_ID_PIOB ( 3) // Parallel IO Controller B #define AT91C_ID_PIOC ( 4) // Parallel IO Controller C #define AT91C_ID_PIOD ( 5) // Parallel IO Controller D diff --git a/target/linux/at91/image/dfboot/src/include/led.h b/target/linux/at91/image/dfboot/src/include/led.h index 9bebd9c3cb2..cd312dfb371 100644 --- a/target/linux/at91/image/dfboot/src/include/led.h +++ b/target/linux/at91/image/dfboot/src/include/led.h @@ -21,7 +21,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - + #ifndef __LED_H #define __LED_H diff --git a/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h b/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h index c322b32a498..58673d8b806 100644 --- a/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h +++ b/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h @@ -298,7 +298,7 @@ static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU In //*---------------------------------------------------------------------------- //* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked +//* \brief Test if DBGU Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller @@ -344,7 +344,7 @@ static inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Inte //*---------------------------------------------------------------------------- //* \fn AT91F_RTC_IsInterruptMasked -//* \brief Test if RTC Interrupt is Masked +//* \brief Test if RTC Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_RTC_IsInterruptMasked( AT91PS_RTC pRtc, // \arg pointer to a RTC controller @@ -565,7 +565,7 @@ static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Inte //*---------------------------------------------------------------------------- //* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked +//* \brief Test if SSC Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, // \arg pointer to a SSC controller @@ -666,7 +666,7 @@ static inline void AT91F_SPI_Disable ( //*---------------------------------------------------------------------------- static inline void AT91F_SPI_CfgMode ( AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register + int mode) // mode register { //* Write to the MR register pSPI->SPI_MR = mode; @@ -679,7 +679,7 @@ static inline void AT91F_SPI_CfgMode ( static inline void AT91F_SPI_CfgPCS ( AT91PS_SPI pSPI, // pointer to a SPI controller char PCS_Device) // PCS of the Device -{ +{ //* Write to the MR register pSPI->SPI_MR &= 0xFFF0FFFF; pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); @@ -785,7 +785,7 @@ static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Inte //*---------------------------------------------------------------------------- //* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked +//* \brief Test if SPI Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, // \arg pointer to a SPI controller @@ -831,7 +831,7 @@ static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interr //*---------------------------------------------------------------------------- //* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked +//* \brief Test if TC Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, // \arg pointer to a TC controller @@ -1107,7 +1107,7 @@ static inline void AT91F_PIO_ForceOutput( //*---------------------------------------------------------------------------- static inline void AT91F_PIO_Enable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled + unsigned int flag) // \arg pio to be enabled { pPio->PIO_PER = flag; } @@ -1118,7 +1118,7 @@ static inline void AT91F_PIO_Enable( //*---------------------------------------------------------------------------- static inline void AT91F_PIO_Disable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled + unsigned int flag) // \arg pio to be disabled { pPio->PIO_PDR = flag; } @@ -1232,9 +1232,9 @@ static inline int AT91F_PIO_IsInputFilterSet( //*---------------------------------------------------------------------------- //* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status +//* \brief Return PIO Output Data Status //*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status +static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status AT91PS_PIO pPio) // \arg pointer to a PIO controller { return pPio->PIO_ODSR; @@ -1284,7 +1284,7 @@ static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrup //*---------------------------------------------------------------------------- //* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked +//* \brief Test if PIO Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, // \arg pointer to a PIO controller @@ -1349,7 +1349,7 @@ static inline int AT91F_PIO_IsMultiDriverSet( //*---------------------------------------------------------------------------- //* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection +//* \brief PIO A Register Selection //*---------------------------------------------------------------------------- static inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, // \arg pointer to a PIO controller @@ -1360,11 +1360,11 @@ static inline void AT91F_PIO_A_RegisterSelection( //*---------------------------------------------------------------------------- //* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection +//* \brief PIO B Register Selection //*---------------------------------------------------------------------------- static inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection + unsigned int flag) // \arg pio B register selection { pPio->PIO_BSR = flag; } @@ -1437,7 +1437,7 @@ static inline int AT91F_PIO_IsOutputWriteSet( //* \fn AT91F_PIO_GetCfgPullup //* \brief Return PIO Configuration Pullup //*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup +static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup AT91PS_PIO pPio) // \arg pointer to a PIO controller { return pPio->PIO_PPUSR; @@ -1445,7 +1445,7 @@ static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration //*---------------------------------------------------------------------------- //* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set +//* \brief Test if PIO Output Data Status is Set //*---------------------------------------------------------------------------- static inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller @@ -1521,7 +1521,7 @@ static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Inte //*---------------------------------------------------------------------------- //* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked +//* \brief Test if TWI Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, // \arg pointer to a TWI controller @@ -2329,7 +2329,7 @@ static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Inte //*---------------------------------------------------------------------------- //* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked +//* \brief Test if UDP Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, // \arg pointer to a UDP controller @@ -2390,7 +2390,7 @@ static inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interr //*---------------------------------------------------------------------------- //* \fn AT91F_ST_IsInterruptMasked -//* \brief Test if ST Interrupt is Masked +//* \brief Test if ST Interrupt is Masked //*---------------------------------------------------------------------------- static inline int AT91F_ST_IsInterruptMasked( AT91PS_ST pSt, // \arg pointer to a ST controller diff --git a/target/linux/at91/image/dfboot/src/init.c b/target/linux/at91/image/dfboot/src/init.c index 4088973f7d9..23a485b867a 100644 --- a/target/linux/at91/image/dfboot/src/init.c +++ b/target/linux/at91/image/dfboot/src/init.c @@ -21,7 +21,7 @@ //* \fn AT91F_DataAbort //* \brief This function reports an Abort //*---------------------------------------------------------------------------- -static void AT91F_SpuriousHandler() +static void AT91F_SpuriousHandler() { puts("ISI"); while (1); @@ -32,7 +32,7 @@ static void AT91F_SpuriousHandler() //* \fn AT91F_DataAbort //* \brief This function reports an Abort //*---------------------------------------------------------------------------- -static void AT91F_DataAbort() +static void AT91F_DataAbort() { puts("IDA"); while (1); @@ -52,7 +52,7 @@ static void AT91F_FetchAbort() //* \fn AT91F_UndefHandler //* \brief This function reports that no handler have been set for current IT //*---------------------------------------------------------------------------- -static void AT91F_UndefHandler() +static void AT91F_UndefHandler() { puts("IUD"); while (1); @@ -68,47 +68,47 @@ static void AT91F_UndefHandler() static void AT91F_InitSdram() { int *pRegister; - + //* Configure PIOC as peripheral (D16/D31) - + AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, // PIO controller base address 0xFFFF0030, 0 ); - + //*Init SDRAM pRegister = (int *)0xFFFFFF98; - *pRegister = 0x2188c155; + *pRegister = 0x2188c155; pRegister = (int *)0xFFFFFF90; - *pRegister = 0x2; + *pRegister = 0x2; pRegister = (int *)0x20000000; - *pRegister = 0; + *pRegister = 0; pRegister = (int *)0xFFFFFF90; - *pRegister = 0x4; + *pRegister = 0x4; pRegister = (int *)0x20000000; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; - *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; pRegister = (int *)0xFFFFFF90; - *pRegister = 0x3; + *pRegister = 0x3; pRegister = (int *)0x20000080; - *pRegister = 0; + *pRegister = 0; pRegister = (int *)0xFFFFFF94; - *pRegister = 0x2e0; + *pRegister = 0x2e0; pRegister = (int *)0x20000000; - *pRegister = 0; + *pRegister = 0; pRegister = (int *)0xFFFFFF90; - *pRegister = 0x00; + *pRegister = 0x00; pRegister = (int *)0x20000000; - *pRegister = 0; + *pRegister = 0; } @@ -127,7 +127,7 @@ static void AT91F_InitMemories() //* CS0 cs for flash pEbi = (int *)0xFFFFFF70; *pEbi = 0x00003284; - + AT91F_InitSdram(); } @@ -150,7 +150,7 @@ void AT91F_LowLevelInit(void) AT91F_SpuriousHandler, // AIC spurious handler 0); // Protect mode - // Perform 8 End Of Interrupt Command to make sýre AIC will not Lock out nIRQ + // Perform 8 End Of Interrupt Command to make sýre AIC will not Lock out nIRQ for(i=0; i<8; i++) AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC); diff --git a/target/linux/at91/image/dfboot/src/led.c b/target/linux/at91/image/dfboot/src/led.c index 40d49113c78..ac348571fe8 100644 --- a/target/linux/at91/image/dfboot/src/led.c +++ b/target/linux/at91/image/dfboot/src/led.c @@ -85,7 +85,7 @@ void LED_blink(unsigned int led) for(j= 0; j < 200000; j++); LED_set(0); for(j= 0; j < 200000; j++); - } + } } diff --git a/target/linux/at91/image/dfboot/src/main.c b/target/linux/at91/image/dfboot/src/main.c index c0705dec608..52bcaa97f0d 100644 --- a/target/linux/at91/image/dfboot/src/main.c +++ b/target/linux/at91/image/dfboot/src/main.c @@ -8,7 +8,7 @@ * intellectual property rights of others. *---------------------------------------------------------------------------- * File Name : main.c - * Object : + * Object : * Creation : HIi 10/10/2003 * Modif : HIi 15/06/2004 : add crc32 to verify the download * from dataflash @@ -107,7 +107,7 @@ AT91S_CtlTempo ctlTempo; //*-------------------------------------------------------------------------------------- //* Function Name : GetTickCount() -//* Object : Return the number of systimer tick +//* Object : Return the number of systimer tick //* Input Parameters : //* Output Parameters : //*-------------------------------------------------------------------------------------- @@ -141,10 +141,10 @@ static void XmodemProtocol(AT91S_PipeStatus status, void *pVoid) { AT91PS_SBuffer pSBuffer = (AT91PS_SBuffer) xmodemPipe.pBuffer->pChild; AT91PS_USART pUsart = svcXmodem.pUsart; - + if (pSBuffer->szRdBuffer == 0) { /* Start a tempo to wait the Xmodem protocol complete */ - svcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart); + svcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart); } } #endif @@ -161,7 +161,7 @@ void AT91F_ST_HANDLER(void) #ifdef XMODEM unsigned int error; #endif - + if (AT91C_BASE_ST->ST_SR & 0x01) { StTick++; ctlTempo.CtlTempoTick(&ctlTempo); @@ -177,9 +177,9 @@ void AT91F_ST_HANDLER(void) AT91F_US_EnableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_RXRDY); } - - else if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | - AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | + + else if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | + AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | AT91C_US_RXBUFF)) { if ( !(svcXmodem.eot) ) svcXmodem.Handler(&svcXmodem, csr); @@ -190,9 +190,9 @@ void AT91F_ST_HANDLER(void) //*----------------------------------------------------------------------------- //* Function Name : AT91F_DisplayMenu() -//* Object : -//* Input Parameters : -//* Return value : +//* Object : +//* Input Parameters : +//* Return value : //*----------------------------------------------------------------------------- static int AT91F_DisplayMenu(void) { @@ -204,30 +204,30 @@ static int AT91F_DisplayMenu(void) puts(menu_dataflash[i]); } return mci_present; -} +} //*----------------------------------------------------------------------------- //* Function Name : AsciiToHex() //* Object : ascii to hexa conversion -//* Input Parameters : -//* Return value : +//* Input Parameters : +//* Return value : //*----------------------------------------------------------------------------- static unsigned int AsciiToHex(char *s, unsigned int *val) { int n; *val=0; - + if(s[0] == '0' && ((s[1] == 'x') || (s[1] == 'X'))) s+=2; - n = 0; + n = 0; while((n < 8) && (s[n] !=0)) { *val <<= 4; if ( (s[n] >= '0') && (s[n] <='9')) *val += (s[n] - '0'); - else + else if ((s[n] >= 'a') && (s[n] <='f')) *val += (s[n] - 0x57); else @@ -238,7 +238,7 @@ static unsigned int AsciiToHex(char *s, unsigned int *val) n++; } - return 1; + return 1; } @@ -246,8 +246,8 @@ static unsigned int AsciiToHex(char *s, unsigned int *val) //*----------------------------------------------------------------------------- //* Function Name : AT91F_MemoryDisplay() //* Object : Display the content of the dataflash -//* Input Parameters : -//* Return value : +//* Input Parameters : +//* Return value : //*----------------------------------------------------------------------------- static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length) { @@ -265,7 +265,7 @@ static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length) // uip = (unsigned int *)linebuf; // usp = (unsigned short *)linebuf; ucp = (unsigned char *)linebuf; - + printf("%08x:", addr); linebytes = (nbytes > DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; if((addr & 0xF0000000) == 0x20000000) { @@ -277,7 +277,7 @@ static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length) } for (i=0; iCKGR_PLLAR = AT91C_PLLA_VALUE; while (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA)); - + /* - Switch Master Clock from PLLB to PLLA/3 */ tmp = pPmc->PMC_MCKR; /* See Atmel Errata #27 and #28 */ @@ -336,7 +336,7 @@ static unsigned int AT91F_SetPLL(void) while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); } - return 1; + return 1; } @@ -387,7 +387,7 @@ static int AT91F_LoadBoot(void) volatile unsigned int AddressToDownload = AT91C_BOOT_ADDR; #if 0 - /* Read vector 6 to extract size to load */ + /* Read vector 6 to extract size to load */ if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, 32, (char *)AddressToDownload) != AT91C_DATAFLASH_OK) { @@ -397,7 +397,7 @@ static int AT91F_LoadBoot(void) /* calculate the size to download */ SizeToDownload = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); #endif - + // printf("\nLoad UBOOT from dataflash[%x] to SDRAM[%x]\n", // AT91C_BOOT_DATAFLASH_ADDR, AT91C_BOOT_ADDR); if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, SizeToDownload + 8, @@ -417,7 +417,7 @@ static int AT91F_LoadBoot(void) /* Restore the value of Vector 6 */ *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = *(int *)(AddressToDownload + SizeToDownload + 4); - + if (crc1 != crc2) { printf("DF CRC bad %x != %x\n",crc1,crc2); return IMAGE_CRC_ERROR; @@ -543,11 +543,11 @@ int main(void) #endif AT91S_SvcTempo svcBootTempo; // Link to a AT91S_Tempo object unsigned int ix; - volatile unsigned int AddressToDownload, SizeToDownload; + volatile unsigned int AddressToDownload, SizeToDownload; unsigned int DeviceAddress = 0; char command = 0; #ifdef XMODEM - volatile int i = 0; + volatile int i = 0; unsigned int crc1 = 0, crc2 = 0; volatile int device; int NbPage; @@ -568,7 +568,7 @@ int main(void) /* Tempo Initialisation */ pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC)); ctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC)); - + // Attach the tempo to a tempo controler ctlTempo.CtlTempoCreate(&ctlTempo, &svcBootTempo); // LED_init(); @@ -607,11 +607,11 @@ int main(void) AddressToDownload = AT91C_DOWNLOAD_BASE_ADDRESS; SizeToDownload = AT91C_DOWNLOAD_MAX_SIZE; DeviceAddress = 0; - + /* try to detect Dataflash */ if (!Nb_Device) - Nb_Device = AT91F_DataflashInit(); - + Nb_Device = AT91F_DataflashInit(); + mci_present = AT91F_DisplayMenu(); #ifdef PRODTEST @@ -631,10 +631,10 @@ int main(void) command = message[0]; for(ix = 1; (message[ix] == ' ') && (ix < 12); ix++); // Skip some whitespace - + if(!AsciiToHex(&message[ix], &DeviceAddress) ) DeviceAddress = 0; // Illegal DeviceAddress - + switch(command) { #ifdef XMODEM @@ -661,7 +661,7 @@ int main(void) device = 0; break; - + case CFG_DATAFLASH_LOGIC_ADDR_CS3: if (dataflash_info[1].id == 0){ printf("No DF"); @@ -670,7 +670,7 @@ int main(void) } device = 1; break; - + default: command = 0; break; @@ -691,7 +691,7 @@ int main(void) #ifdef MEMDISP case '6': - do + do { AT91F_MemoryDisplay(DeviceAddress, 256); AT91F_ReadLine (NULL, message); @@ -736,9 +736,9 @@ int main(void) #ifdef XMODEM for(i = 0; i <= AT91C_DOWNLOAD_MAX_SIZE; i++) *(unsigned char *)(AddressToDownload + i) = 0; - + xmodemPipe.Read(&xmodemPipe, (char *)AddressToDownload, - SizeToDownload, XmodemProtocol, 0); + SizeToDownload, XmodemProtocol, 0); while(XmodemComplete !=1); SizeToDownload = (unsigned int)((svcXmodem.pData) - (unsigned int)AddressToDownload); @@ -753,21 +753,21 @@ int main(void) i = (SizeToDownload / 512)+1 + (NbPage << 13) + (dataflash_info[device].Device.pages_size << 17); //+4 to add crc32 SizeToDownload = 512 * (i &0xFF); - } + } else { - /* Save the contents of vector 6 ==> will be restored + /* Save the contents of vector 6 ==> will be restored * at boot time (AT91F_StartBoot) */ *(int *)(AddressToDownload + SizeToDownload + 4) = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); /* Modify Vector 6 to contain the size of the * file to copy (Dataflash -> SDRAM)*/ - i = SizeToDownload; - } + i = SizeToDownload; + } *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = i; // printf("\nModification of Arm Vector 6 :%x\n", i); - + // printf("\nWrite %d bytes in DataFlash [0x%x]\n",SizeToDownload, DeviceAddress); crc1 = 0; pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc1); @@ -784,13 +784,13 @@ int main(void) /* clear the buffer before read */ for(i=0; i <= SizeToDownload; i++) *(unsigned char *)(AddressToDownload + i) = 0; - + /* Read dataflash to check the validity of the data */ read_dataflash (DeviceAddress, (SizeToDownload + 4), (char *)(AddressToDownload)); - printf("VFY: "); + printf("VFY: "); crc2 = 0; - + pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc2); crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + @@ -801,7 +801,7 @@ int main(void) printf("ERR"); else printf("OK"); - + command = 0; XmodemComplete = 0; AT91F_WaitKeyPressed(); diff --git a/target/linux/at91/image/dfboot/src/main.h b/target/linux/at91/image/dfboot/src/main.h index a8cd325ca96..e8d17264b2c 100644 --- a/target/linux/at91/image/dfboot/src/main.h +++ b/target/linux/at91/image/dfboot/src/main.h @@ -12,7 +12,7 @@ //* //* 1.0 27/03/03 HIi : Creation //* 1.01 03/05/04 HIi : AT9C_VERSION incremented to 1.01 -//* 1.02 15/06/04 HIi : AT9C_VERSION incremented to 1.02 ==> +//* 1.02 15/06/04 HIi : AT9C_VERSION incremented to 1.02 ==> //* Add crc32 to verify dataflash download //* 1.03 18/04/05 MLC : AT91C_VERSION incremented to 1.03g //* Repeat boot on CRC Failure diff --git a/target/linux/at91/image/dfboot/src/mci_device.c b/target/linux/at91/image/dfboot/src/mci_device.c index cce74a3ae84..02cffc78850 100644 --- a/target/linux/at91/image/dfboot/src/mci_device.c +++ b/target/linux/at91/image/dfboot/src/mci_device.c @@ -94,7 +94,7 @@ int AT91F_MCI_SDCard_SendAppCommand ( status = AT91C_BASE_MCI->MCI_SR; //tick++; } - while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); + while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); // if an error occurs if (((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR) != 0 ) @@ -134,16 +134,16 @@ void AT91F_MCI_Device_Handler( { AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE; AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS; - + pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; - } // End of if AT91C_MCI_TXBUFF - + } // End of if AT91C_MCI_TXBUFF + // If End of Rx Buffer Full interrupt occurred if ( status & AT91C_MCI_RXBUFF ) - { + { AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF; AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS; - + pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; } // End of if AT91C_MCI_RXBUFF @@ -175,30 +175,30 @@ int AT91F_MCI_ReadBlock( //////////////////////////////////////////////////////////////////////////////////////////// if(pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) return AT91C_READ_ERROR; - + if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) return AT91C_READ_ERROR; - + if ( (src + sizeToRead) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) return AT91C_READ_ERROR; // If source does not fit a begin of a block if ( (src % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) return AT91C_READ_ERROR; - + // Test if the MMC supports Partial Read Block // ALWAYS SUPPORTED IN SD Memory Card - if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) + if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) && (pMCI_Device->pMCI_DeviceFeatures->Read_Partial == 0x00) ) return AT91C_READ_ERROR; - + if( sizeToRead > pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) return AT91C_READ_ERROR; //////////////////////////////////////////////////////////////////////////////////////////// - + // Init Mode Register AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); - + if (sizeToRead %4) sizeToRead = (sizeToRead /4)+1; else @@ -219,7 +219,7 @@ int AT91F_MCI_ReadBlock( // (PDC) Receiver Transfer Enable AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN; - + return AT91C_READ_OK; } @@ -238,29 +238,29 @@ int AT91F_MCI_WriteBlock( //////////////////////////////////////////////////////////////////////////////////////////// if( pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) return AT91C_WRITE_ERROR; - + if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) return AT91C_WRITE_ERROR; - + if ( (dest + sizeToWrite) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) return AT91C_WRITE_ERROR; // If source does not fit a begin of a block if ( (dest % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) return AT91C_WRITE_ERROR; - - // Test if the MMC supports Partial Write Block - if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) + + // Test if the MMC supports Partial Write Block + if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) && (pMCI_Device->pMCI_DeviceFeatures->Write_Partial == 0x00) ) return AT91C_WRITE_ERROR; - + if( sizeToWrite > pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length ) return AT91C_WRITE_ERROR; //////////////////////////////////////////////////////////////////////////////////////////// - + // Init Mode Register AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); - + if (sizeToWrite %4) sizeToWrite = (sizeToWrite /4)+1; else @@ -279,10 +279,10 @@ int AT91F_MCI_WriteBlock( // Enable AT91C_MCI_TXBUFE Interrupt AT91C_BASE_MCI->MCI_IER = AT91C_MCI_TXBUFE; - + // Enables TX for PDC transfert requests AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTEN; - + return AT91C_WRITE_OK; } #endif @@ -295,7 +295,7 @@ int AT91F_MCI_WriteBlock( int AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address) { int status; - + //* Check if the MMC card chosen is already the selected one status = AT91F_MCI_GetStatus(pMCI_Device,relative_card_address); @@ -328,17 +328,17 @@ int AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative //*---------------------------------------------------------------------------- int AT91F_MCI_GetCSD (AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address , unsigned int * response) { - + if(AT91F_MCI_SendCommand(pMCI_Device, AT91C_SEND_CSD_CMD, (relative_card_address << 16)) != AT91C_CMD_SEND_OK) return AT91C_CMD_SEND_ERROR; - + response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; - + return AT91C_CMD_SEND_OK; } @@ -359,7 +359,7 @@ int AT91F_MCI_SetBlocklength(AT91PS_MciDevice pMCI_Device,unsigned int length) int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device) { unsigned int response =0x0; - + while(1) { response = AT91F_MCI_SendCommand(pMCI_Device, @@ -367,11 +367,11 @@ int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device) AT91C_MMC_HOST_VOLTAGE_RANGE); if (response != AT91C_CMD_SEND_OK) return AT91C_INIT_ERROR; - + response = AT91C_BASE_MCI->MCI_RSPR[0]; - + if ( (response & AT91C_CARD_POWER_UP_BUSY) == AT91C_CARD_POWER_UP_BUSY) - return(response); + return(response); } } #endif @@ -384,7 +384,7 @@ int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device) int AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) { int Nb_Cards_Found=-1; - + while(1) { if(AT91F_MCI_SendCommand(pMCI_Device, @@ -392,18 +392,18 @@ int AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *respons AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) return Nb_Cards_Found; else - { + { Nb_Cards_Found = 0; //* Assignation of the relative address to the MMC CARD pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Relative_Card_Address = Nb_Cards_Found + AT91C_FIRST_RCA; //* Set the insert flag pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Card_Inserted = AT91C_MMC_CARD_INSERTED; - + if (AT91F_MCI_SendCommand(pMCI_Device, AT91C_MMC_SET_RELATIVE_ADDR_CMD, (Nb_Cards_Found + AT91C_FIRST_RCA) << 16) != AT91C_CMD_SEND_OK) return AT91C_CMD_SEND_ERROR; - + //* If no error during assignation address ==> Increment Nb_cards_Found Nb_Cards_Found++ ; } @@ -438,7 +438,7 @@ int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device) if (AT91F_MCI_GetCSD(pMCI_Device, pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address, tab_response) != AT91C_CMD_SEND_OK) - pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0; + pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0; else { pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); @@ -446,10 +446,10 @@ int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device) pMCI_Device->pMCI_DeviceFeatures[i].Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v22_SECT_SIZE_S) & AT91C_CSD_v22_SECT_SIZE_M ); pMCI_Device->pMCI_DeviceFeatures[i].Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; pMCI_Device->pMCI_DeviceFeatures[i].Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; - + // None in MMC specification version 2.2 pMCI_Device->pMCI_DeviceFeatures[i].Erase_Block_Enable = 0; - + pMCI_Device->pMCI_DeviceFeatures[i].Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; pMCI_Device->pMCI_DeviceFeatures[i].Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; @@ -463,10 +463,10 @@ int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device) pMCI_Device->pMCI_DeviceFeatures[i].Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length * blocknr; //// End of Compute Memory Capacity - - } // end of else + + } // end of else } // end of for - + return AT91C_INIT_OK; } // end of if @@ -484,7 +484,7 @@ int AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device) // The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000. pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = 0x0; - + while( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY ) { response = AT91F_MCI_SDCard_SendAppCommand(pMCI_Device, @@ -492,10 +492,10 @@ int AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device) AT91C_MMC_HOST_VOLTAGE_RANGE); if (response != AT91C_CMD_SEND_OK) return AT91C_INIT_ERROR; - + response = AT91C_BASE_MCI->MCI_RSPR[0]; } - + return(AT91C_BASE_MCI->MCI_RSPR[0]); } @@ -509,12 +509,12 @@ int AT91F_MCI_SDCard_GetCID (AT91PS_MciDevice pMCI_Device, unsigned int *respons AT91C_ALL_SEND_CID_CMD, AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) return AT91C_CMD_SEND_ERROR; - + response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; - + return AT91C_CMD_SEND_OK; } @@ -594,7 +594,7 @@ int AT91F_MCI_SDCard_Init (AT91PS_MciDevice pMCI_Device) printf("SD-Card: %d Bytes\n\r", pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity); if( AT91F_MCI_SDCard_SetBusWidth(pMCI_Device) == AT91C_CMD_SEND_OK ) - { + { if (AT91F_MCI_SetBlocklength(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) == AT91C_CMD_SEND_OK) return AT91C_INIT_OK; } @@ -621,10 +621,10 @@ void AT91F_CfgDevice(void) MCI_Device_Features.Erase_Block_Enable = 0; MCI_Device_Features.Sector_Size = 0; MCI_Device_Features.Memory_Capacity = 0; - + MCI_Device_Desc.state = AT91C_MCI_IDLE; MCI_Device_Desc.SDCard_bus_width = AT91C_MCI_SCDBUS; - + // Init AT91S_DataFlash Global Structure, by default AT45DB choosen !!! MCI_Device.pMCI_DeviceDesc = &MCI_Device_Desc; MCI_Device.pMCI_DeviceFeatures = &MCI_Device_Features; @@ -645,9 +645,9 @@ int AT91F_MCI_Init(void) // Set up PIO SDC_TYPE to switch on MMC/SDCard and not DataFlash Card AT91F_PIO_CfgOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); AT91F_PIO_SetOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); - + // Init MCI for MMC and SDCard interface - AT91F_MCI_CfgPIO(); + AT91F_MCI_CfgPIO(); AT91F_MCI_CfgPMC(); AT91F_PDC_Open(AT91C_BASE_PDC_MCI); @@ -657,7 +657,7 @@ int AT91F_MCI_Init(void) // Init MCI Device Structures AT91F_CfgDevice(); - // Configure MCI interrupt + // Configure MCI interrupt AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_MCI, AT91C_AIC_PRIOR_HIGHEST, @@ -674,7 +674,7 @@ int AT91F_MCI_Init(void) AT91C_MCI_DTOR_1MEGA_CYCLES, AT91C_MCI_MR_PDCMODE, // 15MHz for MCK = 60MHz (CLKDIV = 1) AT91C_MCI_SDCARD_4BITS_SLOTA); - + if(AT91F_MCI_SDCard_Init(&MCI_Device) != AT91C_INIT_OK) return FALSE; else @@ -689,13 +689,13 @@ int AT91F_MCI_Init(void) void AT91F_MCIDeviceWaitReady(unsigned int timeout) { volatile int status; - + do { status = AT91C_BASE_MCI->MCI_SR; timeout--; } - while( !(status & AT91C_MCI_NOTBUSY) && (timeout>0) ); + while( !(status & AT91C_MCI_NOTBUSY) && (timeout>0) ); } unsigned int swab32(unsigned int data) @@ -725,7 +725,7 @@ int AT91F_MCI_ReadBlockSwab( //* Read Block 1 for(i=0;i; default-state = "on"; }; - + internet { function = LED_FUNCTION_WAN_ONLINE; color = ; gpios = <&gpio 11 GPIO_ACTIVE_LOW>; }; - + wan { function = LED_FUNCTION_WAN; color = ; @@ -53,7 +53,7 @@ color = ; gpios = <&gpio 19 GPIO_ACTIVE_LOW>; }; - + lan2 { function = LED_FUNCTION_LAN; function-enumerator = <2>; @@ -108,7 +108,7 @@ reg = <0xff0000 0x010000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; @@ -141,7 +141,7 @@ }; &gpio { - + }; &builtin_switch { diff --git a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts index 6229eefb1f0..b2f224e750d 100644 --- a/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts +++ b/target/linux/ath79/dts/ar9344_mikrotik_routerboard-951g-2hnd.dts @@ -17,7 +17,7 @@ gpio-export,output = <1>; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; }; - + buzzer { gpio-export,name = "buzzer"; gpio-export,output = <1>; diff --git a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts index 60de383008c..8c2b2582a34 100644 --- a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts +++ b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts @@ -59,7 +59,7 @@ gpios = <&gpio 22 GPIO_ACTIVE_LOW>; }; }; - + watchdog { compatible = "linux,wdt-gpio"; diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi index 648c3a9c8e8..0c30e2d13fa 100644 --- a/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi +++ b/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi @@ -159,7 +159,7 @@ reg = <1>; spi-max-frequency = <25000000>; status = "disabled"; - + nand_partitions: partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/ath79/dts/qca9557_fortinet_fap-221-c.dts b/target/linux/ath79/dts/qca9557_fortinet_fap-221-c.dts index 69b6af26099..83bda877a46 100644 --- a/target/linux/ath79/dts/qca9557_fortinet_fap-221-c.dts +++ b/target/linux/ath79/dts/qca9557_fortinet_fap-221-c.dts @@ -89,7 +89,7 @@ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; - + virtual_flash { compatible = "mtd-concat"; @@ -197,7 +197,7 @@ &wmac { status = "okay"; - + nvmem-cells = <&calibration_wmac>, <&macaddr_uboot_3ff80 1>; nvmem-cell-names = "calibration", "mac-address"; }; diff --git a/target/linux/ath79/dts/qca9558_aruba_ap-115.dts b/target/linux/ath79/dts/qca9558_aruba_ap-115.dts index 8f6cb71724f..5a7fa593cec 100644 --- a/target/linux/ath79/dts/qca9558_aruba_ap-115.dts +++ b/target/linux/ath79/dts/qca9558_aruba_ap-115.dts @@ -41,7 +41,7 @@ color = ; gpios = <&gpio 4 GPIO_ACTIVE_LOW>; }; - + led_power_red: power-red { function = LED_FUNCTION_POWER; color = ; @@ -113,7 +113,7 @@ * * We can not support this with OpenWrt, as this * would require us to influence the pinmux based on the CS. - * + * * We force-select Bank 1. Remember to blame Aruba for that. */ cs0_pin5: spi-cs0-pin5 { diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts index 79b5e4e6ea7..a81b4d96a0d 100644 --- a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts +++ b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts @@ -55,7 +55,7 @@ watchdog { compatible = "linux,wdt-gpio"; - + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; hw_algo = "toggle"; hw_margin_ms = <1200>; diff --git a/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts index 64ad7f06d3e..a1551c071f5 100644 --- a/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts +++ b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts @@ -171,7 +171,7 @@ ð0 { status = "okay"; - + pll-data = <0x03000101 0x00000101 0x00001919>; phy-mode = "sgmii"; diff --git a/target/linux/ath79/image/lzma-loader/src/LzmaDecode.c b/target/linux/ath79/image/lzma-loader/src/LzmaDecode.c index cb8345377ea..3470e55d6ec 100644 --- a/target/linux/ath79/image/lzma-loader/src/LzmaDecode.c +++ b/target/linux/ath79/image/lzma-loader/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -46,7 +46,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #endif #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -57,9 +57,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -82,7 +82,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -168,7 +168,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int lc = vs->Properties.lc; #ifdef _LZMA_OUT_READ - + UInt32 Range = vs->Range; UInt32 Code = vs->Code; #ifdef _LZMA_IN_CB @@ -210,7 +210,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); UInt32 i; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; + p[i] = kBitModelTotal >> 1; rep0 = rep1 = rep2 = rep3 = 1; state = 0; globalPos = 0; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + #ifdef _LZMA_IN_CB RC_INIT; #else @@ -275,7 +275,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -287,9 +287,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -338,7 +338,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -365,14 +365,14 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 pos; #endif UpdateBit0(prob); - + #ifdef _LZMA_OUT_READ if (distanceLimit == 0) #else if (nowPos == 0) #endif return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; #ifdef _LZMA_OUT_READ pos = dictionaryPos - rep0; @@ -408,7 +408,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -469,7 +469,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) @@ -524,7 +524,7 @@ int LzmaDecode(CLzmaDecoderState *vs, len += kMatchMinLen; #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) + if (rep0 > distanceLimit) #else if (rep0 > nowPos) #endif diff --git a/target/linux/ath79/image/lzma-loader/src/LzmaDecode.h b/target/linux/ath79/image/lzma-loader/src/LzmaDecode.h index 2870eeb9c9c..bd75525aedb 100644 --- a/target/linux/ath79/image/lzma-loader/src/LzmaDecode.h +++ b/target/linux/ath79/image/lzma-loader/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -31,7 +31,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ diff --git a/target/linux/ath79/image/lzma-loader/src/LzmaTypes.h b/target/linux/ath79/image/lzma-loader/src/LzmaTypes.h index 9c27290757c..83f96f46437 100644 --- a/target/linux/ath79/image/lzma-loader/src/LzmaTypes.h +++ b/target/linux/ath79/image/lzma-loader/src/LzmaTypes.h @@ -1,5 +1,5 @@ -/* -LzmaTypes.h +/* +LzmaTypes.h Types for LZMA Decoder @@ -13,12 +13,12 @@ This file is part of LZMA SDK 4.40 (2006-05-01) #ifndef _7ZIP_BYTE_DEFINED #define _7ZIP_BYTE_DEFINED typedef unsigned char Byte; -#endif +#endif #ifndef _7ZIP_UINT16_DEFINED #define _7ZIP_UINT16_DEFINED typedef unsigned short UInt16; -#endif +#endif #ifndef _7ZIP_UINT32_DEFINED #define _7ZIP_UINT32_DEFINED @@ -27,7 +27,7 @@ typedef unsigned long UInt32; #else typedef unsigned int UInt32; #endif -#endif +#endif /* #define _LZMA_NO_SYSTEM_SIZE_T */ /* You can use it, if you don't want */ diff --git a/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.c index 951700bddfb..900c7e7b49f 100644 --- a/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.c +++ b/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder - + LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -89,7 +89,7 @@ void RangeDecoderInit(CRangeDecoder *rd, rd->Code = (rd->Code << 8) | ReadByte; } -#define RC_INIT_VAR UInt32 range = rd->Range; UInt32 code = rd->Code; +#define RC_INIT_VAR UInt32 range = rd->Range; UInt32 code = rd->Code; #define RC_FLUSH_VAR rd->Range = range; rd->Code = code; #define RC_NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | ReadByte; } @@ -157,7 +157,7 @@ int RangeDecoderBitDecode(CProb *prob, CRangeDecoder *rd) { A1; range -= bound; code -= bound; *prob -= (*prob) >> kNumMoveBits; mi = (mi + mi) + 1; } \ RC_NORMALIZE -#define RC_GET_BIT(prob, mi) RC_GET_BIT2(prob, mi, ; , ;) +#define RC_GET_BIT(prob, mi) RC_GET_BIT2(prob, mi, ; , ;) int RangeDecoderBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd) { @@ -207,7 +207,7 @@ int RangeDecoderReverseBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder } Byte LzmaLiteralDecode(CProb *probs, CRangeDecoder *rd) -{ +{ int symbol = 1; #ifdef _LZMA_LOC_OPT RC_INIT_VAR @@ -229,7 +229,7 @@ Byte LzmaLiteralDecode(CProb *probs, CRangeDecoder *rd) } Byte LzmaLiteralDecodeMatch(CProb *probs, CRangeDecoder *rd, Byte matchByte) -{ +{ int symbol = 1; #ifdef _LZMA_LOC_OPT RC_INIT_VAR @@ -284,7 +284,7 @@ Byte LzmaLiteralDecodeMatch(CProb *probs, CRangeDecoder *rd, Byte matchByte) #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) int LzmaLenDecode(CProb *p, CRangeDecoder *rd, int posState) { @@ -294,7 +294,7 @@ int LzmaLenDecode(CProb *p, CRangeDecoder *rd, int posState) if(RangeDecoderBitDecode(p + LenChoice2, rd) == 0) return kLenNumLowSymbols + RangeDecoderBitTreeDecode(p + LenMid + (posState << kLenNumMidBits), kLenNumMidBits, rd); - return kLenNumLowSymbols + kLenNumMidSymbols + + return kLenNumLowSymbols + kLenNumMidSymbols + RangeDecoderBitTreeDecode(p + LenHigh, kLenNumHighBits, rd); } @@ -377,8 +377,8 @@ int LzmaDecoderInit( vs->RemainLen = 0; dictionary[dictionarySize - 1] = 0; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - RangeDecoderInit(&vs->RangeDecoder, + p[i] = kBitModelTotal >> 1; + RangeDecoderInit(&vs->RangeDecoder, #ifdef _LZMA_IN_CB inCallback #else @@ -388,7 +388,7 @@ int LzmaDecoderInit( return LZMA_RESULT_OK; } -int LzmaDecode(unsigned char *buffer, +int LzmaDecode(unsigned char *buffer, unsigned char *outStream, UInt32 outSize, UInt32 *outSizeProcessed) { @@ -458,8 +458,8 @@ int LzmaDecode( if (bufferSize < numProbs * sizeof(CProb)) return LZMA_RESULT_NOT_ENOUGH_MEM; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - RangeDecoderInit(&rd, + p[i] = kBitModelTotal >> 1; + RangeDecoderInit(&rd, #ifdef _LZMA_IN_CB inCallback #else @@ -472,7 +472,7 @@ int LzmaDecode( while(nowPos < outSize) { int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -486,9 +486,9 @@ int LzmaDecode( return LZMA_RESULT_DATA_ERROR; if (RangeDecoderBitDecode(p + IsMatch + (state << kNumPosBitsMax) + posState, &rd) == 0) { - CProb *probs = p + Literal + (LZMA_LIT_SIZE * + CProb *probs = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -521,7 +521,7 @@ int LzmaDecode( dictionaryPos = 0; #endif } - else + else { previousIsMatch = 1; if (RangeDecoderBitDecode(p + IsRep + state, &rd) == 1) @@ -534,7 +534,7 @@ int LzmaDecode( UInt32 pos; #endif if ( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -562,7 +562,7 @@ int LzmaDecode( UInt32 distance; if(RangeDecoderBitDecode(p + IsRepG1 + state, &rd) == 0) distance = rep1; - else + else { if(RangeDecoderBitDecode(p + IsRepG2 + state, &rd) == 0) distance = rep2; @@ -588,7 +588,7 @@ int LzmaDecode( state = state < 7 ? 7 : 10; len = LzmaLenDecode(p + LenCoder, &rd, posState); posSlot = RangeDecoderBitTreeDecode(p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits), kNumPosSlotBits, &rd); if (posSlot >= kStartPosModelIndex) { @@ -601,7 +601,7 @@ int LzmaDecode( } else { - rep0 += RangeDecoderDecodeDirectBits(&rd, + rep0 += RangeDecoderDecodeDirectBits(&rd, numDirectBits - kNumAlignBits) << kNumAlignBits; rep0 += RangeDecoderReverseBitTreeDecode(p + Align, kNumAlignBits, &rd); } @@ -616,7 +616,7 @@ int LzmaDecode( len = -1; break; } - if (rep0 > nowPos + if (rep0 > nowPos #ifdef _LZMA_OUT_READ + globalPos #endif diff --git a/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.h index f58944e3c3f..ff8e96bd262 100644 --- a/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.h +++ b/target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -29,7 +29,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ @@ -63,10 +63,10 @@ typedef struct _ILzmaInCallback #define LZMA_BASE_SIZE 1846 #define LZMA_LIT_SIZE 768 -/* +/* bufferSize = (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp)))* sizeof(CProb) bufferSize += 100 in case of _LZMA_OUT_READ -by default CProb is unsigned short, +by default CProb is unsigned short, but if specify _LZMA_PROB_32, CProb will be UInt32(unsigned int) */ @@ -84,7 +84,7 @@ int LzmaDecoderInit( #endif int LzmaDecode( - unsigned char *buffer, + unsigned char *buffer, #ifndef _LZMA_OUT_READ UInt32 bufferSize, int lc, int lp, int pb, diff --git a/target/linux/bcm47xx/image/lzma-loader/src/decompress.c b/target/linux/bcm47xx/image/lzma-loader/src/decompress.c index 05681b152d4..292d6dfe560 100644 --- a/target/linux/bcm47xx/image/lzma-loader/src/decompress.c +++ b/target/linux/bcm47xx/image/lzma-loader/src/decompress.c @@ -106,10 +106,10 @@ static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize) val = *(unsigned int *)data; data += 4; } - + *bufferSize = 1; *buffer = ((unsigned char *)&val) + (offset++ & 3); - + return LZMA_RESULT_OK; } @@ -117,12 +117,12 @@ static __inline__ unsigned char get_byte(void) { unsigned char *buffer; UInt32 fake; - + return read_byte(0, &buffer, &fake), *buffer; } /* should be the first function */ -void entry(unsigned long icache_size, unsigned long icache_lsize, +void entry(unsigned long icache_size, unsigned long icache_lsize, unsigned long dcache_size, unsigned long dcache_lsize, unsigned long fw_arg0, unsigned long fw_arg1, unsigned long fw_arg2, unsigned long fw_arg3) @@ -145,7 +145,7 @@ void entry(unsigned long icache_size, unsigned long icache_lsize, if (((struct trx_header *)data)->magic == EDIMAX_PS_HEADER_MAGIC) data += EDIMAX_PS_HEADER_LEN; /* compressed kernel is in the partition 0 or 1 */ - if (((struct trx_header *)data)->offsets[1] > 65536) + if (((struct trx_header *)data)->offsets[1] > 65536) data += ((struct trx_header *)data)->offsets[0]; else data += ((struct trx_header *)data)->offsets[1]; @@ -168,7 +168,7 @@ void entry(unsigned long icache_size, unsigned long icache_lsize, ((unsigned int)get_byte() << 24); /* skip rest of the header (upper half of uncompressed size) */ - for (i = 0; i < 4; i++) + for (i = 0; i < 4; i++) get_byte(); /* decompress kernel */ diff --git a/target/linux/bmips/dts/bcm63168-smartrg-sr505n.dts b/target/linux/bmips/dts/bcm63168-smartrg-sr505n.dts index 571289b4c61..4193102f49b 100644 --- a/target/linux/bmips/dts/bcm63168-smartrg-sr505n.dts +++ b/target/linux/bmips/dts/bcm63168-smartrg-sr505n.dts @@ -16,7 +16,7 @@ keys { compatible = "gpio-keys-polled"; poll-interval = <100>; - + reset { label = "reset"; gpios = <&gpio 32 GPIO_ACTIVE_LOW>; @@ -180,7 +180,7 @@ &pinctrl { pinctrl_leds: leds { function = "led"; - pins = "gpio1", "gpio8", + pins = "gpio1", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio14", "gpio15", diff --git a/target/linux/bmips/dts/bcm6318-tp-link-td-w8968-v3.dts b/target/linux/bmips/dts/bcm6318-tp-link-td-w8968-v3.dts index 59b209daed4..d7e733c1398 100644 --- a/target/linux/bmips/dts/bcm6318-tp-link-td-w8968-v3.dts +++ b/target/linux/bmips/dts/bcm6318-tp-link-td-w8968-v3.dts @@ -12,11 +12,11 @@ led-running = &led_power_green; led-upgrade = &led_power_green; }; - + keys { compatible = "gpio-keys-polled"; poll-interval = <100>; - + wlan { label = "wlan"; gpios = <&gpio 9 GPIO_ACTIVE_LOW>; @@ -38,7 +38,7 @@ debounce-interval = <60>; }; }; - + bcm43217-sprom { compatible = "brcm,bcma-sprom"; @@ -182,7 +182,7 @@ function = LED_FUNCTION_USB; color = ; }; - + led@16 { reg = <16>; active-low; diff --git a/target/linux/bmips/dts/bcm6328-dlink-dsl-2750b-b1.dts b/target/linux/bmips/dts/bcm6328-dlink-dsl-2750b-b1.dts index 970182629d6..3a99f8bd3c5 100644 --- a/target/linux/bmips/dts/bcm6328-dlink-dsl-2750b-b1.dts +++ b/target/linux/bmips/dts/bcm6328-dlink-dsl-2750b-b1.dts @@ -63,7 +63,7 @@ &leds { status = "okay"; - + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds>; @@ -213,7 +213,7 @@ nvmem-cells = <&macaddr_cfe_6a0 1>, <&cal_data_1000>; nvmem-cell-names = "mac-address", "calibration"; - + #gpio-cells = <2>; gpio-controller; }; diff --git a/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6348-enet.c b/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6348-enet.c index ca184e575b2..85105f591e4 100644 --- a/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6348-enet.c +++ b/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6348-enet.c @@ -1610,7 +1610,7 @@ static int bcm6348_emac_probe(struct platform_device *pdev) GFP_KERNEL); if (IS_ERR_OR_NULL(emac->reset)) return PTR_ERR(emac->reset); - + } for (i = 0; i < emac->num_resets; i++) { emac->reset[i] = devm_reset_control_get_by_index(dev, i); diff --git a/target/linux/bmips/image/lzma-loader/src/LzmaDecode.c b/target/linux/bmips/image/lzma-loader/src/LzmaDecode.c index cb8345377ea..3470e55d6ec 100644 --- a/target/linux/bmips/image/lzma-loader/src/LzmaDecode.c +++ b/target/linux/bmips/image/lzma-loader/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -46,7 +46,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #endif #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -57,9 +57,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -82,7 +82,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -168,7 +168,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int lc = vs->Properties.lc; #ifdef _LZMA_OUT_READ - + UInt32 Range = vs->Range; UInt32 Code = vs->Code; #ifdef _LZMA_IN_CB @@ -210,7 +210,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); UInt32 i; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; + p[i] = kBitModelTotal >> 1; rep0 = rep1 = rep2 = rep3 = 1; state = 0; globalPos = 0; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + #ifdef _LZMA_IN_CB RC_INIT; #else @@ -275,7 +275,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -287,9 +287,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -338,7 +338,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -365,14 +365,14 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 pos; #endif UpdateBit0(prob); - + #ifdef _LZMA_OUT_READ if (distanceLimit == 0) #else if (nowPos == 0) #endif return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; #ifdef _LZMA_OUT_READ pos = dictionaryPos - rep0; @@ -408,7 +408,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -469,7 +469,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) @@ -524,7 +524,7 @@ int LzmaDecode(CLzmaDecoderState *vs, len += kMatchMinLen; #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) + if (rep0 > distanceLimit) #else if (rep0 > nowPos) #endif diff --git a/target/linux/bmips/image/lzma-loader/src/LzmaDecode.h b/target/linux/bmips/image/lzma-loader/src/LzmaDecode.h index 2870eeb9c9c..bd75525aedb 100644 --- a/target/linux/bmips/image/lzma-loader/src/LzmaDecode.h +++ b/target/linux/bmips/image/lzma-loader/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -31,7 +31,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ diff --git a/target/linux/bmips/image/lzma-loader/src/LzmaTypes.h b/target/linux/bmips/image/lzma-loader/src/LzmaTypes.h index 9c27290757c..83f96f46437 100644 --- a/target/linux/bmips/image/lzma-loader/src/LzmaTypes.h +++ b/target/linux/bmips/image/lzma-loader/src/LzmaTypes.h @@ -1,5 +1,5 @@ -/* -LzmaTypes.h +/* +LzmaTypes.h Types for LZMA Decoder @@ -13,12 +13,12 @@ This file is part of LZMA SDK 4.40 (2006-05-01) #ifndef _7ZIP_BYTE_DEFINED #define _7ZIP_BYTE_DEFINED typedef unsigned char Byte; -#endif +#endif #ifndef _7ZIP_UINT16_DEFINED #define _7ZIP_UINT16_DEFINED typedef unsigned short UInt16; -#endif +#endif #ifndef _7ZIP_UINT32_DEFINED #define _7ZIP_UINT32_DEFINED @@ -27,7 +27,7 @@ typedef unsigned long UInt32; #else typedef unsigned int UInt32; #endif -#endif +#endif /* #define _LZMA_NO_SYSTEM_SIZE_T */ /* You can use it, if you don't want */ diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_jimage.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_jimage.c index 1770dd47ce1..1244bbdb06e 100644 --- a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_jimage.c +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_jimage.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Paweł Dembicki + * Copyright (C) 2018 Paweł Dembicki * * Based on: mtdsplit_uimage.c * Copyright (C) 2013 Gabor Juhos diff --git a/target/linux/generic/files/drivers/net/phy/adm6996.c b/target/linux/generic/files/drivers/net/phy/adm6996.c index dfee13c0bf4..d917427419a 100644 --- a/target/linux/generic/files/drivers/net/phy/adm6996.c +++ b/target/linux/generic/files/drivers/net/phy/adm6996.c @@ -84,7 +84,7 @@ struct adm6996_priv { u16 vlan_id[ADM_NUM_VLANS]; u8 vlan_table[ADM_NUM_VLANS]; /* bitmap, 1 = port is member */ u8 vlan_tagged[ADM_NUM_VLANS]; /* bitmap, 1 = tagged member */ - + struct mutex mib_lock; char buf[2048]; @@ -805,12 +805,12 @@ adm6996_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *link) { struct adm6996_priv *priv = to_adm(dev); - + u16 reg = 0; - + if (port >= ADM_NUM_PORTS) return -EINVAL; - + switch (port) { case 0: reg = r16(priv, ADM_PS0); @@ -838,7 +838,7 @@ adm6996_get_port_link(struct switch_dev *dev, int port, default: return -EINVAL; } - + link->link = reg & ADM_PS_LS; if (!link->link) return 0; @@ -1003,9 +1003,9 @@ static int adm6996_switch_init(struct adm6996_priv *priv, const char *alias, str w16(priv, ADM_VID_CHECK, test); test ^= r16(priv, ADM_VID_CHECK); if (test & (1 << 12)) { - /* - * Bit 12 of this register is read-only. - * This is the FC model. + /* + * Bit 12 of this register is read-only. + * This is the FC model. */ priv->model = ADM6996FC; } else { diff --git a/target/linux/generic/files/drivers/net/phy/psb6970.c b/target/linux/generic/files/drivers/net/phy/psb6970.c index 2587b999138..2af32df1727 100644 --- a/target/linux/generic/files/drivers/net/phy/psb6970.c +++ b/target/linux/generic/files/drivers/net/phy/psb6970.c @@ -7,7 +7,7 @@ * under the terms of the GNU General Public License v2 as published by the * Free Software Foundation. * - * The switch programming done in this driver follows the + * The switch programming done in this driver follows the * "Ethernet Traffic Separation using VLAN" Application Note as * published by Lantiq. */ diff --git a/target/linux/generic/files/drivers/net/phy/rtl8306.c b/target/linux/generic/files/drivers/net/phy/rtl8306.c index 31bc7589c4b..9bd1735f67b 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8306.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8306.c @@ -587,7 +587,7 @@ rtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, st return rtl_attr_get_int(dev, attr, val); } -static int +static int rtl_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *link) { if (port >= RTL8306_NUM_PORTS) diff --git a/target/linux/generic/image/lzma-loader/src/LzmaDecode.c b/target/linux/generic/image/lzma-loader/src/LzmaDecode.c index c90a0d3ef47..8c863efe5c2 100644 --- a/target/linux/generic/image/lzma-loader/src/LzmaDecode.c +++ b/target/linux/generic/image/lzma-loader/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.22 Copyright (c) 1999-2005 Igor Pavlov (2005-06-10) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -50,7 +50,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #endif #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -61,9 +61,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -86,7 +86,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -174,7 +174,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int lc = vs->Properties.lc; #ifdef _LZMA_OUT_READ - + UInt32 Range = vs->Range; UInt32 Code = vs->Code; #ifdef _LZMA_IN_CB @@ -216,7 +216,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); UInt32 i; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; + p[i] = kBitModelTotal >> 1; rep0 = rep1 = rep2 = rep3 = 1; state = 0; globalPos = 0; @@ -267,7 +267,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + #ifdef _LZMA_IN_CB RC_INIT; #else @@ -281,7 +281,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -293,9 +293,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -344,7 +344,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -371,14 +371,14 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 pos; #endif UpdateBit0(prob); - + #ifdef _LZMA_OUT_READ if (distanceLimit == 0) #else if (nowPos == 0) #endif return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; #ifdef _LZMA_OUT_READ pos = dictionaryPos - rep0; @@ -414,7 +414,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -475,7 +475,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) @@ -530,7 +530,7 @@ int LzmaDecode(CLzmaDecoderState *vs, len += kMatchMinLen; #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) + if (rep0 > distanceLimit) #else if (rep0 > nowPos) #endif diff --git a/target/linux/generic/image/lzma-loader/src/LzmaDecode.h b/target/linux/generic/image/lzma-loader/src/LzmaDecode.h index 213062af12c..abc02d7edf3 100644 --- a/target/linux/generic/image/lzma-loader/src/LzmaDecode.h +++ b/target/linux/generic/image/lzma-loader/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -29,7 +29,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ diff --git a/target/linux/generic/image/lzma-loader/src/decompress.c b/target/linux/generic/image/lzma-loader/src/decompress.c index 45ac509cdc4..45d77c79416 100644 --- a/target/linux/generic/image/lzma-loader/src/decompress.c +++ b/target/linux/generic/image/lzma-loader/src/decompress.c @@ -92,11 +92,11 @@ static __inline__ unsigned char get_byte(void) { unsigned char *buffer; UInt32 fake; - + return read_byte(0, &buffer, &fake), *buffer; } -/* This puts lzma workspace 128k below RAM end. +/* This puts lzma workspace 128k below RAM end. * That should be enough for both lzma and stack */ static char *buffer = (char *)(RAMSTART + RAMSIZE - 0x00020000); @@ -104,7 +104,7 @@ extern char lzma_start[]; extern char lzma_end[]; /* should be the first function */ -void entry(unsigned long icache_size, unsigned long icache_lsize, +void entry(unsigned long icache_size, unsigned long icache_lsize, unsigned long dcache_size, unsigned long dcache_lsize) { unsigned int i; /* temp value */ @@ -141,7 +141,7 @@ void entry(unsigned long icache_size, unsigned long icache_lsize, ((unsigned int)get_byte() << 24); /* skip rest of the header (upper half of uncompressed size) */ - for (i = 0; i < 4; i++) + for (i = 0; i < 4; i++) get_byte(); /* decompress kernel */ diff --git a/target/linux/generic/image/lzma-loader/src/print.c b/target/linux/generic/image/lzma-loader/src/print.c index 950687beff1..66c177856f2 100644 --- a/target/linux/generic/image/lzma-loader/src/print.c +++ b/target/linux/generic/image/lzma-loader/src/print.c @@ -27,9 +27,9 @@ static const char theFatalMsg[] = "fatal error in lp_Print!"; * A low level printf() function. */ void -lp_Print(void (*output)(void *, char *, int), +lp_Print(void (*output)(void *, char *, int), void * arg, - char *fmt, + char *fmt, va_list ap) { @@ -40,7 +40,7 @@ lp_Print(void (*output)(void *, char *, int), (*output)(arg, s, l); \ } \ } - + char buf[LP_MAX_BUF]; char c; @@ -57,7 +57,7 @@ lp_Print(void (*output)(void *, char *, int), int length; for(;;) { - { + { /* scan for the next '%' */ char *fmtStart = fmt; while ( (*fmt != '\0') && (*fmt != '%')) { @@ -73,7 +73,7 @@ lp_Print(void (*output)(void *, char *, int), /* we found a '%' */ fmt ++; - + /* check for long */ if (*fmt == 'l') { longFlag = 1; @@ -119,9 +119,9 @@ lp_Print(void (*output)(void *, char *, int), negFlag = 0; switch (*fmt) { case 'b': - if (longFlag) { - num = va_arg(ap, long int); - } else { + if (longFlag) { + num = va_arg(ap, long int); + } else { num = va_arg(ap, int); } length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); @@ -130,10 +130,10 @@ lp_Print(void (*output)(void *, char *, int), case 'd': case 'D': - if (longFlag) { + if (longFlag) { num = va_arg(ap, long int); - } else { - num = va_arg(ap, int); + } else { + num = va_arg(ap, int); } if (num < 0) { num = - num; @@ -145,10 +145,10 @@ lp_Print(void (*output)(void *, char *, int), case 'o': case 'O': - if (longFlag) { + if (longFlag) { num = va_arg(ap, long int); - } else { - num = va_arg(ap, int); + } else { + num = va_arg(ap, int); } length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); OUTPUT(arg, buf, length); @@ -156,30 +156,30 @@ lp_Print(void (*output)(void *, char *, int), case 'u': case 'U': - if (longFlag) { + if (longFlag) { num = va_arg(ap, long int); - } else { - num = va_arg(ap, int); + } else { + num = va_arg(ap, int); } length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); OUTPUT(arg, buf, length); break; - + case 'x': - if (longFlag) { + if (longFlag) { num = va_arg(ap, long int); - } else { - num = va_arg(ap, int); + } else { + num = va_arg(ap, int); } length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); OUTPUT(arg, buf, length); break; case 'X': - if (longFlag) { + if (longFlag) { num = va_arg(ap, long int); - } else { - num = va_arg(ap, int); + } else { + num = va_arg(ap, int); } length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); OUTPUT(arg, buf, length); @@ -219,7 +219,7 @@ int PrintChar(char * buf, char c, int length, int ladjust) { int i; - + if (length < 1) length = 1; if (ladjust) { *buf = c; @@ -251,7 +251,7 @@ PrintString(char * buf, char* s, int length, int ladjust) } int -PrintNum(char * buf, unsigned long u, int base, int negFlag, +PrintNum(char * buf, unsigned long u, int base, int negFlag, int length, int ladjust, char padc, int upcase) { /* algorithm : @@ -298,7 +298,7 @@ PrintNum(char * buf, unsigned long u, int base, int negFlag, } else { for (i = actualLength; i< length; i++) buf[i] = padc; } - + /* prepare to reverse the string */ { diff --git a/target/linux/generic/image/lzma-loader/src/print.h b/target/linux/generic/image/lzma-loader/src/print.h index b051463909b..9fea609676b 100644 --- a/target/linux/generic/image/lzma-loader/src/print.h +++ b/target/linux/generic/image/lzma-loader/src/print.h @@ -28,9 +28,9 @@ * output function cannot assume the buffer is null-terminated after * l number of chars. */ -void lp_Print(void (*output)(void *, char *, int), +void lp_Print(void (*output)(void *, char *, int), void * arg, - char *fmt, + char *fmt, va_list ap); #endif diff --git a/target/linux/generic/image/lzma-loader/src/printf.c b/target/linux/generic/image/lzma-loader/src/printf.c index 49bd50d7c78..e3d5332ce70 100644 --- a/target/linux/generic/image/lzma-loader/src/printf.c +++ b/target/linux/generic/image/lzma-loader/src/printf.c @@ -19,7 +19,7 @@ static void myoutput(void *arg, char *s, int l) // special termination call if ((l==1) && (s[0] == '\0')) return; - + for (i=0; i< l; i++) { Uart16550Put(s[i]); if (s[i] == '\n') Uart16550Put('\r'); diff --git a/target/linux/generic/image/lzma-loader/src/uart16550.c b/target/linux/generic/image/lzma-loader/src/uart16550.c index 7df57276001..125670f3ef3 100644 --- a/target/linux/generic/image/lzma-loader/src/uart16550.c +++ b/target/linux/generic/image/lzma-loader/src/uart16550.c @@ -52,12 +52,12 @@ void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop) UART16550_WRITE(OFS_INTR_ENABLE, 0); /* set up buad rate */ - { + { uint32 divisor; - + /* set DIAB bit */ UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - + /* set divisor */ divisor = MAX_BAUD / baud; UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lbr20.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lbr20.dts index fade33299a4..2ce7af9875a 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lbr20.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lbr20.dts @@ -113,7 +113,7 @@ reg = <0x1957000 0x100>; qcom,wifi_noc_memtype_m0_m2 = ; }; - + }; }; @@ -320,7 +320,7 @@ label = "boarddata1"; reg = <0x00d00000 0x00080000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts index bb66c6c8083..ad8078cd744 100644 --- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts @@ -40,7 +40,7 @@ compatible = "gpio-keys"; pinctrl-0 = <&button_pins>; pinctrl-names = "default"; - + reset { label = "reset"; gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; @@ -157,7 +157,7 @@ pins = "gpio6", "gpio7"; }; }; - + usb_pwr_en_pins: usb_pwr_en_pins { mux { pins = "gpio22"; diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts index 9219e34a925..f26d026be85 100644 --- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-ap3935.dts @@ -57,7 +57,7 @@ gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; }; - led_power_orange: power_orange { + led_power_orange: power_orange { function = LED_FUNCTION_POWER; color = ; gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; @@ -304,7 +304,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - + ubi@0 { label = "ubi"; reg = <0x0000000 0x20000000>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts index 478934c2c19..5c5f533dbc2 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts @@ -96,7 +96,7 @@ }; phy13: ethernet-phy@13 { reg = <0x13>; - + leds { #address-cells = <1>; #size-cells = <0>; diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts index 0fb7347d736..60e14ba9c45 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts @@ -32,23 +32,23 @@ nvmem-cell-names = "mac-address"; brcm,sprom = "brcm/bcm43222-sprom.bin"; - brcm,sprom-fixups = <2 0x04d2>, + brcm,sprom-fixups = <2 0x04d2>, <65 0x1308>, <68 0x0402>, <70 0x1cc6>, <71 0x3c49>, <72 0x1132>, <87 0x0315>, <88 0x0315>, <96 0x2048>, <97 0xfeed>, <98 0x153e>, <99 0xfb1f>, <100 0x3e54>, - <101 0x3848>, <102 0xfea0>, + <101 0x3848>, <102 0xfea0>, <103 0x145c>, <104 0xfaf0>, <105 0xfe6e>, <106 0x110c>, <107 0xfb7e>, <108 0xff00>, - <109 0x13c4>, <110 0xfb30>, - <111 0x0000>, <112 0x204c>, - <113 0xfeb8>, <114 0x1508>, + <109 0x13c4>, <110 0xfb30>, + <111 0x0000>, <112 0x204c>, + <113 0xfeb8>, <114 0x1508>, <115 0xfacb>, <116 0x3e48>, - <117 0x3848>, <118 0xfeb2>, - <119 0x156e>, <120 0xfabf>, + <117 0x3848>, <118 0xfeb2>, + <119 0x156e>, <120 0xfabf>, <121 0xfe57>, <122 0x1139>, <123 0xfb6d>, <124 0xff38>, <125 0x13ee>, <126 0xfb6d>, diff --git a/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c index cb8345377ea..3470e55d6ec 100644 --- a/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c +++ b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -46,7 +46,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #endif #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -57,9 +57,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -82,7 +82,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -168,7 +168,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int lc = vs->Properties.lc; #ifdef _LZMA_OUT_READ - + UInt32 Range = vs->Range; UInt32 Code = vs->Code; #ifdef _LZMA_IN_CB @@ -210,7 +210,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); UInt32 i; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; + p[i] = kBitModelTotal >> 1; rep0 = rep1 = rep2 = rep3 = 1; state = 0; globalPos = 0; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + #ifdef _LZMA_IN_CB RC_INIT; #else @@ -275,7 +275,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -287,9 +287,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -338,7 +338,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -365,14 +365,14 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 pos; #endif UpdateBit0(prob); - + #ifdef _LZMA_OUT_READ if (distanceLimit == 0) #else if (nowPos == 0) #endif return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; #ifdef _LZMA_OUT_READ pos = dictionaryPos - rep0; @@ -408,7 +408,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -469,7 +469,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) @@ -524,7 +524,7 @@ int LzmaDecode(CLzmaDecoderState *vs, len += kMatchMinLen; #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) + if (rep0 > distanceLimit) #else if (rep0 > nowPos) #endif diff --git a/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h index 2870eeb9c9c..bd75525aedb 100644 --- a/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h +++ b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -31,7 +31,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ diff --git a/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h b/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h index 9c27290757c..83f96f46437 100644 --- a/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h +++ b/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h @@ -1,5 +1,5 @@ -/* -LzmaTypes.h +/* +LzmaTypes.h Types for LZMA Decoder @@ -13,12 +13,12 @@ This file is part of LZMA SDK 4.40 (2006-05-01) #ifndef _7ZIP_BYTE_DEFINED #define _7ZIP_BYTE_DEFINED typedef unsigned char Byte; -#endif +#endif #ifndef _7ZIP_UINT16_DEFINED #define _7ZIP_UINT16_DEFINED typedef unsigned short UInt16; -#endif +#endif #ifndef _7ZIP_UINT32_DEFINED #define _7ZIP_UINT32_DEFINED @@ -27,7 +27,7 @@ typedef unsigned long UInt32; #else typedef unsigned int UInt32; #endif -#endif +#endif /* #define _LZMA_NO_SYSTEM_SIZE_T */ /* You can use it, if you don't want */ diff --git a/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts index 2ced26e2957..19c004e8fcc 100644 --- a/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts +++ b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts @@ -148,7 +148,7 @@ label = "Factory"; reg = <0x50000 0x10000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; diff --git a/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts b/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts index 6ab48cc5e1d..be2bfcfb368 100644 --- a/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts +++ b/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts @@ -215,7 +215,7 @@ #nvmem-cell-cells = <1>; }; }; - + }; partition@69c0000 { diff --git a/target/linux/mediatek/dts/mt7981b-netis-nx31.dts b/target/linux/mediatek/dts/mt7981b-netis-nx31.dts index 82f666df794..f5e89902338 100644 --- a/target/linux/mediatek/dts/mt7981b-netis-nx31.dts +++ b/target/linux/mediatek/dts/mt7981b-netis-nx31.dts @@ -195,7 +195,7 @@ reg = <0x380000 0x200000>; read-only; }; - + partition@580000 { label = "ubi"; reg = <0x580000 0x7a80000>; diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts index 2b079f5bcac..c313e08288d 100644 --- a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; diff --git a/target/linux/mediatek/dts/mt7986a-acer-w6-common.dtsi b/target/linux/mediatek/dts/mt7986a-acer-w6-common.dtsi index 03913f04e10..8b35ce25178 100644 --- a/target/linux/mediatek/dts/mt7986a-acer-w6-common.dtsi +++ b/target/linux/mediatek/dts/mt7986a-acer-w6-common.dtsi @@ -250,7 +250,7 @@ slot0: pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <0x03>; + #address-cells = <0x03>; #size-cells = <0x02>; }; }; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts index b32a3b56130..e5b47905e59 100644 --- a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts @@ -45,7 +45,7 @@ nvmem-layout { compatible = "fixed-layout"; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <1>; eeprom_factory: eeprom@0 { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_hal.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_hal.c index b9373492cb5..b24812425cc 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_hal.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_hal.c @@ -262,7 +262,7 @@ void rtk_hal_dump_table(void) printk(" %2d", l2_data.fid); printk(" %4d", l2_data.cvid); printk(" %02x%02x%02x%02x%02x%02x\n", l2_data.mac.octet[0], - l2_data.mac.octet[1], l2_data.mac.octet[2], l2_data.mac.octet[3], + l2_data.mac.octet[1], l2_data.mac.octet[2], l2_data.mac.octet[3], l2_data.mac.octet[4], l2_data.mac.octet[5]); address ++; } @@ -523,7 +523,7 @@ void rtk_hal_qos_get_table2type(struct ra_switch_ioctl_data *data) void rtk_hal_qos_set_port2table(struct ra_switch_ioctl_data *data) { rtk_api_ret_t ret; - + ret = rtk_qos_portPriSelIndex_set(data->port, data->qos_table_idx); if (ret != 0) printk("rtk_qos_portPriSelIndex_set failed\n"); @@ -533,7 +533,7 @@ void rtk_hal_qos_get_port2table(struct ra_switch_ioctl_data *data) { rtk_api_ret_t ret; rtk_qos_priDecTbl_t Index; - + ret = rtk_qos_portPriSelIndex_get(data->port, &Index); if (ret != 0) printk("rtk_qos_portPriSelIndex_set failed\n"); @@ -642,7 +642,7 @@ void rtk_hal_enable_igmpsnoop(struct ra_switch_ioctl_data *data) { rtk_api_ret_t ret; rtk_portmask_t pmask; - + ret = rtk_igmp_init(); if (data->on_off == 1) { @@ -800,7 +800,7 @@ void rtk_hal_vlan_tag(struct ra_switch_ioctl_data *data) RTK_PORTMASK_PORT_SET(vlan.untag, data->port); else RTK_PORTMASK_PORT_CLEAR(vlan.untag, data->port); - + ret = rtk_vlan_set(data->vid, &vlan); if (ret != RT_ERR_OK) printk("rtk_vlan_set failed\n"); diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s.c index 6a55631d525..2988c8af56d 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s.c @@ -28,15 +28,15 @@ #define RTL8367C_SW_CPU_PORT 6 //RTL8367C_PHY_PORT_NUM + ext0 + ext1 -#define RTL8367C_NUM_PORTS 7 -#define RTL8367C_NUM_VIDS 4096 +#define RTL8367C_NUM_PORTS 7 +#define RTL8367C_NUM_VIDS 4096 struct rtl8367_priv { struct switch_dev swdev; bool global_vlan_enable; }; -struct rtl8367_mib_counter { +struct rtl8367_mib_counter { const char *name; }; @@ -72,13 +72,13 @@ static struct rtl8367_mib_counter rtl8367c_mib_counters[] = { {"etherStatsPkts256to511Octets"}, {"etherStatsPkts512to1023Octets"}, {"etherStatsPkts1024toMaxOctets"}, - {"etherStatsMcastPkts"}, + {"etherStatsMcastPkts"}, {"etherStatsBcastPkts"}, {"ifOutOctets"}, {"dot3StatsSingleCollisionFrames"}, {"dot3StatsMultipleCollisionFrames"}, {"dot3StatsDeferredTransmissions"}, - {"dot3StatsLateCollisions"}, + {"dot3StatsLateCollisions"}, {"etherStatsCollisions"}, {"dot3StatsExcessiveCollisions"}, {"dot3OutPauseFrames"}, @@ -131,7 +131,7 @@ static inline unsigned int rtl8367c_portmask_phy_to_sw(rtk_portmask_t phy_portma if(RTK_PORTMASK_IS_PORT_SET(phy_portmask,rtl8367c_sw_to_phy_port(i))) { RTK_PORTMASK_PORT_CLEAR(phy_portmask,rtl8367c_sw_to_phy_port(i)); RTK_PORTMASK_PORT_SET(phy_portmask,i); - } + } } return (unsigned int)phy_portmask.bits[0]; @@ -155,7 +155,7 @@ static int rtl8367c_get_mibs_num(void) static const char *rtl8367c_get_mib_name(int idx) { - + return rtl8367c_mib_counters[idx].name; } @@ -166,7 +166,7 @@ static int rtl8367c_get_port_mib_counter(int idx, int port, unsigned long long * static int rtl8367c_is_vlan_valid(unsigned int vlan) { - unsigned max = RTL8367C_NUM_VIDS; + unsigned max = RTL8367C_NUM_VIDS; if (vlan == 0 || vlan >= max) return 0; @@ -175,37 +175,37 @@ static int rtl8367c_is_vlan_valid(unsigned int vlan) } static int rtl8367c_get_vlan( unsigned short vid, struct rtl8367_vlan_info *vlan) -{ +{ rtk_vlan_cfg_t vlan_cfg; memset(vlan, '\0', sizeof(struct rtl8367_vlan_info)); if (vid >= RTL8367C_NUM_VIDS) - return -EINVAL; + return -EINVAL; if(rtk_vlan_get(vid,&vlan_cfg)) - return -EINVAL; - + return -EINVAL; + vlan->vid = vid; - vlan->member = rtl8367c_portmask_phy_to_sw(vlan_cfg.mbr); - vlan->untag = rtl8367c_portmask_phy_to_sw(vlan_cfg.untag); + vlan->member = rtl8367c_portmask_phy_to_sw(vlan_cfg.mbr); + vlan->untag = rtl8367c_portmask_phy_to_sw(vlan_cfg.untag); vlan->fid = vlan_cfg.fid_msti; return 0; } static int rtl8367c_set_vlan( unsigned short vid, u32 mbr, u32 untag, u8 fid) -{ +{ rtk_vlan_cfg_t vlan_cfg; int i; - memset(&vlan_cfg, 0x00, sizeof(rtk_vlan_cfg_t)); + memset(&vlan_cfg, 0x00, sizeof(rtk_vlan_cfg_t)); for (i = 0; i < RTL8367C_NUM_PORTS; i++) { if (mbr & (1 << i)) { RTK_PORTMASK_PORT_SET(vlan_cfg.mbr, rtl8367c_sw_to_phy_port(i)); if(untag & (1 << i)) - RTK_PORTMASK_PORT_SET(vlan_cfg.untag, rtl8367c_sw_to_phy_port(i)); + RTK_PORTMASK_PORT_SET(vlan_cfg.untag, rtl8367c_sw_to_phy_port(i)); } } vlan_cfg.fid_msti=fid; @@ -217,9 +217,9 @@ static int rtl8367c_set_vlan( unsigned short vid, u32 mbr, u32 untag, u8 fid) static int rtl8367c_get_pvid( int port, int *pvid) { u32 prio=0; - + if (port >= RTL8367C_NUM_PORTS) - return -EINVAL; + return -EINVAL; return rtk_vlan_portPvid_get(rtl8367c_sw_to_phy_port(port),pvid,&prio); } @@ -228,16 +228,16 @@ static int rtl8367c_get_pvid( int port, int *pvid) static int rtl8367c_set_pvid( int port, int pvid) { u32 prio=0; - + if (port >= RTL8367C_NUM_PORTS) - return -EINVAL; + return -EINVAL; return rtk_vlan_portPvid_set(rtl8367c_sw_to_phy_port(port),pvid,prio); } static int rtl8367c_get_port_link(int port, int *link, int *speed, int *duplex) { - + if(rtk_port_phyStatus_get(rtl8367c_sw_to_phy_port(port),(rtk_port_linkStatus_t *)link, (rtk_port_speed_t *)speed,(rtk_port_duplex_t *)duplex)) return -EINVAL; @@ -252,7 +252,7 @@ rtl8367_sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) { - struct rtl8367_priv *priv = container_of(dev, struct rtl8367_priv, swdev); + struct rtl8367_priv *priv = container_of(dev, struct rtl8367_priv, swdev); priv->global_vlan_enable = val->value.i ; @@ -295,7 +295,7 @@ static int rtl8367_sw_reset_port_mibs(struct switch_dev *dev, static int rtl8367_sw_get_port_mib(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -{ +{ int i, len = 0; unsigned long long counter = 0; static char mib_buf[4096]; @@ -305,7 +305,7 @@ static int rtl8367_sw_get_port_mib(struct switch_dev *dev, len += snprintf(mib_buf + len, sizeof(mib_buf) - len, "Port %d MIB counters\n", - val->port_vlan); + val->port_vlan); for (i = 0; i port_vlan)) return -EINVAL; @@ -401,8 +401,8 @@ static int rtl8367_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val * u32 untag = 0; u8 fid=0; int err; - int i; - + int i; + if (!rtl8367c_is_vlan_valid(val->port_vlan)) return -EINVAL; @@ -430,7 +430,7 @@ static int rtl8367_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val * //pr_info("[%s] vid=%d , mem=%x,untag=%x,fid=%d \n",__func__,val->port_vlan,member,untag,fid); - return rtl8367c_set_vlan(val->port_vlan, member, untag, fid); + return rtl8367c_set_vlan(val->port_vlan, member, untag, fid); } @@ -442,7 +442,7 @@ static int rtl8367_sw_get_port_pvid(struct switch_dev *dev, int port, int *val) static int rtl8367_sw_set_port_pvid(struct switch_dev *dev, int port, int val) -{ +{ return rtl8367c_set_pvid(port, val); } @@ -459,17 +459,17 @@ static int rtl8367_sw_reset_switch(struct switch_dev *dev) static int rtl8367_sw_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *link) -{ +{ int speed; if (port >= RTL8367C_NUM_PORTS) return -EINVAL; if(rtl8367c_get_port_link(port,(int *)&link->link,(int *)&speed,(int *)&link->duplex)) - return -EINVAL; + return -EINVAL; if (!link->link) - return 0; + return 0; switch (speed) { case 0: @@ -497,8 +497,8 @@ static struct switch_attr rtl8367_globals[] = { .description = "Enable VLAN mode", .set = rtl8367_sw_set_vlan_enable, .get = rtl8367_sw_get_vlan_enable, - .max = 1, - }, { + .max = 1, + }, { .type = SWITCH_TYPE_NOVAL, .name = "reset_mibs", .description = "Reset all MIB counters", @@ -562,8 +562,8 @@ int rtl8367s_swconfig_init(void (*reset_func)(void)) int err=0; rtl8367_switch_reset_func = reset_func ; - - memset(priv, 0, sizeof(struct rtl8367_priv)); + + memset(priv, 0, sizeof(struct rtl8367_priv)); priv->global_vlan_enable =0; dev->name = "RTL8367C"; @@ -571,7 +571,7 @@ int rtl8367s_swconfig_init(void (*reset_func)(void)) dev->ports = RTL8367C_NUM_PORTS; dev->vlans = RTL8367C_NUM_VIDS; dev->ops = &rtl8367_sw_ops; - dev->alias = "RTL8367C"; + dev->alias = "RTL8367C"; err = register_switch(dev, NULL); pr_info("[%s]\n",__func__); diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_dbg.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_dbg.c index 039d73d876b..6bc9cbbf063 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_dbg.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_dbg.c @@ -49,7 +49,7 @@ static void rtk_dump_mib_type(rtk_stat_port_type_t cntr_idx) rtk_stat_port_get(port, cntr_idx, &Cntr); printk("%8llu", Cntr); } - + printk("\n"); } static void rtk_hal_dump_mib(void) @@ -103,7 +103,7 @@ static void rtk_hal_dump_mib(void) rtk_dump_mib_type(STAT_Dot3InPauseFrames); /* clear MIB */ rtk_stat_global_reset(); - + } static int rtk_hal_dump_vlan(void) @@ -138,7 +138,7 @@ static int rtk_hal_dump_vlan(void) EXT_PORT1) ? '1' : '-'); printk("\n"); } - + return 0; } diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c index d70aeebad92..52cd4de3948 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c @@ -10,7 +10,7 @@ * GNU General Public License for more details. * */ - + #include #include #include @@ -64,7 +64,7 @@ unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsig bus->write(bus, phy_addr, phy_register, write_data); mutex_unlock(&bus->mdio_lock); - + return 0; } @@ -89,7 +89,7 @@ static int rtl8367s_hw_reset(void) static int rtl8367s_vlan_config(int want_at_p0) { rtk_vlan_cfg_t vlan1, vlan2; - + /* Set LAN/WAN VLAN partition */ memset(&vlan1, 0x00, sizeof(rtk_vlan_cfg_t)); @@ -101,7 +101,7 @@ static int rtl8367s_vlan_config(int want_at_p0) RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT1); RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT2); RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT3); - + if (want_at_p0) { RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT4); RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT4); @@ -111,11 +111,11 @@ static int rtl8367s_vlan_config(int want_at_p0) } vlan1.ivl_en = 1; - + rtk_vlan_set(1, &vlan1); - + memset(&vlan2, 0x00, sizeof(rtk_vlan_cfg_t)); - + RTK_PORTMASK_PORT_SET(vlan2.mbr, EXT_PORT1); RTK_PORTMASK_PORT_SET(vlan2.untag, EXT_PORT1); @@ -144,7 +144,7 @@ static int rtl8367s_vlan_config(int want_at_p0) rtk_vlan_portPvid_set(UTP_PORT4, 2, 0); } - return 0; + return 0; } static int rtl8367s_hw_init(void) @@ -201,7 +201,7 @@ static void set_rtl8367s_rgmii(void) rtk_port_macForceLinkExt_set(EXT_PORT1, mode, &mac_cfg); rtk_port_rgmiiDelayExt_set(EXT_PORT1, 1, 3); rtk_port_phyEnableAll_set(ENABLED); - + } void init_gsw(void) @@ -239,9 +239,9 @@ static int rtk_gsw_probe(struct platform_device *pdev) return -EPROBE_DEFER; gsw = devm_kzalloc(&pdev->dev, sizeof(struct rtk_gsw), GFP_KERNEL); - + if (!gsw) - return -ENOMEM; + return -ENOMEM; gsw->dev = &pdev->dev; @@ -263,12 +263,12 @@ static int rtk_gsw_probe(struct platform_device *pdev) "mediatek,port_map", &pm)) { if (!strcasecmp(pm, "wllll")) - rtl8367s_vlan_config(1); + rtl8367s_vlan_config(1); else rtl8367s_vlan_config(0); - + } else { -#ifdef CONFIG_SWCONFIG +#ifdef CONFIG_SWCONFIG rtl8367s_swconfig_init(&init_gsw); #else rtl8367s_vlan_config(0); @@ -280,7 +280,7 @@ static int rtk_gsw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gsw); return 0; - + } static void rtk_gsw_remove(struct platform_device *pdev) diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts index 5d214e38a4e..6648ff884b3 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts @@ -25,7 +25,7 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x10000000>; }; - + leds { compatible = "gpio-leds"; @@ -175,7 +175,7 @@ 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x100000>; - + wifi@0,0 { compatible = "pci168c,0033"; reg = <0x0 0 0 0 0>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts index 9abf20fec58..dc38c66e115 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-gl-b3000.dts @@ -413,7 +413,7 @@ &wifi0 { // IPQ5018 status = "okay"; - + qcom,rproc = <&q6_wcss_pd1>; qcom,userpd-subsys-name = "q6v5_wcss_userpd1"; qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-spnmx56.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-spnmx56.dts index 4993d9d1988..87b29e2defc 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-spnmx56.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq5018-spnmx56.dts @@ -184,7 +184,7 @@ memory-region = <&q6_mem_regions>; firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt", "ath11k/IPQ5018/hw1.0/m3_fw.mdt"; - + // IPQ5018 q6_wcss_pd1: pd-1 { firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt"; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-fap650.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-fap650.dts index 48a046e84f6..ae5852ede1f 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-fap650.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-fap650.dts @@ -13,7 +13,7 @@ / { model = "Yuncore FAP650"; compatible = "yuncore,fap650", "qcom,ipq6018"; - + aliases { ethernet0 = &dp5; ethernet1 = &dp4; @@ -216,7 +216,7 @@ &blsp1_spi1 { status = "okay"; - + flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -321,7 +321,7 @@ nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-bus-width = <8>; - + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-mr7500.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-mr7500.dts index 1b401e326f6..ad411256539 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-mr7500.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-mr7500.dts @@ -13,7 +13,7 @@ / { model = "Linksys MR7500"; compatible = "linksys,mr7500", "qcom,ipq6018"; - + aliases { serial0 = &blsp1_uart3; serial1 = &blsp1_uart2; @@ -25,24 +25,24 @@ label-mac-device = &dp5_syn; }; - + chosen { stdout-path = "serial0:115200n8"; bootargs-append = " root=/dev/ubiblock0_0"; }; - + extcon_usb { pinctrl-0 = <&extcon_usb_pins>; pinctrl-names = "default"; id-gpio = <&tlmm 26 GPIO_ACTIVE_LOW>; status = "okay"; }; - + gpio_keys { compatible = "gpio-keys"; pinctrl-0 = <&button_pins>; pinctrl-names = "default"; - + wps { label = "wps"; linux,code = ; @@ -55,10 +55,10 @@ gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; }; }; - + leds { compatible = "pwm-leds"; - + usb { color = ; function = LED_FUNCTION_USB; @@ -68,7 +68,7 @@ trigger-sources = <&usb3_port1>, <&usb3_port2>; linux,default-trigger = "usbport"; }; - + led_system_red: red { color = ; function = LED_FUNCTION_INDICATOR; @@ -76,14 +76,14 @@ max-brightness = <255>; panic-indicator; }; - + led_system_green: green { color = ; function = LED_FUNCTION_INDICATOR; pwms = <&pwm 3 1250000>; max-brightness = <255>; }; - + led_system_blue: blue { color = ; function = LED_FUNCTION_POWER; @@ -91,7 +91,7 @@ max-brightness = <255>; }; }; - + reg_usb_vbus: regulator-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb_vbus"; @@ -110,7 +110,7 @@ drive-strength = <8>; bias-pull-up; }; - + /*LED_USB*/ mux_1 { pins = "gpio30"; @@ -118,7 +118,7 @@ drive-strength = <8>; bias-pull-down; }; - + /*LED_R*/ mux_2 { pins = "gpio31"; @@ -126,7 +126,7 @@ drive-strength = <8>; bias-pull-down; }; - + /*LED_G*/ mux_3 { pins = "gpio32"; @@ -135,14 +135,14 @@ bias-pull-down; }; }; - + extcon_usb_pins: extcon_usb_pins { pins = "gpio26"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - + button_pins: button_pins { wps_button { pins = "gpio37"; @@ -214,7 +214,7 @@ pinctrl-names = "default"; reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; status = "okay"; - + ethernet-phy-package { #address-cells = <1>; #size-cells = <0>; @@ -222,7 +222,7 @@ reg = <0>; qcom,package-mode = "qsgmii"; - + qca8075_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; @@ -230,14 +230,14 @@ leds { #address-cells = <1>; #size-cells = <0>; - + led@0 { reg = <0>; color = ; function = LED_FUNCTION_LAN; default-state = "keep"; }; - + led@1 { reg = <1>; color = ; @@ -254,14 +254,14 @@ leds { #address-cells = <1>; #size-cells = <0>; - + led@0 { reg = <0>; color = ; function = LED_FUNCTION_LAN; default-state = "keep"; }; - + led@1 { reg = <1>; color = ; @@ -278,14 +278,14 @@ leds { #address-cells = <1>; #size-cells = <0>; - + led@0 { reg = <0>; color = ; function = LED_FUNCTION_LAN; default-state = "keep"; }; - + led@1 { reg = <1>; color = ; @@ -302,14 +302,14 @@ leds { #address-cells = <1>; #size-cells = <0>; - + led@0 { reg = <0>; color = ; function = LED_FUNCTION_LAN; default-state = "keep"; }; - + led@1 { reg = <1>; color = ; @@ -329,14 +329,14 @@ leds { #address-cells = <1>; #size-cells = <0>; - + led@0 { reg = <0>; color = ; function = LED_FUNCTION_WAN; default-state = "keep"; }; - + led@1 { reg = <1>; color = ; @@ -402,7 +402,7 @@ switch_wan_bmp = ; switch_mac_mode = ; switch_mac_mode1 = ; - + qcom,port_phyinfo { port@1 { port_id = <1>; @@ -493,12 +493,12 @@ &dwc_0 { #address-cells = <1>; #size-cells = <0>; - + usb3_port1: port@1 { reg = <1>; #trigger-source-cells = <0>; }; - + usb3_port2: port@2 { reg = <2>; #trigger-source-cells = <0>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap620hd-v1.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap620hd-v1.dts index 64b74728316..18a3759e79d 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap620hd-v1.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap620hd-v1.dts @@ -75,7 +75,7 @@ pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; - + ar8031: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap660hd-v1.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap660hd-v1.dts index 500847c98b1..62d40d7e1b0 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap660hd-v1.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-eap660hd-v1.dts @@ -74,7 +74,7 @@ pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; - + qca8081_28: ethernet-phy@28 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <28>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts index 15ca4d8ec40..91804b862fb 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts @@ -137,7 +137,7 @@ reg = <28>; reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; reset-deassert-us = <10000>; - + leds { #address-cells = <1>; #size-cells = <0>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi index 7f8b8137491..221de781881 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi @@ -158,13 +158,13 @@ pinctrl-names = "default"; status = "okay"; - + tlc59208f@27 { #address-cells = <1>; #size-cells = <0>; compatible = "ti,tlc59108"; reg = <0x27>; - + led@0 { label = "rgb:led0"; reg = <0>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts index 0e184452e30..c56bc704cec 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-homewrk.dts @@ -24,7 +24,7 @@ nand@0 { reg = <0>; /* - * Some devices use Micron NAND with with 8 bit ECC + * Some devices use Micron NAND with with 8 bit ECC * other AMD/Spansion NAND with 4 bit ECC *nand-ecc-strength = <4>; *nand-ecc-step-size = <512>; diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts index 1477019ab94..6d9b94a0bb3 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8174-mx4300.dts @@ -42,7 +42,7 @@ nand@0 { reg = <0>; /* - * Some devices use Micron NAND with with 8 bit ECC + * Some devices use Micron NAND with with 8 bit ECC * other AMD/Spansion NAND with 4 bit ECC *nand-ecc-strength = <4>; *nand-ecc-step-size = <512>; diff --git a/target/linux/ramips/dts/mt7620a_bolt_bl100.dts b/target/linux/ramips/dts/mt7620a_bolt_bl100.dts index 09f3123b4fc..fefa95b3e6a 100644 --- a/target/linux/ramips/dts/mt7620a_bolt_bl100.dts +++ b/target/linux/ramips/dts/mt7620a_bolt_bl100.dts @@ -53,7 +53,7 @@ label = "blue:lte4"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - + led_lte5 { label = "red:lte5"; gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; @@ -81,20 +81,20 @@ gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy1tpt"; }; - + led_wlan5 { function = LED_FUNCTION_WLAN_5GHZ; color = ; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy0tpt"; }; - + led_lan { function = LED_FUNCTION_LAN; color = ; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; }; - + led_wan { function = LED_FUNCTION_WAN; color = ; @@ -227,7 +227,7 @@ &wmac { nvmem-cells = <&eeprom_factory_0>; nvmem-cell-names = "eeprom"; - + pinctrl-names = "default", "pa_gpio"; pinctrl-0 = <&pa_pins>; pinctrl-1 = <&pa_gpio_pins>; diff --git a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts index eb3e8aac54c..507b7644ad3 100644 --- a/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts +++ b/target/linux/ramips/dts/mt7620n_zyxel_keenetic-lite-iii-a.dts @@ -19,7 +19,7 @@ keys { compatible = "gpio-keys"; - + reset { label = "reset"; gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; // #GPIO1 diff --git a/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts b/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts index 788684163ba..f39f79ee87f 100644 --- a/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts +++ b/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts @@ -9,8 +9,8 @@ / { compatible = "comfast,cf-ew72-v2", "mediatek,mt7621-soc"; model = "COMFAST CF-EW72 V2"; - - // There are at least two HW variants of cf-ew72-v2: + + // There are at least two HW variants of cf-ew72-v2: // With external RAM chip and with integrated RAM (RAM chip not soldered). // Both act same. @@ -33,7 +33,7 @@ compatible = "gpio-leds"; // The only both visible and controllable indicator is wifi LED. - // CF-EW72 have 8 LEDs: + // CF-EW72 have 8 LEDs: // "wlan" is the only LED is controllable with GPIO and have proper hole in shell. // "power", "wan" and "lan" LEDs have proper holes in shell, but can not be controlled with GPIO // "hidden_led_2" and "hidden_led_4" can be controlled with GPIO, but have no proper holes in shell @@ -42,14 +42,14 @@ // "noconn_led_6" and "noconn_led_8" exist, but have no proper holes in shell and not controlled: // "noconn_led_6" is between LAN and WLAN LEDs // "noconn_led_8" is after WLAN LED - + // LED "hidden_led_2" between POWER and WAN LEDs is controllable with GPIO, but it has no proper hole in shell; // LED "hidden_led_4" between WAN and LAN LEDs is controllable with GPIO, but it has no proper hole in shell; // TABLE of LEDs. All leds are blue. // // Place (WAN->ANT) | Num | GPIO | LED name (LuCI) | Note - // -----------------|-----|----------------------------------------------------------------------------------------- + // -----------------|-----|----------------------------------------------------------------------------------------- // power | 1 | | | POWER LED. Not controlled with GPIO. // hidden_led_2 | 2 | 13 | blue:hidden_led_2 | This LED does not have proper hole in shell. // wan | 3 | | | WAN LED. Not controlled with GPIO. @@ -99,13 +99,13 @@ reg = <0x0 0x30000>; read-only; }; - + partition@30000 { label = "Config"; reg = <0x30000 0x10000>; read-only; }; - + partition@40000 { label = "factory"; reg = <0x40000 0x10000>; @@ -130,11 +130,11 @@ #nvmem-cell-cells = <1>; }; - // Serial number can be found in "factory" at 0xE100. + // Serial number can be found in "factory" at 0xE100. // it starts and ends with double quotes `"` and is ASCII string }; }; - + partition@50000 { label = "firmware"; compatible = "denx,uimage"; @@ -193,7 +193,7 @@ nvmem-cells = <&macaddr_factory_e000 1>; nvmem-cell-names = "mac-address"; }; - + lan: port@1 { status = "okay"; label = "lan"; diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-2150-r1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-2150-r1.dts index 8a1bae328f3..65cb7e2b206 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-2150-r1.dts +++ b/target/linux/ramips/dts/mt7621_dlink_dir-2150-r1.dts @@ -108,7 +108,7 @@ }; }; }; - + partition@140000 { label = "firmware"; compatible = "denx,uimage"; diff --git a/target/linux/ramips/dts/mt7621_gemtek_wvrtm-130acn.dts b/target/linux/ramips/dts/mt7621_gemtek_wvrtm-130acn.dts index eb5c079901c..d57c77581ed 100644 --- a/target/linux/ramips/dts/mt7621_gemtek_wvrtm-130acn.dts +++ b/target/linux/ramips/dts/mt7621_gemtek_wvrtm-130acn.dts @@ -21,7 +21,7 @@ label = "power"; gpios = <&gpio 27 GPIO_ACTIVE_LOW>; linux,code = ; - }; + }; }; &leds { @@ -40,7 +40,7 @@ nvmem-cell-names = "eeprom"; #address-cells = <2>; #size-cells = <0>; - + band@0 { /* 2.4 GHz */ reg = <0>; diff --git a/target/linux/ramips/dts/mt7621_gemtek_wvrtm-1xxacn.dtsi b/target/linux/ramips/dts/mt7621_gemtek_wvrtm-1xxacn.dtsi index da334508eca..8b645082150 100644 --- a/target/linux/ramips/dts/mt7621_gemtek_wvrtm-1xxacn.dtsi +++ b/target/linux/ramips/dts/mt7621_gemtek_wvrtm-1xxacn.dtsi @@ -99,7 +99,7 @@ function = LED_FUNCTION_INDICATOR; color = ; function-enumerator = <4>; - }; + }; led_power: led-5 { gpios = <&gpio_hc595 5 GPIO_ACTIVE_HIGH>; @@ -183,7 +183,7 @@ read-only; }; - partition@200000 { + partition@200000 { label = "factory"; reg = <0x200000 0x100000>; read-only; @@ -235,7 +235,7 @@ ubiconcat0: partition@400000 { label = "ubiconcat0"; reg = <0x400000 0x1c00000>; - }; + }; }; ubiconcat1: partition@2800000 { diff --git a/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts b/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts index 845afd4ec1f..eea181c3074 100644 --- a/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts +++ b/target/linux/ramips/dts/mt7621_hanyang_hyc-g920.dts @@ -21,7 +21,7 @@ bootargs = "console=ttyS0,115200"; bootargs-override = "console=ttyS0,115200"; }; - + leds { compatible = "gpio-leds"; diff --git a/target/linux/ramips/dts/mt7621_keenetic_kn-1910.dts b/target/linux/ramips/dts/mt7621_keenetic_kn-1910.dts index 97b7c956882..ee09b8895ca 100644 --- a/target/linux/ramips/dts/mt7621_keenetic_kn-1910.dts +++ b/target/linux/ramips/dts/mt7621_keenetic_kn-1910.dts @@ -144,7 +144,7 @@ label = "RF-EEPROM"; reg = <0x100000 0x80000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; diff --git a/target/linux/ramips/dts/mt7628an_cudy_m1200-v1.dts b/target/linux/ramips/dts/mt7628an_cudy_m1200-v1.dts index 05721d99849..2e1381c4afb 100644 --- a/target/linux/ramips/dts/mt7628an_cudy_m1200-v1.dts +++ b/target/linux/ramips/dts/mt7628an_cudy_m1200-v1.dts @@ -30,7 +30,7 @@ linux,code = ; gpios = <&gpio 11 GPIO_ACTIVE_LOW>; }; - + wps { label = "wps"; diff --git a/target/linux/ramips/dts/mt7628an_keenetic_kn-1221.dts b/target/linux/ramips/dts/mt7628an_keenetic_kn-1221.dts index 6f5cf96856e..09dac5421f1 100644 --- a/target/linux/ramips/dts/mt7628an_keenetic_kn-1221.dts +++ b/target/linux/ramips/dts/mt7628an_keenetic_kn-1221.dts @@ -120,7 +120,7 @@ label = "rf-eeprom"; reg = <0x40000 0x10000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; @@ -170,7 +170,7 @@ reg = <0x1030000 0x10000>; read-only; }; - + partition@1040000 { label = "rf-eeprom_res"; reg = <0x1040000 0x10000>; @@ -181,7 +181,7 @@ label = "firmware_2"; reg = <0x1050000 0xe60000>; }; - + partition@1eb0000 { label = "Config_2"; reg = <0x1eb0000 0x40000>; diff --git a/target/linux/ramips/dts/mt7628an_keenetic_kn-1711.dts b/target/linux/ramips/dts/mt7628an_keenetic_kn-1711.dts index 80326a96288..dcabc3fb4e9 100644 --- a/target/linux/ramips/dts/mt7628an_keenetic_kn-1711.dts +++ b/target/linux/ramips/dts/mt7628an_keenetic_kn-1711.dts @@ -137,7 +137,7 @@ label = "rf-eeprom"; reg = <0x40000 0x10000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; @@ -191,7 +191,7 @@ reg = <0x1030000 0x10000>; read-only; }; - + partition@1040000 { label = "rf-eeprom_res"; reg = <0x1040000 0x10000>; @@ -202,7 +202,7 @@ label = "firmware_2"; reg = <0x1050000 0xe60000>; }; - + partition@1eb0000 { label = "Config_2"; reg = <0x1eb0000 0x40000>; diff --git a/target/linux/ramips/dts/mt7628an_keenetic_kn-1713.dts b/target/linux/ramips/dts/mt7628an_keenetic_kn-1713.dts index 52c5338345c..b6ebc485407 100644 --- a/target/linux/ramips/dts/mt7628an_keenetic_kn-1713.dts +++ b/target/linux/ramips/dts/mt7628an_keenetic_kn-1713.dts @@ -137,7 +137,7 @@ label = "rf-eeprom"; reg = <0x40000 0x10000>; read-only; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; @@ -191,7 +191,7 @@ reg = <0x1030000 0x10000>; read-only; }; - + partition@1040000 { label = "rf-eeprom_res"; reg = <0x1040000 0x10000>; @@ -202,7 +202,7 @@ label = "firmware_2"; reg = <0x1050000 0xe60000>; }; - + partition@1eb0000 { label = "Config_2"; reg = <0x1eb0000 0x40000>; diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts index b6a5a61b7ce..065987d6533 100644 --- a/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts +++ b/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts @@ -17,7 +17,7 @@ led-upgrade = &led_power; label-mac-device = ðernet; }; - + chosen { bootargs = "console=ttyS0,115200"; }; @@ -80,7 +80,7 @@ gpios = <&gpio 46 GPIO_ACTIVE_LOW>; linux,code = ; }; - }; + }; }; &spi0 { diff --git a/target/linux/ramips/image/lzma-loader/src/LzmaDecode.c b/target/linux/ramips/image/lzma-loader/src/LzmaDecode.c index cb8345377ea..3470e55d6ec 100644 --- a/target/linux/ramips/image/lzma-loader/src/LzmaDecode.c +++ b/target/linux/ramips/image/lzma-loader/src/LzmaDecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -46,7 +46,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #endif #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -57,9 +57,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -82,7 +82,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -168,7 +168,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int lc = vs->Properties.lc; #ifdef _LZMA_OUT_READ - + UInt32 Range = vs->Range; UInt32 Code = vs->Code; #ifdef _LZMA_IN_CB @@ -210,7 +210,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); UInt32 i; for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; + p[i] = kBitModelTotal >> 1; rep0 = rep1 = rep2 = rep3 = 1; state = 0; globalPos = 0; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + #ifdef _LZMA_IN_CB RC_INIT; #else @@ -275,7 +275,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -287,9 +287,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos #ifdef _LZMA_OUT_READ + globalPos #endif @@ -338,7 +338,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -365,14 +365,14 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 pos; #endif UpdateBit0(prob); - + #ifdef _LZMA_OUT_READ if (distanceLimit == 0) #else if (nowPos == 0) #endif return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; #ifdef _LZMA_OUT_READ pos = dictionaryPos - rep0; @@ -408,7 +408,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -469,7 +469,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) @@ -524,7 +524,7 @@ int LzmaDecode(CLzmaDecoderState *vs, len += kMatchMinLen; #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) + if (rep0 > distanceLimit) #else if (rep0 > nowPos) #endif diff --git a/target/linux/ramips/image/lzma-loader/src/LzmaDecode.h b/target/linux/ramips/image/lzma-loader/src/LzmaDecode.h index 2870eeb9c9c..bd75525aedb 100644 --- a/target/linux/ramips/image/lzma-loader/src/LzmaDecode.h +++ b/target/linux/ramips/image/lzma-loader/src/LzmaDecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -31,7 +31,7 @@ /* Use read function for output data */ /* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, +/* It can increase speed on some 32-bit CPUs, but memory usage will be doubled in that case */ /* #define _LZMA_LOC_OPT */ diff --git a/target/linux/ramips/image/lzma-loader/src/LzmaTypes.h b/target/linux/ramips/image/lzma-loader/src/LzmaTypes.h index 9c27290757c..83f96f46437 100644 --- a/target/linux/ramips/image/lzma-loader/src/LzmaTypes.h +++ b/target/linux/ramips/image/lzma-loader/src/LzmaTypes.h @@ -1,5 +1,5 @@ -/* -LzmaTypes.h +/* +LzmaTypes.h Types for LZMA Decoder @@ -13,12 +13,12 @@ This file is part of LZMA SDK 4.40 (2006-05-01) #ifndef _7ZIP_BYTE_DEFINED #define _7ZIP_BYTE_DEFINED typedef unsigned char Byte; -#endif +#endif #ifndef _7ZIP_UINT16_DEFINED #define _7ZIP_UINT16_DEFINED typedef unsigned short UInt16; -#endif +#endif #ifndef _7ZIP_UINT32_DEFINED #define _7ZIP_UINT32_DEFINED @@ -27,7 +27,7 @@ typedef unsigned long UInt32; #else typedef unsigned int UInt32; #endif -#endif +#endif /* #define _LZMA_NO_SYSTEM_SIZE_T */ /* You can use it, if you don't want */ diff --git a/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c index 7b4f548462c..dbed9d70756 100644 --- a/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.6/drivers/net/ethernet/rtl838x_eth.c @@ -1820,7 +1820,7 @@ static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum if (priv->extaddr >= 0) addr = priv->extaddr; - + if (addr >= RTMDIO_MAX_PORT) return -ENODEV; @@ -1837,7 +1837,7 @@ static int rtmdio_83xx_read(struct mii_bus *bus, int addr, int regnum) if (priv->extaddr >= 0) addr = priv->extaddr; - + if (addr >= RTMDIO_MAX_PORT) return -ENODEV; @@ -1916,10 +1916,10 @@ static int rtmdio_83xx_write(struct mii_bus *bus, int addr, int regnum, u16 val) if (priv->extaddr >= 0) addr = priv->extaddr; - + if (addr >= RTMDIO_MAX_PORT) return -ENODEV; - + page = priv->page[addr]; if (addr >= 24 && addr <= 27 && priv->id == 0x8380) { @@ -1959,10 +1959,10 @@ static int rtmdio_93xx_write(struct mii_bus *bus, int addr, int regnum, u16 val) if (priv->extaddr >= 0) addr = priv->extaddr; - + if (addr >= RTMDIO_MAX_PORT) return -ENODEV; - + page = priv->page[addr]; if (regnum == RTMDIO_PAGE_SELECT) diff --git a/target/linux/siflower/dts/sf21h8898_bananapi_bpi-rv2-nand.dts b/target/linux/siflower/dts/sf21h8898_bananapi_bpi-rv2-nand.dts index 1a77990dd7a..5098e077186 100644 --- a/target/linux/siflower/dts/sf21h8898_bananapi_bpi-rv2-nand.dts +++ b/target/linux/siflower/dts/sf21h8898_bananapi_bpi-rv2-nand.dts @@ -38,7 +38,7 @@ volumes { factory: ubi-volume-factory { volname = "factory"; - + nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; diff --git a/target/linux/siflower/files-6.6/drivers/net/ethernet/siflower/sf_dpns_debugfs.c b/target/linux/siflower/files-6.6/drivers/net/ethernet/siflower/sf_dpns_debugfs.c index d45dc0adebc..9123c6e2e55 100644 --- a/target/linux/siflower/files-6.6/drivers/net/ethernet/siflower/sf_dpns_debugfs.c +++ b/target/linux/siflower/files-6.6/drivers/net/ethernet/siflower/sf_dpns_debugfs.c @@ -412,12 +412,12 @@ static int sf_dpns_mib_open(struct inode *inode, struct file *file) 83 * (DPNS_MAX_PORT + 1)); } -static const struct file_operations sf_dpns_mib_fops = { - .owner = THIS_MODULE, - .open = sf_dpns_mib_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, +static const struct file_operations sf_dpns_mib_fops = { + .owner = THIS_MODULE, + .open = sf_dpns_mib_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, }; void sf_dpns_debugfs_init(struct dpns_priv *priv) diff --git a/tools/include/byteswap.h b/tools/include/byteswap.h index 015f09740ad..a1b9677b988 100644 --- a/tools/include/byteswap.h +++ b/tools/include/byteswap.h @@ -1,4 +1,4 @@ -#if defined(__linux__) || defined(__CYGWIN__) +#if defined(__linux__) || defined(__CYGWIN__) #include_next #else #include diff --git a/tools/patch-image/src/patch-cmdline.c b/tools/patch-image/src/patch-cmdline.c index 9eaa648ec08..7a54f81b721 100644 --- a/tools/patch-image/src/patch-cmdline.c +++ b/tools/patch-image/src/patch-cmdline.c @@ -51,13 +51,13 @@ int main(int argc, char **argv) fprintf(stderr, "Command line string too long\n"); goto err1; } - + if (((fd = open(argv[1], O_RDWR)) < 0) || (ptr = (char *) mmap(0, search_space + CMDLINE_MAX, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0)) == (void *) (-1)) { fprintf(stderr, "Could not open kernel image"); goto err2; } - + for (p = ptr; p < (ptr + search_space); p += 4) { if (memcmp(p, "CMDLINE:", 8) == 0) { found = 1;