From: Jonas Jelonek Date: Tue, 14 Jul 2026 13:16:42 +0000 (+0000) Subject: realtek: pcs: rtl930x: gate WDIG 10G-mode bit on real baud rate X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=refs%2Fpull%2F24232%2Fhead;p=thirdparty%2Fopenwrt.git realtek: pcs: rtl930x: gate WDIG 10G-mode bit on real baud rate This bit was set unconditionally for any 10G-capable SerDes regardless of hw_mode, including SGMII/1000BASEX/2500BASEX running on 10G-capable silicon. The vendor SDK's dal_longan_construct_mac_default_10gmedia_fiber gates it on the port's declared protocol class instead, applying it to PHY-attached XSGMII/USXGMII as well as genuine fiber - the "medium to fiber" naming doesn't match its actual condition. Gate on speed == RTPCS_SDS_PLL_SPD_10000 instead, matching the real 10G-class protocol family, and actively clear it for 1G/2.5G modes so a prior 10G-class configuration doesn't leave it stuck across a runtime downshift. 0 also matches this register's confirmed hardware reset default on an unconfigured SerDes. Link: https://github.com/openwrt/openwrt/pull/24232 Signed-off-by: Jonas Jelonek --- diff --git a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c index 5fe7119318d..12f411db48c 100644 --- a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c @@ -3006,15 +3006,16 @@ static int rtpcs_930x_sds_config_attachment(struct rtpcs_serdes *sds, if (sds->type != RTPCS_SDS_TYPE_10G) return 0; - /* - * dal_longan_construct_mac_default_10gmedia_fiber: set medium to fiber. - * TODO: does this apply to all fiber modes or only 10GBase-R? - */ - ret = rtpcs_sds_write_bits(sds, PAGE_WDIG, 11, 1, 1, 1); + ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); if (ret < 0) return ret; - ret = rtpcs_sds_select_pll_speed(hw_mode, &speed); + /* + * dal_longan_construct_mac_default_10gmedia_fiber: vendor sets this + * for any 10G-class port regardless of attachment, despite the + * name; 0 matches this register's hardware reset default. + */ + ret = rtpcs_sds_write_bits(sds, PAGE_WDIG, 11, 1, 1, speed == RTPCS_SDS_PLL_SPD_10000); if (ret < 0) return ret;