From: Chad Monroe Date: Tue, 11 Aug 2026 03:02:00 +0000 (-0700) Subject: mediatek: filogic: SDG-8733A: reset the radio through pcie3 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=refs%2Fpull%2F24352%2Fhead;p=thirdparty%2Fopenwrt.git mediatek: filogic: SDG-8733A: reset the radio through pcie3 GPIO 9 is the reset input of the MT7995 radio module, active low. The old description used it as a PERST line on pcie0 with active high polarity, so the port reset toggled the module reset at the wrong time and with the wrong polarity. Describe it as wifi-reset-gpios on pcie3, the port wired to the module reset. The PCIe controller then releases the module from reset before link training, with a 100 ms delay. Signed-off-by: Chad Monroe Link: https://github.com/openwrt/openwrt/pull/24352 Signed-off-by: Jonas Jelonek --- diff --git a/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi b/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi index ce25d2892fd..5ebe63e89fb 100644 --- a/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi +++ b/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi @@ -4,12 +4,15 @@ * Author: Chad Monroe * * Second PCIe function of the MT7995/MT7996-233 radio modules. The - * main function (and the radio0 node) lives on pcie0. + * main function (and the radio0 node) lives on pcie0; the module + * reset is wired to the pcie3 port. */ &pcie3 { pinctrl-names = "default"; pinctrl-0 = <&pcie3_1_pins>; + wifi-reset-gpios = <&pio 9 GPIO_ACTIVE_LOW>; + wifi-reset-msleep = <100>; status = "okay"; }; diff --git a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts index f850b427c8e..fbb98cdd786 100644 --- a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts +++ b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts @@ -183,7 +183,6 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_1_pins>; - reset-gpios = <&pio 9 GPIO_ACTIVE_HIGH>; }; &pio {