Refactor duplicate parent rate lookup code into a common function.
Instead of relying on rules like X is always the parent of Y, we use
the driver ops pointer to make sure we are actually getting the correct
parent clock device. This allows the same function to be called from
different clock types and will allow future chip-specific clock drivers
to not have to follow the rules as strictly.
David Lechner [Tue, 3 Mar 2026 19:54:49 +0000 (13:54 -0600)]
clk: mediatek: use correct struct type for infrasys clocks
Fix the private data type struct type in a couple of infrasys clock
functions.
struct mtk_cg_priv is a superset of struct mtk_clk_priv and has the same
layout at the beginning so there was no compile errors or runtime bugs.
This could only be found by inspecting the code.
Change CLK_TOP_CLK13M rate from 130_000_000 to 13_000_000 and
CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the names
suggest, these clocks are 13/26 MHz, not 130/260 MHz.
Simon Glass [Wed, 4 Mar 2026 18:48:53 +0000 (11:48 -0700)]
kbuild: strip sub_make_done from test-script environment
The exported sub_make_done variable leaks into the environment of all
child processes. When make targets like tcheck spawn independent
make-invocations with O=, those child-makes inherit sub_make_done=1,
skip the KBUILD_OUTPUT setup and try to build in the source tree.
A global 'unexport sub_make_done' cannot be used because the build
system itself re-invokes the top-level Makefile for syncconfig (via
'$(MAKE) -f $(srctree)/Makefile syncconfig'). Without sub_make_done,
that child make re-enters the KBUILD_OUTPUT block and recomputes
abs_objtree. With a relative O= path this resolves to a nested
directory (e.g. build/build/) where .config does not exist.
Instead, use 'env -u sub_make_done' in the test-target recipes so only
the test scripts see a clean environment. This allows their child make
invocations to process O= correctly without affecting internal kbuild
recursion.
This is not strictly a bugfix, but compare with:
commit 27529f1cb02d ("kbuild: skip parsing pre sub-make code for recursion")
Macpaul Lin [Thu, 5 Mar 2026 10:23:24 +0000 (18:23 +0800)]
scsi: Adjust SCSI inquiry command data length
Per the SCSI SPC-4 specification, the standard inquiry data length
should not be less than 36 bytes. The current implementation uses 512
bytes, which causes detection failures on some UFS devices (e.g.,
Longsys) that do not expect a transfer length exceeding the standard
inquiry size.
Align the default standard inquiry length with the Linux kernel's
implementation (see drivers/scsi/scsi_scan.c), which uses 36 bytes as
the default. Devices requiring vendor-specific inquiry lengths should
be handled through quirk settings in the future.
Signed-off-by: ht.lin <ht.lin@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Paresh Bhagat [Wed, 11 Feb 2026 09:49:19 +0000 (15:19 +0530)]
configs: Add fragment config for snagfactory tool
Introduce a new fragment configuration in u-boot to enable support for
the snagfactory tool [1], used for factory flashing of boards. Snagfactory
tool first recovers the board via USB DFU (peripheral boot), and then
uses fastboot to flash given binaries/images to MMC or other on-board
memory via USB. The fragment config can be used to generate boot binaries
for board recovery. This fragment config needs to be added additionally,
while building a53 images for USB DFU boot.
The fragment config enables configurations to allow flashing via
fastboot, manage MMC partitions and boot partitions, customize buffer
size and memory usage for fastboot and also integrate OEM commands and
UUU compatibility. It sets CONFIG_BOOTCOMMAND to start fastboot mode
immediately on startup. It also sets BOOTDELAY to 0 to reduce snagfactory
recovery time. Since BOOTCOMMAND and BOOTDELAY configs are being
modified, these changes cannot be placed in existing DFU fragment config.
Snagfactory used mtd support for flashing both SPI NAND and SPI NOR
devices. The fragment config enables mtd in u-boot and also allows SPI
flash to be treated as an MTD device.
Tom Rini [Mon, 16 Mar 2026 14:24:18 +0000 (08:24 -0600)]
Merge patch series "Add PCIe Boot support for TI J784S4 SoC"
Siddharth Vadapalli <s-vadapalli@ti.com> says:
This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.
PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a
Although the J742S2 EVM supports PCIe boot in Hardware, since it is not
enabled yet in Software, disable PCIe boot related configurations that are
not applicable.
Although the J742S2 EVM supports PCIe boot in Hardware, since it is not
enabled yet in Software, disable PCIe boot related configurations that are
not applicable.
configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot
J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
PCIe1 instance is used for PCIe endpoint boot. Enable the configs
required for PCIe boot on the J784S4 platform.
configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot
J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
PCIe1 instance is used for PCIe endpoint boot. Enable the configs
required for PCIe boot on the J784S4 platform.
Additionally, enable configs for J721E WIZ SERDES wrapper, Cadence
Torrent PHY, and MMIO multiplexer. These are required to configure
the SERDES lanes at the R5 SPL stage for PCIe endpoint operation.
phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage
Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.
phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage
Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence
Torrent PHY driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.
arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot
To enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled
and configured at the R5 stage. Add the required clk-data and dev-data
for SERDES0 and PCIE1.
* Require at least 128 KiB of stack space to use EFI sub-system.
* Avoid buffer overrun in efi_var_restore().
* Avoid superfluous variable store writes on unchanged data
* Implement SPI Flash store for EFI variables.
* Add an efidebug ecpt sub-command to display the ECPT table
and a unit test for the command.
Others:
* Add missing include string.h to make exception command build again.
* lib: uuid: add EBBR 2.1 conformance profile GUID
Tom Rini [Tue, 10 Mar 2026 16:26:21 +0000 (10:26 -0600)]
dfu: Make the DFU_WRITE_ALT symbol available outside of DFU
The DFU_WRITE_ALT symbol is used both directly and indirectly (via
UPDATE_COMMON) for EFI capsule updates (FIT or raw), but does not depend
on DFU itself. Move this symbol outside of "if DFU" to remove a Kconfig
dependency problem.
When building qemu_arm64_defconfig with CMD_EXCEPTION a build error occurs:
In file included from cmd/arm/exception64.c:87:
include/exception.h: In function ‘exception_complete’:
include/exception.h:41:23: error: implicit declaration of
function ‘strlen’ [-Wimplicit-function-declaration]
41 | len = strlen(argv[1]);
| ^~~~~~
Add the missing include.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Shantur Rathore [Fri, 13 Mar 2026 15:45:27 +0000 (16:45 +0100)]
efi_vars: Implement SPI Flash store
Currently U-Boot uses ESP as storage for EFI variables.
Devices with SPI Flash are used for storing environment with this
commit we allow EFI variables to be stored on SPI Flash.
Signed-off-by: Shantur Rathore <i@shantur.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905D3-CC Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Michal Simek [Fri, 13 Mar 2026 11:20:37 +0000 (12:20 +0100)]
efi_loader: avoid superfluous variable store writes on unchanged data
Every SetVariable() call triggers efi_var_mem_ins() followed by
efi_var_to_storage(), even when the variable value is not actually
changing. This is unfriendly to flash-backed stores that suffer
wear from unnecessary erase/write cycles.
Add a change-detection path to efi_var_mem_ins(): when size2 == 0
(i.e. not an append) and the caller passes a non-NULL changep flag,
look up the existing variable and compare attributes, length, time
and data byte-by-byte. If everything matches, set *changep = false
and return EFI_SUCCESS without touching the variable buffer.
Both efi_set_variable_int() and efi_set_variable_runtime() now
check the flag and skip efi_var_mem_del() / efi_var_to_storage()
when nothing changed.
Introduce efi_memcmp_runtime() - a runtime-safe byte-by-byte memory
comparison helper, following the same pattern as the existing
efi_memcpy_runtime(). The standard memcmp() is not available after
ExitBootServices() and calling it from Linux will crash.
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Vincent Stehlé [Mon, 9 Mar 2026 16:36:35 +0000 (17:36 +0100)]
lib: uuid: add EBBR 2.1 conformance profile GUID
Add support for printing the EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID as human
readable text.
This is compiled in only when CONFIG_CMD_EFIDEBUG and CONFIG_EFI_EPCT are
set.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
efi_loader: require at least 128 KiB of stack space
The UEFI specification requires at least 128 KiB stack space. Consider this
value as a prerequisite for CONFIG_EFI_LOADER.
Mention the requirement in the CONFIG_STACK_SPACE description and decribe
that the UEFI sub-system uses CONFIG_STACK_SPACE when defining the memory
map.
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Jonas Karlman [Mon, 9 Mar 2026 21:02:32 +0000 (21:02 +0000)]
rockchip: rk3568: Include all addressable DRAM in memory map
Rockchip RK356x supports up to 8 GiB DRAM, however U-Boot only includes
the initial 32-bit 0-4 GiB addressable range in its memory map,
something that matches gd->ram_top and current expected memory available
for use in U-Boot.
The vendor DRAM init blobs add following ddr_mem rk atags [1]:
Add the remaining 64-bit 4-8 GiB addressable range, that already is
reported to OS, to the U-Boot memory map to more correctly describe all
available and addressable DRAM of RK356x. While at it also add the
missing UL suffix to the PCIe address range for consistency.
Tom Rini [Fri, 13 Mar 2026 20:59:38 +0000 (14:59 -0600)]
Merge patch series "k3_*: Add config fragments for inline ECC and BIST"
Neha Malcom Francis <n-francis@ti.com> says:
Typically we do not enable these configs by default but would still like to
have the option to start building them in our default build flow for
testing. Also there is the added advantage of users being able to see what
is needed in case they choose to enable these features.
Tom Rini [Fri, 13 Mar 2026 20:58:17 +0000 (14:58 -0600)]
Merge patch series "board: k3: Sync rm-cfg with TIFS v11.02.09 firmware"
Sparsh Kumar <sparsh-kumar@ti.com> says:
This series updates the Resource Management (RM) configuration files
for AM62 family devices to align with the TIFS v11.02.09 firmware.
Background
----------
With the latest TIFS firmware (v11.02.09), an additional virtual
interrupt and event is reserved for MCU cores to DM usage on am62x,
am62ax, and am62px devices. This series brings the rm-cfg and
tifs-rm-cfg files in sync with these firmware changes across both
TI reference boards and vendor boards.
These changes are backward compatible with older TIFS firmware versions.
Additionally, the am62x platform was originally introduced without a
tifs-rm-cfg.yaml file, unlike other platforms in the AM62 family.
This series addresses that gap and enables tifs-rm-cfg in binman for
am625-sk and am62p-sk platforms.
Changes
-------
TI reference boards (patches 1-4):
- Update rm-cfg.yaml for am62x, am62ax, am62px
- Sync am62px tifs-rm-cfg.yaml with TIFS firmware template
- Add missing tifs-rm-cfg.yaml for am62x
- Enable tifs-rm-cfg in binman for am625-sk and am62p-sk
with the required interrupt reservation. The tifs-rm-cfg.yaml files
cannot be updated without access to the corresponding SysConfig files,
as both rm-cfg.yaml and tifs-rm-cfg.yaml must remain in sync.
Sparsh Kumar [Wed, 25 Feb 2026 13:24:20 +0000 (18:54 +0530)]
arm: dts: k3: am62x/am62px: Enable tifs-rm-cfg in binman
Add rcfg_yaml_tifs node override to use tifs-rm-cfg.yaml instead of
the default rm-cfg.yaml for am625-sk and am62p-sk platforms.
This enables binman to include the tifs-rm-cfg.yaml configuration
when building tiboot3 images, bringing these platforms in line with
other K3 devices like am62a-sk that already use tifs-rm-cfg.yaml.
This builds on the tifs-rm-cfg files added/updated earlier in this series.
Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Sparsh Kumar [Wed, 25 Feb 2026 13:24:19 +0000 (18:54 +0530)]
board: ti: am62x: tifs-rm-cfg: Add the missing tifs-rm-cfg:
The am62x platform was originally introduced without a
tifs-rm-cfg.yaml file. Add the tifs-rm-cfg to bring am62x
in line with other am62 family of devices (am62px and am62a)
which all include this file.
This complements the rm-cfg update earlier in this series.
Sparsh Kumar [Wed, 25 Feb 2026 13:24:17 +0000 (18:54 +0530)]
board: ti: rm-cfg: Update rm-cfg to reflect new resource reservation
With the latest v11.02.09 TIFS firmware, an additional
virtual interrupt and event is reserved for MCU cores
to DM usage on am62x, am62ax and am62px devices.
Update the rm-cfg to reflect this new reservation.
Updates the polarities for the GPIOs on the sc594
EZKIT carrier board for the newest revision, Rev D.
The new carrier board revision has different polarities
for some GPIOs. This patch updates the sc594 entries
to match the sc598 entries that were updated in a previous
commit, as both SOMs can utilize the EZKIT.
Note that these updates are for the EZKIT carrier
board used by both sc598 and sc594 SOMs, not the SOMs themselves.
Fixes: be79378 ("board: adi: Add support for SC594") Signed-off-by: Caleb Ethridge <caleb.ethridge@analog.com> Reviewed-by: Greg Malysa <malysagreg@gmail.com>
Anton Moryakov [Thu, 26 Feb 2026 21:27:28 +0000 (00:27 +0300)]
linux_compat: fix NULL pointer dereference in get_mem()
Add NULL check after memalign() call in get_mem() to prevent
potential NULL pointer dereference (CWE-476).
The function memalign() can return NULL on allocation failure.
Dereferencing the returned pointer without checking for NULL
may cause a crash in low-memory conditions.
Changes:
- Add NULL check after memalign() allocation
- Return NULL on failure, consistent with function semantics
This fixes the static analyzer warning:
linux_compat.c:34: dereference of memalign return value without NULL check
Reported-by: static analyzer Svace Signed-off-by: Anton Moryakov <ant.v.moryakov@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nikita Shubin [Thu, 26 Feb 2026 16:39:10 +0000 (19:39 +0300)]
serial: ns16550: Fix return-type warning
Fix compiler warning:
drivers/serial/ns16550.c: In function ‘serial_in_dynamic’:
drivers/serial/ns16550.c:153:1: warning: control reaches end
of non-void function [-Wreturn-type]
153 | }
| ^
Anurag Dutta [Thu, 26 Feb 2026 09:05:24 +0000 (14:35 +0530)]
arm: dts: k3-j721s2*: Enable OSPI1 with 32-bit address mappings for R5 SPL
The R5 SPL requires 32-bit address mappings for OSPI1(QSPI) access.
Override the OSPI1 node with appropriate 32-bit register ranges to
enable proper address translation on the 32-bit R5 core, while
preserving 64-bit mappings for A72 cores. While at it, remove the
disabled status override for ospi1 node to support booting from
qspi.
Michal Simek [Thu, 26 Feb 2026 09:27:16 +0000 (10:27 +0100)]
spl: Remake SPL elf from bin
On Xilinx MB-V there is a need to use ELF file for SPL which is placed
in BRAM (Block RAM) because tools for placing code to bitstream requires to
use ELF. That's why introduce SPL_REMAKE_ELF similar to REMAKE_ELF option
as was originally done by commit f4dc714aaa2d ("arm64: Turn u-boot.bin back
into an ELF file after relocate-rela").
There is already generic and simple linker script (arch/u-boot-elf.lds)
which can be also used without any modification.
Signed-off-by: Michal Simek <michal.simek@amd.com>
spl: spi: fix loss of spl_load() error on soft reset
When CONFIG_SPI_FLASH_SOFT_RESET is enabled, spi_nor_remove() is called
after spl_load() to switch the flash back to legacy SPI mode. However,
the return value of spi_nor_remove() unconditionally overwrites the
return value of spl_load(), discarding any load error.
Fix this by preserving the spl_load() error and only propagating the
spi_nor_remove() error as a fallback. Also log a message when
spi_nor_remove() fails, since in the case where spl_load() already
failed its error would otherwise be silently discarded.
Marek Vasut [Tue, 27 Jan 2026 23:48:40 +0000 (00:48 +0100)]
lmb: Reinstate access to memory above ram_top
Revert commit eb052cbb896f ("lmb: add and reserve memory above ram_top")
and commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from
same bank"). These are based on incorrect premise of the first commit, that
"U-Boot does not use memory above ram_top". While U-Boot itself indeed does
not and should not use memory above ram_top, user can perfectly well use
that memory from the U-Boot shell, for example to load content in there.
Currently, attempt to use that memory to load large image using TFTP ends
with "TFTP error: trying to overwrite reserved memory...". With this change
in place, the memory can be used again.
Fixes: eb052cbb896f ("lmb: add and reserve memory above ram_top") Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Reported-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
net:
- Move network PHY under NETDEVICES
- s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO}
- Add support for Airoha AN8811HB PHY
- airoha: PCS and MDIO support for Airoha AN7581 SoC
net-lwip:
- Fix issue when TFTP blocksize is >8192
- Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and
resource usage.
- Enable mii command for NET_LWIP
Tom Rini [Tue, 10 Mar 2026 16:26:14 +0000 (10:26 -0600)]
net: Move network PHY under NETDEVICES
A number of network PHY drivers have Kconfig dependencies on various
network drivers under NETDEVICES. This is in addition to logical
dependencies of network PHYs needing network drivers. Resolve the
Kconfig problems by moving the network PHY lines to be after the network
devices, within the overall NETDEVICES guard.
Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Jerome Forissier <jerome.forissier@arm.com>
Pranav Tilak [Tue, 10 Mar 2026 12:58:25 +0000 (18:28 +0530)]
net: lwip: scale buffer pool size with TFTP block size
TFTP transfers fail when tftpblocksize is set to 8192 or larger due to
insufficient buffer resources for IP fragment reassembly.
Calculate PBUF_POOL_SIZE and IP_REASS_MAX_PBUFS dynamically based on
CONFIG_TFTP_BLOCKSIZE using IP fragmentation boundaries (1480 usable
bytes per fragment at 1500 MTU). The pool size includes headroom for
TX, ARP, and protocol overhead, while ensuring PBUF_POOL_SIZE remains
greater than IP_REASS_MAX_PBUFS as required by lwIP.
Jonas Karlman [Mon, 9 Mar 2026 21:06:39 +0000 (21:06 +0000)]
net: lwip: Fix PBUF_POOL_BUFSIZE when PROT_TCP_LWIP is disabled
The PBUF_POOL_BUFSIZE ends up being only 592 bytes, instead of 1514,
when PROT_TCP_LWIP Kconfig option is disabled. This results in a full
Ethernet frame requiring three PBUFs instead of just one.
This happens because the PBUF_POOL_BUFSIZE constant depends on the value
of a TCP_MSS constant, something that defaults to 536 when PROT_TCP_LWIP
is disabled.
Tommy Shih [Thu, 26 Feb 2026 08:52:00 +0000 (16:52 +0800)]
net: phy: air_en8811: add support for Airoha AN8811HB PHY
Add support for the Airoha AN8811HB 2.5 Gigabit PHY to the existing
en8811h driver. This PHY supports 10/100/1000/2500 Mbps speeds.
Update the driver to recognize the AN8811HB PHY ID and handle its
specific firmware loading requirements. The firmware loading mechanism
remains consistent with the existing implementation.
This driver is based on:
- Linux upstream PHY subsystem (v7.0-rc1)
- air_an8811hb v0.0.4 out-of-tree uboot driver written by
"Lucien.Jheng <lucien.jheng@airoha.com>"
Current code just bind mt7531 mdio with it's driver, so mdio device may
not be probed and hense not usable.
This patch:
* Forces probing of mt7531 mdio for GDM1 port
* Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have
multiple available MDIO, so the name 'mdio' isn't descriptive enough.
* Sets mdio bus for the GDM port device
net: airoha: fill in support for PCS/PHY in Airoha Ethernet driver
Add required changes to call PCS function to configure the Serdes Port.
The Ethernet driver is adapted following Upstream Kernel node structure.
Function calling order is the same of Phylink upstream kernel.
With the PCS support, also add support for attaching PHY. With
"in-band-status" set in DT for the managed property, a rudimental
support for SFP module is present.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
net: airoha-pcs: an7581: sync with linux code a bit
based on linux kernel patches from
https://github.com/Ansuel/openwrt/commits/openwrt-24.10-airoha-an7581-stable/
created by Christian Marangi <ansuelsmth@gmail.com>
Tom Rini [Thu, 12 Mar 2026 13:45:29 +0000 (07:45 -0600)]
Merge tag 'mediatek-for-next-2026-03-11' of https://source.denx.de/u-boot/custodians/u-boot-mediatek into next
A fix:
* Fixing compiling MT8195 due to some independent changes that were applied
around the same time as MT8195 support was merged. (CI would not have caught
this since we didn't have a defconfig until now).
And few small features:
* New defconfig for MT8395/Genio 1200 EVK.
* pinctrl support for MT8189-compatible SoCs.
net: airoha: add initial support for multiple GDM port
Rework the driver to support multiple GDM port. The driver is split to
main driver as a MISC driver with forced probe (by using the
DM_FLAG_PROBE_AFTER_BIND) and each GDM port register a ETH driver.
This permit a 1:1 implementation with the linux kernel driver and permit
to use the same exact DT nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
common: spl: spl_dfu.c: Fix warning associated with PCI subclass_code
The subclass_code member of the pci_ep_header structure is a 1-byte
field. The macro PCI_CLASS_MEMORY_RAM is a concetation of baseclass_code
and subclass_code as follows:
PCI_BASE_CLASS_MEMORY: 0x05
Subclass Code for RAM: 0x00
PCI_CLASS_MEMORY_RAM: 0x0500
Hence, instead of extracting it via an implicity type conversion from int
to u8 which throws a warning, explicitly mask the bits to extract the
subclass_code.
Alexey Charkov [Tue, 20 Jan 2026 18:09:02 +0000 (22:09 +0400)]
spl: Make UFS available for SPL builds
Add minimal infrastructure to build SPL images with support for UFS
storage devices. This also pulls in SCSI support and charset functions,
which are dependencies of the UFS code.
With this, only a fixed offset is supported for loading the next image,
which should be specified in CONFIG_SPL_UFS_RAW_U_BOOT_SECTOR as the
number of 4096-byte sectors into the UFS block device.
David Lechner [Mon, 9 Feb 2026 23:34:18 +0000 (17:34 -0600)]
pinctl: mediatek: increase max number of base addresses
Increase the maximum number of base addresses that can be handled by the
mediatek pinctrl driver from 10 to 15. This is needed for the MT8189
which has 15 base addresses.
Shiva Tripathi [Wed, 25 Feb 2026 11:24:38 +0000 (16:54 +0530)]
arm: k3: Kconfig: Enable fTPM and RPMB support
Enable firmware TPM (fTPM) support via OP-TEE for K3 platforms with
MMC hardware. This provides TPM 2.0 functionality through
Microsoft's fTPM Trusted Application running in OP-TEE secure world,
using eMMC RPMB as persistent storage.
fTPM support in U-Boot provides the foundation for measured boot
and disk encryption use cases.
The ARM64 condition ensures these apply only to A53/A72 cores and the
MMC condition ensures fTPM is enabled only on platforms with eMMC
hardware support.
Signed-off-by: Shiva Tripathi <s-tripathi1@ti.com> Acked-by: Andrew Davis <afd@ti.com>
Add checkkconfigsymbols.py from Linux 7.0-rc1 (unchanged since v6.2).
This tool allows to identify the usage of symbols that are not defined
in Kconfig.
projects / thirdparty / u-boot.git / log
