Lin, Meng-Bo [Fri, 6 Jan 2023 14:31:19 +0000 (14:31 +0000)]
arm64: dts: qcom: msm8916-samsung-j5-common: Add new device trees
After moving msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi,
Add new J5 2016 device tree.
[Add j5x device tree]
Co-developed-by: Josef W Menad <JosefWMenad@protonmail.ch> Signed-off-by: Josef W Menad <JosefWMenad@protonmail.ch>
[Use &pm8916_usbin as USB extcon and add chassis-type for j5x] Co-developed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
[Use common init device tree] Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143024.547194-1-linmengbo0689@protonmail.com
Move msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi, and add
a common device tree for with initial support for:
- GPIO keys
- SDHCI (internal and external storage)
- USB Device Mode
- UART (on USB connector via the SM5703 MUIC)
- WCNSS (WiFi/BT)
- Regulators
The two devices (all other variants of J5 released in 2015 and J5X
released in 2016) are very similar, with some differences in display and
GPIO pins. The common parts are shared in msm8916-samsung-j5-common.dtsi
to reduce duplication.
This patch rewrites J5 2015 devices, later patches will add support for
other models.
Konrad Dybcio [Wed, 4 Jan 2023 17:16:42 +0000 (18:16 +0100)]
arm64: dts: qcom: sm6350: Set up DDR & L3 scaling
Add the CPU OPP tables including core frequency and L3 bus frequency.
The L3 throughput values were chosen by studying the frequencies
available in HW LUT and picking the highest one that's less than the
CPU frequency. DDR clock rates come from the vendor kernel.
Alex Elder [Sat, 31 Dec 2022 00:27:16 +0000 (18:27 -0600)]
arm64: dts: qcom: use qcom,gsi-loader for IPA
Depending on the platform, either the modem or the AP must load GSI
firmware for IPA before it can be used. To date, this has been
indicated by the presence or absence of a "modem-init" property.
That mechanism has been deprecated. Instead, we indicate how GSI
firmware should be loaded by the value of the "qcom,gsi-loader"
property.
Update all arm64 platforms that use IPA to use the "qcom,gsi-loader"
property to specify how the GSI firmware is loaded.
Update the affected nodes so the status property is last.
Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Moved sc7280 change herobrine-lte-sku] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221231002716.2367375-3-elder@linaro.org
arm64: dts: qcom: sc7280-idp: add amp pin config function
Bindings expect each pin config to come with a "function" property:
sc7280-crd-r3.dtb: pinctrl@f100000: amp-en-state: 'oneOf' conditional failed, one must be fixed:
'function' is a required property
'bias-pull-down', 'drive-strength', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+'
Fixes: 976d321f32dc ("arm64: dts: qcom: msm8992: Make the DT an overlay on top of 8994") Signed-off-by: Petr Vorel <petr.vorel@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226185440.440968-3-pevik@seznam.cz
Original google firmware reports 12 MiB:
[ 0.000000] cma: Found cont_splash_mem@0, memory base 0x0000000003400000, size 12 MiB, limit 0xffffffffffffffff
which is actually 12*1024*1024 = 0xc00000.
This matches the aosp source [1]:
&cont_splash_mem {
reg = <0 0x03400000 0 0xc00000>;
};
Fixes: 3cb6a271f4b0 ("arm64: dts: qcom: msm8992-bullhead: Fix cont_splash_mem mapping") Fixes: 976d321f32dc ("arm64: dts: qcom: msm8992: Make the DT an overlay on top of 8994")
[1] https://android.googlesource.com/kernel/msm.git/+/android-7.0.0_r0.17/arch/arm64/boot/dts/lge/msm8992-bullhead.dtsi#141
Bjorn Andersson [Wed, 18 Jan 2023 22:59:11 +0000 (16:59 -0600)]
Merge tag 'qcom-arm64-fixes-for-6.2' into arm64-for-6.3
Qualcomm ARM64 DTS fixes for 6.2
The cluster idle issue was resolved on SM8250, so the change disabling
the cluster state is being reverted.
Issues where identified with the QMP PHY binding, that would prevent
enablement of Displayport and it was decided not to support the old
binding for the recently introduced SC8280XP, which broke USB. This
adjusts the USB PHY nodes to the new binding. The reset signal for the
first QMP PHY is corrected as well.
The reserved memory map is updated on Xiaomi Mi 4C and Huawei Nexus 6P,
to avoid instabilities caused by use of protected memory regions.
The compatible for the MSM8992 TCSR mutex is corrected as well.
Lastly SDHCI interconnects on SM8350 are corrected to match the
providers #interconnect-cells.
Growing the CMA region and querying /proc/meminfo indicates that a newly
booted system (currently) uses 64MB CMA.
Define a memory region sufficiently large for the current use cases, to
avoid forcing users to add this themselves, through command line
parameters etc.
While fixing the CRD define the same region for the X13s.
Johan Hovold [Tue, 3 Jan 2023 10:31:36 +0000 (11:31 +0100)]
arm64: dts: qcom: sc8280xp: disable sound nodes
The sound nodes in the SoC dtsi should be disabled by default.
Note that the lpass-tlmm and macro blocks depend on having the board dts
enable the adsp and specifying an appropriate firmware to enable the
q6prm clock controller.
arm64: dts: qcom: sc8280xp: drop bogus clock-controller property
There is no "clock-controller" property:
sa8295p-adp.dtb: service@2: clock-controller: 'clock-controller' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/sound/qcom,q6prm.yaml
Kuogee Hsieh [Tue, 27 Dec 2022 17:44:59 +0000 (09:44 -0800)]
arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
arm64: dts: qcom: sm8350: drop unused dispcc power-domain-names
Display clock controller bindings do not allow power-domain-names:
sm8350-hdk.dtb: clock-controller@af00000: 'power-domain-names' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
Bjorn Andersson [Thu, 12 Jan 2023 13:50:55 +0000 (05:50 -0800)]
arm64: dts: qcom: sc8280xp: Use MMCX for all DP controllers
While MDSS_GDSC is a subdomain of MMCX, Linux does not respect this
relationship and sometimes invokes sync_state on the rpmhpd (MMCX)
before the DisplayPort controller has had a chance to probe.
The result when this happens is that the power is lost to the multimedia
subsystem between the probe of msm_drv and the DisplayPort controller -
which results in an irrecoverable state.
While this is an implementation problem, this aligns the power domain
setting of the one DP instance with that of all the others.
Fixes: 57d6ef683a15 ("arm64: dts: qcom: sc8280xp: Define some of the display blocks") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230112135055.3836555-1-quic_bjorande@quicinc.com
Johan Hovold [Thu, 12 Jan 2023 07:45:03 +0000 (08:45 +0100)]
arm64: dts: qcom: sc8280xp-crd: allow vreg_l3b to be disabled
The vreg_l3b supply is used by the eDP, UFS and USB1 PHYs which are now
described by the devicetree so that the regulator no longer needs to be
marked always-on.
Bjorn Andersson [Thu, 12 Jan 2023 13:51:17 +0000 (05:51 -0800)]
arm64: dts: qcom: sc8280xp: Vote for CX in USB controllers
Running GCC_USB30_*_MASTER_CLK at 200MHz requires CX at nominal level,
not doing so results in occasional lockups. This was previously hidden
by the fact that the display stack incorrectly voted for CX (instead of
MMCX).
Stephan Gerhold [Sat, 7 Jan 2023 11:09:58 +0000 (12:09 +0100)]
arm64: dts: qcom: msm8916: Add DMA for all I2C controllers
i2c-qup allows using DMA to speed up larger transfers. In msm8916.dtsi
the DMA channels are already assigned to the SPI controllers but
missing for I2C. Add them there as well.
This also fixes confusing errors in dmesg for each I2C controller:
i2c_qup 78b6000.i2c: tx channel not available
Stephan Gerhold [Sat, 7 Jan 2023 11:09:57 +0000 (12:09 +0100)]
arm64: dts: qcom: msm8916: Enable blsp_dma by default
Adding the "dmas" to the I2C controllers prevents probing them if
blsp_dma is disabled (infinite probe deferral). Avoid this by enabling
blsp_dma by default - it's an integral part of the SoC that is almost
always used (even if just for UART).
Marijn Suijten [Mon, 9 Jan 2023 23:41:32 +0000 (00:41 +0100)]
arm64: dts: qcom: sdm845-tama: Add volume up and camera GPIO keys
Tama has four GPIO-wired keys: two for camera focus and shutter /
snapshot, and two more for volume up and down. As per the comment these
used to not work because the necessary pin bias was missing, which is
now set via pinctrl on pm8998_gpios.
The missing bias has also been added to the existing volume down button,
which receives a node name and label cleanup at the same time to be more
consistent with other DTS and the newly added buttons. Its deprecated
gpio-key,wakeup property has also been replaced with wakeup-source.
Note that volume up is also available through the usual PON RESIN node,
but unlike other platforms only triggers when the power button is held
down at the same time making it unsuitable to serve as KEY_VOLUMEUP.
Fixes: 30a7f99befc6 ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109234133.365644-1-marijn.suijten@somainline.org
arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
received from endpoint devices to the CPU using GIC-ITS MSI controller.
Add support for it.
Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the
msi-map-mask of 0xff00, all the 32 devices under these two busses can
share the same Device ID.
The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.
It should be noted that the MSIs for BDF (1:0.0) only works with Device
ID of 0x5980 and 0x5a00. Hence, the IDs are swapped.
Eric Chanudet [Mon, 19 Dec 2022 19:10:01 +0000 (14:10 -0500)]
arm64: dts: qcom: pm8941-rtc add alarm register
A few descriptions including a qcom,pm8941-rtc describe two reg-names
for the "rtc" and "alarm" register banks, but only one offset.
For consistency with reg-names, add the "alarm" register offset.
No functional change is expected from this.
Signed-off-by: Eric Chanudet <echanude@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221219191000.2570545-5-echanude@redhat.com
arm64: dts: qcom: replace underscores in node names
Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens. In few places adjust the name to
match other nodes (e.g. xxx-regulator).
Konrad Dybcio [Tue, 13 Dec 2022 13:25:17 +0000 (14:25 +0100)]
arm64: dts: qcom: sm8450-nagara: Disable empty i2c bus
As much as it hurts me, there is no FM radio chips on these devices.
It seems to be present on Japanese models, but these are not available
globally and differ in a few more ways anyway (such as a super high-tech
NFC chip). Since it's the only subdevice of its I2C host bus, disable
said bus to save some power.
Konrad Dybcio [Tue, 13 Dec 2022 13:25:16 +0000 (14:25 +0100)]
arm64: dts: qcom: sm8350-sagami: Disable empty i2c bus
As much as it hurts me, there is no FM radio chips on these devices.
It seems to be present on Japanese models, but these are not available
globally and differ in a few more ways anyway (such as a super high-tech
NFC chip). Since it's the only subdevice of its I2C host bus, disable
said bus to save some power.
As much as it hurts me, there is no FM radio chips on these devices.
It seems to be present on Japanese models, but these are not available
globally and differ in a few more ways anyway (such as a super high-tech
NFC chip).
The Always On Subsystem (AOSS) QMP is not a power domain controller
since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property
to control load state") and few others. In fact, it was never a power
domain controller but rather control of power state of remote
processors. This power state control is now handled differently, thus
the AOSS QMP nodes do not have power-domain-cells:
sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property
From schema: Documentation/devicetree/bindings/power/power-domain.yaml
AOSS QMP is an interface to the actuall AOSS subsystem responsible for
some of power management functions, thus let's call the nodes as
"power-management".
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to
get pcie 2a controller enabled on Qdrive3.
This patch enables 4GB 64bit memory space for PCIE_2A to have BAR
allocations of 64bit pref mem needed on this Qdrive3 platform with dual
SoCs for root port and switch NT-EP. Hence this ranges property is
overridden in sa8540p-ride.dts only.
Moved tlmm node at the end as it tends to become rahter long.
arm64: dts: qcom: sdm845: order top-level nodes alphabetically
Order top-level nodes like memory, reserved-memory, opp-table-cpu
alphabetically for easier code maintenance. No functional change (same
dtx_diff, except phandle changes).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221212100232.138519-2-krzysztof.kozlowski@linaro.org
projects / thirdparty / kernel / linux.git / log
