Stephan Gerhold [Mon, 4 Dec 2023 10:21:21 +0000 (11:21 +0100)]
arm64: dts: qcom: msm8939: Make blsp_dma controlled-remotely
The blsp_dma controller is shared between the different subsystems,
which is why it is already initialized by the firmware. We should not
reinitialize it from Linux to avoid potential other users of the DMA
engine to misbehave.
In mainline this can be described using the "qcom,controlled-remotely"
property. In the downstream/vendor kernel from Qualcomm there is an
opposite "qcom,managed-locally" property. This property is *not* set
for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely"
upstream matches the behavior of the downstream/vendor kernel.
Adding this seems to fix some weird issues with UART where both
input/output becomes garbled with certain obscure firmware versions on
some devices.
Stephan Gerhold [Mon, 4 Dec 2023 10:21:20 +0000 (11:21 +0100)]
arm64: dts: qcom: msm8916: Make blsp_dma controlled-remotely
The blsp_dma controller is shared between the different subsystems,
which is why it is already initialized by the firmware. We should not
reinitialize it from Linux to avoid potential other users of the DMA
engine to misbehave.
In mainline this can be described using the "qcom,controlled-remotely"
property. In the downstream/vendor kernel from Qualcomm there is an
opposite "qcom,managed-locally" property. This property is *not* set
for the qcom,sps-dma@7884000 [1] so adding "qcom,controlled-remotely"
upstream matches the behavior of the downstream/vendor kernel.
Adding this seems to fix some weird issues with UART where both
input/output becomes garbled with certain obscure firmware versions on
some devices.
Stephan Gerhold [Mon, 4 Dec 2023 09:55:53 +0000 (10:55 +0100)]
arm64: dts: qcom: msm8939: Add clock-frequency for broadcast timer
Looks like not all firmware versions used for MSM8939 program the timer
frequency for both broadcast/MMIO timers, causing a WARNING at runtime:
WARNING: CPU: 0 PID: 0 at kernel/time/clockevents.c:38 cev_delta2ns+0x74/0x90
pc : cev_delta2ns+0x74/0x90
lr : clockevents_config.part.0+0x64/0x8c
Call trace:
cev_delta2ns+0x74/0x90
clockevents_config_and_register+0x20/0x34
arch_timer_mem_of_init+0x374/0x534
timer_probe+0x88/0x110
time_init+0x14/0x4c
start_kernel+0x2c0/0x640
Unfortunately there is no way to fix the firmware on most of these
devices since it's proprietary and signed. As a workaround, specify the
clock-frequency explicitly in the DT to fix the warning.
Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Reported-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231204-msm8939-timer-v1-1-a2486c625786@gerhold.net Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Mon, 4 Dec 2023 09:46:11 +0000 (10:46 +0100)]
arm64: dts: qcom: Add missing vio-supply for AW2013
Add the missing vio-supply to all usages of the AW2013 LED controller
to ensure that the regulator needed for pull-up of the interrupt and
I2C lines is really turned on. While this seems to have worked fine so
far some of these regulators are not guaranteed to be always-on. For
example, pm8916_l6 is typically turned off together with the display
if there aren't any other devices (e.g. sensors) keeping it always-on.
Enable the UFS phy and controller so that we can access the internal
storage of the phone.
At the same time we need to bump the minimum voltage used for UFS VCC,
otherwise it doesn't initialize properly. The 2.952V is taken from the
vcc-voltage-level property downstream.
See also the following link for more information about the VCCQ/VCCQ2:
https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/1590a3739e7dc29d2597307881553236d492f188/fp5/yupik-idp-pm7250b.dtsi#207
Luca Weiss [Sat, 25 Nov 2023 12:19:27 +0000 (13:19 +0100)]
arm64: dts: qcom: msm8953: Set initial address for memory
The dtbs_check really doesn't like having memory without reg set.
The base address depends on the amount of RAM you have:
<= 2.00 GiB RAM: 0x80000000
= 3.00 GiB RAM: 0x40000000
= 3.75 GiB RAM: 0x10000000
(more does not fit into the 32-bit physical address space)
So, let's pick one of the values, 0x10000000 which is used on devices
with 3.75 GiB RAM. Since the bootloader will update it to what's present
on the device it doesn't matter too much.
Nitin Rawat [Tue, 5 Dec 2023 14:38:55 +0000 (15:38 +0100)]
arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc
Add UFS host controller and PHY nodes for sc7280 soc.
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[luca: various cleanups and additions as written in the cover letter] Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231205-sc7280-ufs-v6-2-ad6ca7796de7@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Rajendra Nayak [Tue, 5 Dec 2023 06:24:01 +0000 (11:54 +0530)]
arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts
Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for
X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers,
geni UART, interrupt controller, TLMM, reserved memory, interconnects,
SMMU and LLCC nodes.
Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205062403.14848-4-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Now interconnect dependent devices are added in sm8650 DTSI,
now enable more devices for the Qualcomm SM8650 QRD board:
- PCIe
- Display
- DSPs
- SDCard
- UFS
- USB role switch with PMIC Glink
- Bluetooth
Now interconnect dependent devices are added in sm8650 DTSI,
now enable more devices for the Qualcomm SM8650 MTP board:
- PCIe
- Display
- DSPs
- SDCard
- UFS
- USB role switch with PMIC Glink
Johan Hovold [Mon, 20 Nov 2023 16:43:31 +0000 (17:43 +0100)]
arm64: dts: qcom: sm8550: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Note that only triggering on rising edges can be used to detect resume
events but not disconnect events.
Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231120164331.8116-12-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Johan Hovold [Mon, 20 Nov 2023 16:43:30 +0000 (17:43 +0100)]
arm64: dts: qcom: sm8150: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Fixes: 0c9dde0d2015 ("arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes") Fixes: b33d2868e8d3 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes") Cc: stable@vger.kernel.org # 5.10 Cc: Jonathan Marek <jonathan@marek.ca> Cc: Jack Pham <quic_jackp@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Jack Pham <quic_jackp@quicinc.com> Link: https://lore.kernel.org/r/20231120164331.8116-11-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Johan Hovold [Mon, 20 Nov 2023 16:43:29 +0000 (17:43 +0100)]
arm64: dts: qcom: sm6375: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Cc: stable@vger.kernel.org # 6.2 Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231120164331.8116-10-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Johan Hovold [Mon, 20 Nov 2023 16:43:28 +0000 (17:43 +0100)]
arm64: dts: qcom: sdm845: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Johan Hovold [Mon, 20 Nov 2023 16:43:27 +0000 (17:43 +0100)]
arm64: dts: qcom: sdm670: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Fixes: 07c8ded6e373 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Cc: stable@vger.kernel.org # 6.2 Cc: Richard Acayan <mailingradian@gmail.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20231120164331.8116-8-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Johan Hovold [Mon, 20 Nov 2023 16:43:26 +0000 (17:43 +0100)]
arm64: dts: qcom: sc8180x: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Fixes: b080f53a8f44 ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes") Cc: stable@vger.kernel.org # 6.5 Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231120164331.8116-7-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Note that only triggering on rising edges can be used to detect resume
events but not disconnect events.
Johan Hovold [Mon, 20 Nov 2023 16:43:23 +0000 (17:43 +0100)]
arm64: dts: qcom: sc7180: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Cc: stable@vger.kernel.org # 5.10 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20231120164331.8116-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Johan Hovold [Mon, 20 Nov 2023 16:43:22 +0000 (17:43 +0100)]
arm64: dts: qcom: sa8775p: fix USB wakeup interrupt types
The DP/DM wakeup interrupts are edge triggered and which edge to trigger
on depends on use-case and whether a Low speed or Full/High speed device
is connected.
Note that only triggering on rising edges can be used to detect resume
events but not disconnect events.
Fixes: de1001525c1a ("arm64: dts: qcom: sa8775p: add USB nodes") Cc: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20231120164331.8116-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Konrad Dybcio [Mon, 20 Nov 2023 12:12:53 +0000 (13:12 +0100)]
arm64: dts: qcom: sc7280: Fix up GPU SIDs
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access will hang the board.
The current settings are functionally identical, *but* due to what is
likely hardcoded security policies, the secure firmware rejects them,
resulting in the board hanging. To avoid that, alter the settings such
that SID 0 and 1 are described separately.
Rohit Agarwal [Fri, 17 Nov 2023 08:07:35 +0000 (13:37 +0530)]
arm64: dts: qcom: Add interconnect nodes for SDX75
Add interconnect nodes to support interconnects on SDX75.
Also parallely add the interconnect property for UART required
so that the bootup to shell does not break with interconnects
in place.
Nia Espera [Sat, 11 Nov 2023 22:07:42 +0000 (23:07 +0100)]
arm64: dts: qcom: sm8350: Fix remoteproc interrupt type
In a similar vein to
https://lore.kernel.org/lkml/20220530080842.37024-3-manivannan.sadhasivam@linaro.org/,
the remote processors on sm8350 fail to initialize with the 'correct'
(i.e., specified in downstream) IRQ type. Change this to EDGE_RISING.
The Samsung S6SY761 touchscreen bindings expect AVDD regulator which is
missing in the Sony Xperia PDX225 DTS. There is however pinctrl setting
for in the touchscreen device node with similar name: "avdd", so assume
author wanted to control a fixed regulator with a GPIO.
This fixes dtbs_check warning:
sm6375-sony-xperia-murray-pdx225.dtb: touchscreen@48: 'avdd-supply' is a required property
arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller
Add interrupts to SM6125 DWC3 USB controller, based on downstream/vendor
code of Trinket DTSI from Xiaomi Laurel device, to fix dtbs_check
warnings:
sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'interrupt-names' is a required property
sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'oneOf' conditional failed, one must be fixed:
'interrupts' is a required property
'interrupts-extended' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20231111164229.63803-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sm6115: align mem timer size cells with bindings
Commit 70d1e09ebf19 ("arm64: dts: qcom: sm6115: Use 64 bit addressing")
converted all addresses to 64-bit addressing, but the ARMv7 memory
mapped architected timer bindings expect sizes up to 32-bit. Keep
64-bit addressing but change size of memory mapping to 32-bit
(size-cells=1) and adjust the ranges to match this.
This fixes dtbs_check warnings like:
sm6115p-lenovo-j606f.dtb: timer@f120000: #size-cells:0:0: 1 was expected
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